1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 #include <linux/reset.h> 16 17 #include "xhci.h" 18 #include "xhci-trace.h" 19 #include "xhci-pci.h" 20 21 #define SSIC_PORT_NUM 2 22 #define SSIC_PORT_CFG2 0x880c 23 #define SSIC_PORT_CFG2_OFFSET 0x30 24 #define PROG_DONE (1 << 30) 25 #define SSIC_PORT_UNUSED (1 << 31) 26 #define SPARSE_DISABLE_BIT 17 27 #define SPARSE_CNTL_ENABLE 0xC12C 28 29 /* Device for a quirk */ 30 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 31 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 32 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100 34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 35 36 #define PCI_VENDOR_ID_ETRON 0x1b6f 37 #define PCI_DEVICE_ID_EJ168 0x7023 38 39 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 40 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 41 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 42 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 43 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 44 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 45 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 46 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 47 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 48 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 49 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 50 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1 52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 53 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 54 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 55 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 56 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 57 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 58 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af 59 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13 60 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138 61 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI 0x461e 62 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_XHCI 0x464e 63 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed 64 65 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639 66 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 67 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 68 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 69 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 70 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_1 0x161a 71 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_2 0x161b 72 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_3 0x161d 73 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_4 0x161e 74 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_5 0x15d6 75 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_6 0x15d7 76 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_7 0x161c 77 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_8 0x161f 78 79 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042 80 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 81 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242 82 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142 83 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242 84 85 static const char hcd_name[] = "xhci_hcd"; 86 87 static struct hc_driver __read_mostly xhci_pci_hc_driver; 88 89 static int xhci_pci_setup(struct usb_hcd *hcd); 90 91 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 92 .reset = xhci_pci_setup, 93 }; 94 95 /* called after powerup, by probe or system-pm "wakeup" */ 96 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 97 { 98 /* 99 * TODO: Implement finding debug ports later. 100 * TODO: see if there are any quirks that need to be added to handle 101 * new extended capabilities. 102 */ 103 104 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 105 if (!pci_set_mwi(pdev)) 106 xhci_dbg(xhci, "MWI active\n"); 107 108 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 109 return 0; 110 } 111 112 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 113 { 114 struct pci_dev *pdev = to_pci_dev(dev); 115 struct xhci_driver_data *driver_data; 116 const struct pci_device_id *id; 117 118 id = pci_match_id(to_pci_driver(pdev->dev.driver)->id_table, pdev); 119 120 if (id && id->driver_data) { 121 driver_data = (struct xhci_driver_data *)id->driver_data; 122 xhci->quirks |= driver_data->quirks; 123 } 124 125 /* Look for vendor-specific quirks */ 126 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 127 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 128 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 129 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 130 pdev->revision == 0x0) { 131 xhci->quirks |= XHCI_RESET_EP_QUIRK; 132 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 133 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated"); 134 } 135 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 136 pdev->revision == 0x4) { 137 xhci->quirks |= XHCI_SLOW_SUSPEND; 138 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 139 "QUIRK: Fresco Logic xHC revision %u" 140 "must be suspended extra slowly", 141 pdev->revision); 142 } 143 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 144 xhci->quirks |= XHCI_BROKEN_STREAMS; 145 /* Fresco Logic confirms: all revisions of this chip do not 146 * support MSI, even though some of them claim to in their PCI 147 * capabilities. 148 */ 149 xhci->quirks |= XHCI_BROKEN_MSI; 150 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 151 "QUIRK: Fresco Logic revision %u " 152 "has broken MSI implementation", 153 pdev->revision); 154 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 155 } 156 157 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 158 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 159 xhci->quirks |= XHCI_BROKEN_STREAMS; 160 161 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 162 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100) 163 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 164 165 if (pdev->vendor == PCI_VENDOR_ID_NEC) 166 xhci->quirks |= XHCI_NEC_HOST; 167 168 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 169 xhci->quirks |= XHCI_AMD_0x96_HOST; 170 171 /* AMD PLL quirk */ 172 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) 173 xhci->quirks |= XHCI_AMD_PLL_FIX; 174 175 if (pdev->vendor == PCI_VENDOR_ID_AMD && 176 (pdev->device == 0x145c || 177 pdev->device == 0x15e0 || 178 pdev->device == 0x15e1 || 179 pdev->device == 0x43bb)) 180 xhci->quirks |= XHCI_SUSPEND_DELAY; 181 182 if (pdev->vendor == PCI_VENDOR_ID_AMD && 183 (pdev->device == 0x15e0 || pdev->device == 0x15e1)) 184 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; 185 186 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) { 187 xhci->quirks |= XHCI_DISABLE_SPARSE; 188 xhci->quirks |= XHCI_RESET_ON_RESUME; 189 } 190 191 if (pdev->vendor == PCI_VENDOR_ID_AMD) 192 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 193 194 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 195 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 196 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 197 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 198 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 199 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 200 201 if (pdev->vendor == PCI_VENDOR_ID_AMD && 202 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) 203 xhci->quirks |= XHCI_BROKEN_D3COLD; 204 205 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 206 xhci->quirks |= XHCI_LPM_SUPPORT; 207 xhci->quirks |= XHCI_INTEL_HOST; 208 xhci->quirks |= XHCI_AVOID_BEI; 209 } 210 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 211 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 212 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 213 xhci->limit_active_eps = 64; 214 xhci->quirks |= XHCI_SW_BW_CHECKING; 215 /* 216 * PPT desktop boards DH77EB and DH77DF will power back on after 217 * a few seconds of being shutdown. The fix for this is to 218 * switch the ports from xHCI to EHCI on shutdown. We can't use 219 * DMI information to find those particular boards (since each 220 * vendor will change the board name), so we have to key off all 221 * PPT chipsets. 222 */ 223 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 224 } 225 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 226 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 227 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 228 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 229 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 230 } 231 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 232 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 233 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 234 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 235 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 236 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 237 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 238 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI || 239 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) { 240 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 241 } 242 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 243 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 244 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 245 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 246 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 247 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 248 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI)) 249 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 250 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 251 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 252 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 253 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 254 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 255 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) 256 xhci->quirks |= XHCI_MISSING_CAS; 257 258 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 259 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 260 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 261 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI || 262 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 263 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 264 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 265 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 266 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || 267 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI || 268 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI || 269 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI || 270 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI || 271 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_XHCI || 272 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI)) 273 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 274 275 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 276 pdev->device == PCI_DEVICE_ID_EJ168) { 277 xhci->quirks |= XHCI_RESET_ON_RESUME; 278 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 279 xhci->quirks |= XHCI_BROKEN_STREAMS; 280 } 281 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 282 pdev->device == 0x0014) { 283 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 284 xhci->quirks |= XHCI_ZERO_64B_REGS; 285 } 286 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 287 pdev->device == 0x0015) { 288 xhci->quirks |= XHCI_RESET_ON_RESUME; 289 xhci->quirks |= XHCI_ZERO_64B_REGS; 290 } 291 if (pdev->vendor == PCI_VENDOR_ID_VIA) 292 xhci->quirks |= XHCI_RESET_ON_RESUME; 293 294 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 295 if (pdev->vendor == PCI_VENDOR_ID_VIA && 296 pdev->device == 0x3432) 297 xhci->quirks |= XHCI_BROKEN_STREAMS; 298 299 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) { 300 xhci->quirks |= XHCI_LPM_SUPPORT; 301 xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS; 302 } 303 304 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 305 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) 306 xhci->quirks |= XHCI_BROKEN_STREAMS; 307 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 308 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) { 309 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 310 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 311 } 312 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 313 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI || 314 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI || 315 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI)) 316 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 317 318 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 319 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 320 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 321 322 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 323 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 324 325 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 326 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 327 pdev->device == 0x9026) 328 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 329 330 if (pdev->vendor == PCI_VENDOR_ID_AMD && 331 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 || 332 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4)) 333 xhci->quirks |= XHCI_NO_SOFT_RETRY; 334 335 if (pdev->vendor == PCI_VENDOR_ID_AMD && 336 (pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_1 || 337 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_2 || 338 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_3 || 339 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_4 || 340 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_5 || 341 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_6 || 342 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_7 || 343 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_8)) 344 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 345 346 if (xhci->quirks & XHCI_RESET_ON_RESUME) 347 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 348 "QUIRK: Resetting on resume"); 349 } 350 351 #ifdef CONFIG_ACPI 352 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 353 { 354 static const guid_t intel_dsm_guid = 355 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 356 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 357 union acpi_object *obj; 358 359 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 360 NULL); 361 ACPI_FREE(obj); 362 } 363 #else 364 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 365 #endif /* CONFIG_ACPI */ 366 367 /* called during probe() after chip reset completes */ 368 static int xhci_pci_setup(struct usb_hcd *hcd) 369 { 370 struct xhci_hcd *xhci; 371 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 372 int retval; 373 374 xhci = hcd_to_xhci(hcd); 375 if (!xhci->sbrn) 376 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 377 378 /* imod_interval is the interrupt moderation value in nanoseconds. */ 379 xhci->imod_interval = 40000; 380 381 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 382 if (retval) 383 return retval; 384 385 if (!usb_hcd_is_primary_hcd(hcd)) 386 return 0; 387 388 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 389 xhci_pme_acpi_rtd3_enable(pdev); 390 391 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 392 393 /* Find any debug ports */ 394 return xhci_pci_reinit(xhci, pdev); 395 } 396 397 /* 398 * We need to register our own PCI probe function (instead of the USB core's 399 * function) in order to create a second roothub under xHCI. 400 */ 401 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 402 { 403 int retval; 404 struct xhci_hcd *xhci; 405 struct usb_hcd *hcd; 406 struct xhci_driver_data *driver_data; 407 struct reset_control *reset; 408 409 driver_data = (struct xhci_driver_data *)id->driver_data; 410 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) { 411 retval = renesas_xhci_check_request_fw(dev, id); 412 if (retval) 413 return retval; 414 } 415 416 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 417 if (IS_ERR(reset)) 418 return PTR_ERR(reset); 419 reset_control_reset(reset); 420 421 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 422 pm_runtime_get_noresume(&dev->dev); 423 424 /* Register the USB 2.0 roothub. 425 * FIXME: USB core must know to register the USB 2.0 roothub first. 426 * This is sort of silly, because we could just set the HCD driver flags 427 * to say USB 2.0, but I'm not sure what the implications would be in 428 * the other parts of the HCD code. 429 */ 430 retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver); 431 432 if (retval) 433 goto put_runtime_pm; 434 435 /* USB 2.0 roothub is stored in the PCI device now. */ 436 hcd = dev_get_drvdata(&dev->dev); 437 xhci = hcd_to_xhci(hcd); 438 xhci->reset = reset; 439 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev, 440 pci_name(dev), hcd); 441 if (!xhci->shared_hcd) { 442 retval = -ENOMEM; 443 goto dealloc_usb2_hcd; 444 } 445 446 retval = xhci_ext_cap_init(xhci); 447 if (retval) 448 goto put_usb3_hcd; 449 450 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 451 IRQF_SHARED); 452 if (retval) 453 goto put_usb3_hcd; 454 /* Roothub already marked as USB 3.0 speed */ 455 456 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 457 HCC_MAX_PSA(xhci->hcc_params) >= 4) 458 xhci->shared_hcd->can_do_streams = 1; 459 460 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 461 pm_runtime_put_noidle(&dev->dev); 462 463 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 464 pm_runtime_allow(&dev->dev); 465 466 return 0; 467 468 put_usb3_hcd: 469 usb_put_hcd(xhci->shared_hcd); 470 dealloc_usb2_hcd: 471 usb_hcd_pci_remove(dev); 472 put_runtime_pm: 473 pm_runtime_put_noidle(&dev->dev); 474 return retval; 475 } 476 477 static void xhci_pci_remove(struct pci_dev *dev) 478 { 479 struct xhci_hcd *xhci; 480 481 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 482 483 xhci->xhc_state |= XHCI_STATE_REMOVING; 484 485 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 486 pm_runtime_forbid(&dev->dev); 487 488 if (xhci->shared_hcd) { 489 usb_remove_hcd(xhci->shared_hcd); 490 usb_put_hcd(xhci->shared_hcd); 491 xhci->shared_hcd = NULL; 492 } 493 494 /* Workaround for spurious wakeups at shutdown with HSW */ 495 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 496 pci_set_power_state(dev, PCI_D3hot); 497 498 usb_hcd_pci_remove(dev); 499 } 500 501 #ifdef CONFIG_PM 502 /* 503 * In some Intel xHCI controllers, in order to get D3 working, 504 * through a vendor specific SSIC CONFIG register at offset 0x883c, 505 * SSIC PORT need to be marked as "unused" before putting xHCI 506 * into D3. After D3 exit, the SSIC port need to be marked as "used". 507 * Without this change, xHCI might not enter D3 state. 508 */ 509 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 510 { 511 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 512 u32 val; 513 void __iomem *reg; 514 int i; 515 516 for (i = 0; i < SSIC_PORT_NUM; i++) { 517 reg = (void __iomem *) xhci->cap_regs + 518 SSIC_PORT_CFG2 + 519 i * SSIC_PORT_CFG2_OFFSET; 520 521 /* Notify SSIC that SSIC profile programming is not done. */ 522 val = readl(reg) & ~PROG_DONE; 523 writel(val, reg); 524 525 /* Mark SSIC port as unused(suspend) or used(resume) */ 526 val = readl(reg); 527 if (suspend) 528 val |= SSIC_PORT_UNUSED; 529 else 530 val &= ~SSIC_PORT_UNUSED; 531 writel(val, reg); 532 533 /* Notify SSIC that SSIC profile programming is done */ 534 val = readl(reg) | PROG_DONE; 535 writel(val, reg); 536 readl(reg); 537 } 538 } 539 540 /* 541 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 542 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 543 */ 544 static void xhci_pme_quirk(struct usb_hcd *hcd) 545 { 546 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 547 void __iomem *reg; 548 u32 val; 549 550 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 551 val = readl(reg); 552 writel(val | BIT(28), reg); 553 readl(reg); 554 } 555 556 static void xhci_sparse_control_quirk(struct usb_hcd *hcd) 557 { 558 u32 reg; 559 560 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE); 561 reg &= ~BIT(SPARSE_DISABLE_BIT); 562 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE); 563 } 564 565 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 566 { 567 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 568 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 569 int ret; 570 571 /* 572 * Systems with the TI redriver that loses port status change events 573 * need to have the registers polled during D3, so avoid D3cold. 574 */ 575 if (xhci->quirks & (XHCI_COMP_MODE_QUIRK | XHCI_BROKEN_D3COLD)) 576 pci_d3cold_disable(pdev); 577 578 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 579 xhci_pme_quirk(hcd); 580 581 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 582 xhci_ssic_port_unused_quirk(hcd, true); 583 584 if (xhci->quirks & XHCI_DISABLE_SPARSE) 585 xhci_sparse_control_quirk(hcd); 586 587 ret = xhci_suspend(xhci, do_wakeup); 588 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 589 xhci_ssic_port_unused_quirk(hcd, false); 590 591 return ret; 592 } 593 594 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 595 { 596 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 597 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 598 int retval = 0; 599 600 reset_control_reset(xhci->reset); 601 602 /* The BIOS on systems with the Intel Panther Point chipset may or may 603 * not support xHCI natively. That means that during system resume, it 604 * may switch the ports back to EHCI so that users can use their 605 * keyboard to select a kernel from GRUB after resume from hibernate. 606 * 607 * The BIOS is supposed to remember whether the OS had xHCI ports 608 * enabled before resume, and switch the ports back to xHCI when the 609 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 610 * writers. 611 * 612 * Unconditionally switch the ports back to xHCI after a system resume. 613 * It should not matter whether the EHCI or xHCI controller is 614 * resumed first. It's enough to do the switchover in xHCI because 615 * USB core won't notice anything as the hub driver doesn't start 616 * running again until after all the devices (including both EHCI and 617 * xHCI host controllers) have been resumed. 618 */ 619 620 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 621 usb_enable_intel_xhci_ports(pdev); 622 623 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 624 xhci_ssic_port_unused_quirk(hcd, false); 625 626 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 627 xhci_pme_quirk(hcd); 628 629 retval = xhci_resume(xhci, hibernated); 630 return retval; 631 } 632 633 static void xhci_pci_shutdown(struct usb_hcd *hcd) 634 { 635 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 636 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 637 638 xhci_shutdown(hcd); 639 640 /* Yet another workaround for spurious wakeups at shutdown with HSW */ 641 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 642 pci_set_power_state(pdev, PCI_D3hot); 643 } 644 #endif /* CONFIG_PM */ 645 646 /*-------------------------------------------------------------------------*/ 647 648 static const struct xhci_driver_data reneses_data = { 649 .quirks = XHCI_RENESAS_FW_QUIRK, 650 .firmware = "renesas_usb_fw.mem", 651 }; 652 653 /* PCI driver selection metadata; PCI hotplugging uses this */ 654 static const struct pci_device_id pci_ids[] = { 655 { PCI_DEVICE(0x1912, 0x0014), 656 .driver_data = (unsigned long)&reneses_data, 657 }, 658 { PCI_DEVICE(0x1912, 0x0015), 659 .driver_data = (unsigned long)&reneses_data, 660 }, 661 /* handle any USB 3.0 xHCI controller */ 662 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 663 }, 664 { /* end: all zeroes */ } 665 }; 666 MODULE_DEVICE_TABLE(pci, pci_ids); 667 668 /* 669 * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't 670 * load firmware, so don't encumber the xhci-pci driver with it. 671 */ 672 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS) 673 MODULE_FIRMWARE("renesas_usb_fw.mem"); 674 #endif 675 676 /* pci driver glue; this is a "new style" PCI driver module */ 677 static struct pci_driver xhci_pci_driver = { 678 .name = hcd_name, 679 .id_table = pci_ids, 680 681 .probe = xhci_pci_probe, 682 .remove = xhci_pci_remove, 683 /* suspend and resume implemented later */ 684 685 .shutdown = usb_hcd_pci_shutdown, 686 #ifdef CONFIG_PM 687 .driver = { 688 .pm = &usb_hcd_pci_pm_ops 689 }, 690 #endif 691 }; 692 693 static int __init xhci_pci_init(void) 694 { 695 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 696 #ifdef CONFIG_PM 697 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend; 698 xhci_pci_hc_driver.pci_resume = xhci_pci_resume; 699 xhci_pci_hc_driver.shutdown = xhci_pci_shutdown; 700 #endif 701 return pci_register_driver(&xhci_pci_driver); 702 } 703 module_init(xhci_pci_init); 704 705 static void __exit xhci_pci_exit(void) 706 { 707 pci_unregister_driver(&xhci_pci_driver); 708 } 709 module_exit(xhci_pci_exit); 710 711 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 712 MODULE_LICENSE("GPL"); 713