1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 16 #include "xhci.h" 17 #include "xhci-trace.h" 18 19 #define SSIC_PORT_NUM 2 20 #define SSIC_PORT_CFG2 0x880c 21 #define SSIC_PORT_CFG2_OFFSET 0x30 22 #define PROG_DONE (1 << 30) 23 #define SSIC_PORT_UNUSED (1 << 31) 24 25 /* Device for a quirk */ 26 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 27 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 28 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 29 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 30 31 #define PCI_VENDOR_ID_ETRON 0x1b6f 32 #define PCI_DEVICE_ID_EJ168 0x7023 33 34 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 35 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 36 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 37 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 38 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 39 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 40 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 41 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 42 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 43 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 44 45 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 46 47 static const char hcd_name[] = "xhci_hcd"; 48 49 static struct hc_driver __read_mostly xhci_pci_hc_driver; 50 51 static int xhci_pci_setup(struct usb_hcd *hcd); 52 53 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 54 .reset = xhci_pci_setup, 55 }; 56 57 /* called after powerup, by probe or system-pm "wakeup" */ 58 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 59 { 60 /* 61 * TODO: Implement finding debug ports later. 62 * TODO: see if there are any quirks that need to be added to handle 63 * new extended capabilities. 64 */ 65 66 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 67 if (!pci_set_mwi(pdev)) 68 xhci_dbg(xhci, "MWI active\n"); 69 70 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 71 return 0; 72 } 73 74 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 75 { 76 struct pci_dev *pdev = to_pci_dev(dev); 77 78 /* Look for vendor-specific quirks */ 79 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 80 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 81 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 82 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 83 pdev->revision == 0x0) { 84 xhci->quirks |= XHCI_RESET_EP_QUIRK; 85 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 86 "QUIRK: Fresco Logic xHC needs configure" 87 " endpoint cmd after reset endpoint"); 88 } 89 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 90 pdev->revision == 0x4) { 91 xhci->quirks |= XHCI_SLOW_SUSPEND; 92 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 93 "QUIRK: Fresco Logic xHC revision %u" 94 "must be suspended extra slowly", 95 pdev->revision); 96 } 97 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 98 xhci->quirks |= XHCI_BROKEN_STREAMS; 99 /* Fresco Logic confirms: all revisions of this chip do not 100 * support MSI, even though some of them claim to in their PCI 101 * capabilities. 102 */ 103 xhci->quirks |= XHCI_BROKEN_MSI; 104 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 105 "QUIRK: Fresco Logic revision %u " 106 "has broken MSI implementation", 107 pdev->revision); 108 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 109 } 110 111 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 112 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 113 xhci->quirks |= XHCI_BROKEN_STREAMS; 114 115 if (pdev->vendor == PCI_VENDOR_ID_NEC) 116 xhci->quirks |= XHCI_NEC_HOST; 117 118 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 119 xhci->quirks |= XHCI_AMD_0x96_HOST; 120 121 /* AMD PLL quirk */ 122 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info()) 123 xhci->quirks |= XHCI_AMD_PLL_FIX; 124 125 if (pdev->vendor == PCI_VENDOR_ID_AMD) 126 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 127 128 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 129 xhci->quirks |= XHCI_LPM_SUPPORT; 130 xhci->quirks |= XHCI_INTEL_HOST; 131 xhci->quirks |= XHCI_AVOID_BEI; 132 } 133 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 134 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 135 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 136 xhci->limit_active_eps = 64; 137 xhci->quirks |= XHCI_SW_BW_CHECKING; 138 /* 139 * PPT desktop boards DH77EB and DH77DF will power back on after 140 * a few seconds of being shutdown. The fix for this is to 141 * switch the ports from xHCI to EHCI on shutdown. We can't use 142 * DMI information to find those particular boards (since each 143 * vendor will change the board name), so we have to key off all 144 * PPT chipsets. 145 */ 146 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 147 } 148 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 149 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 150 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 151 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 152 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 153 } 154 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 155 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 156 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 157 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 158 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 159 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 160 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 161 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) { 162 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 163 } 164 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 165 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) { 166 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 167 } 168 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 169 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 170 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 171 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) 172 xhci->quirks |= XHCI_MISSING_CAS; 173 174 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 175 pdev->device == PCI_DEVICE_ID_EJ168) { 176 xhci->quirks |= XHCI_RESET_ON_RESUME; 177 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 178 xhci->quirks |= XHCI_BROKEN_STREAMS; 179 } 180 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 181 pdev->device == 0x0015) 182 xhci->quirks |= XHCI_RESET_ON_RESUME; 183 if (pdev->vendor == PCI_VENDOR_ID_VIA) 184 xhci->quirks |= XHCI_RESET_ON_RESUME; 185 186 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 187 if (pdev->vendor == PCI_VENDOR_ID_VIA && 188 pdev->device == 0x3432) 189 xhci->quirks |= XHCI_BROKEN_STREAMS; 190 191 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 192 pdev->device == 0x1042) 193 xhci->quirks |= XHCI_BROKEN_STREAMS; 194 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 195 pdev->device == 0x1142) 196 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 197 198 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 199 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 200 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 201 202 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 203 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 204 205 if (xhci->quirks & XHCI_RESET_ON_RESUME) 206 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 207 "QUIRK: Resetting on resume"); 208 } 209 210 #ifdef CONFIG_ACPI 211 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 212 { 213 static const guid_t intel_dsm_guid = 214 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 215 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 216 union acpi_object *obj; 217 218 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 219 NULL); 220 ACPI_FREE(obj); 221 } 222 #else 223 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 224 #endif /* CONFIG_ACPI */ 225 226 /* called during probe() after chip reset completes */ 227 static int xhci_pci_setup(struct usb_hcd *hcd) 228 { 229 struct xhci_hcd *xhci; 230 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 231 int retval; 232 233 xhci = hcd_to_xhci(hcd); 234 if (!xhci->sbrn) 235 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 236 237 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 238 if (retval) 239 return retval; 240 241 if (!usb_hcd_is_primary_hcd(hcd)) 242 return 0; 243 244 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 245 246 /* Find any debug ports */ 247 return xhci_pci_reinit(xhci, pdev); 248 } 249 250 /* 251 * We need to register our own PCI probe function (instead of the USB core's 252 * function) in order to create a second roothub under xHCI. 253 */ 254 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 255 { 256 int retval; 257 struct xhci_hcd *xhci; 258 struct hc_driver *driver; 259 struct usb_hcd *hcd; 260 261 driver = (struct hc_driver *)id->driver_data; 262 263 /* For some HW implementation, a XHCI reset is just not enough... */ 264 if (usb_xhci_needs_pci_reset(dev)) { 265 dev_info(&dev->dev, "Resetting\n"); 266 if (pci_reset_function_locked(dev)) 267 dev_warn(&dev->dev, "Reset failed"); 268 } 269 270 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 271 pm_runtime_get_noresume(&dev->dev); 272 273 /* Register the USB 2.0 roothub. 274 * FIXME: USB core must know to register the USB 2.0 roothub first. 275 * This is sort of silly, because we could just set the HCD driver flags 276 * to say USB 2.0, but I'm not sure what the implications would be in 277 * the other parts of the HCD code. 278 */ 279 retval = usb_hcd_pci_probe(dev, id); 280 281 if (retval) 282 goto put_runtime_pm; 283 284 /* USB 2.0 roothub is stored in the PCI device now. */ 285 hcd = dev_get_drvdata(&dev->dev); 286 xhci = hcd_to_xhci(hcd); 287 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, 288 pci_name(dev), hcd); 289 if (!xhci->shared_hcd) { 290 retval = -ENOMEM; 291 goto dealloc_usb2_hcd; 292 } 293 294 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 295 IRQF_SHARED); 296 if (retval) 297 goto put_usb3_hcd; 298 /* Roothub already marked as USB 3.0 speed */ 299 300 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 301 HCC_MAX_PSA(xhci->hcc_params) >= 4) 302 xhci->shared_hcd->can_do_streams = 1; 303 304 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 305 xhci_pme_acpi_rtd3_enable(dev); 306 307 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 308 pm_runtime_put_noidle(&dev->dev); 309 310 return 0; 311 312 put_usb3_hcd: 313 usb_put_hcd(xhci->shared_hcd); 314 dealloc_usb2_hcd: 315 usb_hcd_pci_remove(dev); 316 put_runtime_pm: 317 pm_runtime_put_noidle(&dev->dev); 318 return retval; 319 } 320 321 static void xhci_pci_remove(struct pci_dev *dev) 322 { 323 struct xhci_hcd *xhci; 324 325 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 326 xhci->xhc_state |= XHCI_STATE_REMOVING; 327 if (xhci->shared_hcd) { 328 usb_remove_hcd(xhci->shared_hcd); 329 usb_put_hcd(xhci->shared_hcd); 330 } 331 332 /* Workaround for spurious wakeups at shutdown with HSW */ 333 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 334 pci_set_power_state(dev, PCI_D3hot); 335 336 usb_hcd_pci_remove(dev); 337 } 338 339 #ifdef CONFIG_PM 340 /* 341 * In some Intel xHCI controllers, in order to get D3 working, 342 * through a vendor specific SSIC CONFIG register at offset 0x883c, 343 * SSIC PORT need to be marked as "unused" before putting xHCI 344 * into D3. After D3 exit, the SSIC port need to be marked as "used". 345 * Without this change, xHCI might not enter D3 state. 346 */ 347 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 348 { 349 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 350 u32 val; 351 void __iomem *reg; 352 int i; 353 354 for (i = 0; i < SSIC_PORT_NUM; i++) { 355 reg = (void __iomem *) xhci->cap_regs + 356 SSIC_PORT_CFG2 + 357 i * SSIC_PORT_CFG2_OFFSET; 358 359 /* Notify SSIC that SSIC profile programming is not done. */ 360 val = readl(reg) & ~PROG_DONE; 361 writel(val, reg); 362 363 /* Mark SSIC port as unused(suspend) or used(resume) */ 364 val = readl(reg); 365 if (suspend) 366 val |= SSIC_PORT_UNUSED; 367 else 368 val &= ~SSIC_PORT_UNUSED; 369 writel(val, reg); 370 371 /* Notify SSIC that SSIC profile programming is done */ 372 val = readl(reg) | PROG_DONE; 373 writel(val, reg); 374 readl(reg); 375 } 376 } 377 378 /* 379 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 380 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 381 */ 382 static void xhci_pme_quirk(struct usb_hcd *hcd) 383 { 384 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 385 void __iomem *reg; 386 u32 val; 387 388 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 389 val = readl(reg); 390 writel(val | BIT(28), reg); 391 readl(reg); 392 } 393 394 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 395 { 396 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 397 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 398 int ret; 399 400 /* 401 * Systems with the TI redriver that loses port status change events 402 * need to have the registers polled during D3, so avoid D3cold. 403 */ 404 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 405 pci_d3cold_disable(pdev); 406 407 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 408 xhci_pme_quirk(hcd); 409 410 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 411 xhci_ssic_port_unused_quirk(hcd, true); 412 413 ret = xhci_suspend(xhci, do_wakeup); 414 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 415 xhci_ssic_port_unused_quirk(hcd, false); 416 417 return ret; 418 } 419 420 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 421 { 422 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 423 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 424 int retval = 0; 425 426 /* The BIOS on systems with the Intel Panther Point chipset may or may 427 * not support xHCI natively. That means that during system resume, it 428 * may switch the ports back to EHCI so that users can use their 429 * keyboard to select a kernel from GRUB after resume from hibernate. 430 * 431 * The BIOS is supposed to remember whether the OS had xHCI ports 432 * enabled before resume, and switch the ports back to xHCI when the 433 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 434 * writers. 435 * 436 * Unconditionally switch the ports back to xHCI after a system resume. 437 * It should not matter whether the EHCI or xHCI controller is 438 * resumed first. It's enough to do the switchover in xHCI because 439 * USB core won't notice anything as the hub driver doesn't start 440 * running again until after all the devices (including both EHCI and 441 * xHCI host controllers) have been resumed. 442 */ 443 444 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 445 usb_enable_intel_xhci_ports(pdev); 446 447 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 448 xhci_ssic_port_unused_quirk(hcd, false); 449 450 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 451 xhci_pme_quirk(hcd); 452 453 retval = xhci_resume(xhci, hibernated); 454 return retval; 455 } 456 #endif /* CONFIG_PM */ 457 458 /*-------------------------------------------------------------------------*/ 459 460 /* PCI driver selection metadata; PCI hotplugging uses this */ 461 static const struct pci_device_id pci_ids[] = { { 462 /* handle any USB 3.0 xHCI controller */ 463 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 464 .driver_data = (unsigned long) &xhci_pci_hc_driver, 465 }, 466 { /* end: all zeroes */ } 467 }; 468 MODULE_DEVICE_TABLE(pci, pci_ids); 469 470 /* pci driver glue; this is a "new style" PCI driver module */ 471 static struct pci_driver xhci_pci_driver = { 472 .name = (char *) hcd_name, 473 .id_table = pci_ids, 474 475 .probe = xhci_pci_probe, 476 .remove = xhci_pci_remove, 477 /* suspend and resume implemented later */ 478 479 .shutdown = usb_hcd_pci_shutdown, 480 #ifdef CONFIG_PM 481 .driver = { 482 .pm = &usb_hcd_pci_pm_ops 483 }, 484 #endif 485 }; 486 487 static int __init xhci_pci_init(void) 488 { 489 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 490 #ifdef CONFIG_PM 491 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend; 492 xhci_pci_hc_driver.pci_resume = xhci_pci_resume; 493 #endif 494 return pci_register_driver(&xhci_pci_driver); 495 } 496 module_init(xhci_pci_init); 497 498 static void __exit xhci_pci_exit(void) 499 { 500 pci_unregister_driver(&xhci_pci_driver); 501 } 502 module_exit(xhci_pci_exit); 503 504 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 505 MODULE_LICENSE("GPL"); 506