1 /* 2 * xHCI host controller driver PCI Bus Glue. 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/pci.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 27 #include "xhci.h" 28 29 /* Device for a quirk */ 30 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 31 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 32 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 33 34 #define PCI_VENDOR_ID_ETRON 0x1b6f 35 #define PCI_DEVICE_ID_ASROCK_P67 0x7023 36 37 static const char hcd_name[] = "xhci_hcd"; 38 39 /* called after powerup, by probe or system-pm "wakeup" */ 40 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 41 { 42 /* 43 * TODO: Implement finding debug ports later. 44 * TODO: see if there are any quirks that need to be added to handle 45 * new extended capabilities. 46 */ 47 48 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 49 if (!pci_set_mwi(pdev)) 50 xhci_dbg(xhci, "MWI active\n"); 51 52 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 53 return 0; 54 } 55 56 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 57 { 58 struct pci_dev *pdev = to_pci_dev(dev); 59 60 /* Look for vendor-specific quirks */ 61 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 62 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 63 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 64 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 65 pdev->revision == 0x0) { 66 xhci->quirks |= XHCI_RESET_EP_QUIRK; 67 xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure" 68 " endpoint cmd after reset endpoint\n"); 69 } 70 /* Fresco Logic confirms: all revisions of this chip do not 71 * support MSI, even though some of them claim to in their PCI 72 * capabilities. 73 */ 74 xhci->quirks |= XHCI_BROKEN_MSI; 75 xhci_dbg(xhci, "QUIRK: Fresco Logic revision %u " 76 "has broken MSI implementation\n", 77 pdev->revision); 78 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 79 } 80 81 if (pdev->vendor == PCI_VENDOR_ID_NEC) 82 xhci->quirks |= XHCI_NEC_HOST; 83 84 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 85 xhci->quirks |= XHCI_AMD_0x96_HOST; 86 87 /* AMD PLL quirk */ 88 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info()) 89 xhci->quirks |= XHCI_AMD_PLL_FIX; 90 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 91 xhci->quirks |= XHCI_LPM_SUPPORT; 92 xhci->quirks |= XHCI_INTEL_HOST; 93 } 94 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 95 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 96 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 97 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 98 xhci->limit_active_eps = 64; 99 xhci->quirks |= XHCI_SW_BW_CHECKING; 100 /* 101 * PPT desktop boards DH77EB and DH77DF will power back on after 102 * a few seconds of being shutdown. The fix for this is to 103 * switch the ports from xHCI to EHCI on shutdown. We can't use 104 * DMI information to find those particular boards (since each 105 * vendor will change the board name), so we have to key off all 106 * PPT chipsets. 107 */ 108 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 109 xhci->quirks |= XHCI_AVOID_BEI; 110 } 111 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 112 pdev->device == PCI_DEVICE_ID_ASROCK_P67) { 113 xhci->quirks |= XHCI_RESET_ON_RESUME; 114 xhci_dbg(xhci, "QUIRK: Resetting on resume\n"); 115 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 116 } 117 if (pdev->vendor == PCI_VENDOR_ID_VIA) 118 xhci->quirks |= XHCI_RESET_ON_RESUME; 119 } 120 121 /* called during probe() after chip reset completes */ 122 static int xhci_pci_setup(struct usb_hcd *hcd) 123 { 124 struct xhci_hcd *xhci; 125 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 126 int retval; 127 128 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 129 if (retval) 130 return retval; 131 132 xhci = hcd_to_xhci(hcd); 133 if (!usb_hcd_is_primary_hcd(hcd)) 134 return 0; 135 136 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 137 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 138 139 /* Find any debug ports */ 140 retval = xhci_pci_reinit(xhci, pdev); 141 if (!retval) 142 return retval; 143 144 kfree(xhci); 145 return retval; 146 } 147 148 /* 149 * We need to register our own PCI probe function (instead of the USB core's 150 * function) in order to create a second roothub under xHCI. 151 */ 152 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 153 { 154 int retval; 155 struct xhci_hcd *xhci; 156 struct hc_driver *driver; 157 struct usb_hcd *hcd; 158 159 driver = (struct hc_driver *)id->driver_data; 160 /* Register the USB 2.0 roothub. 161 * FIXME: USB core must know to register the USB 2.0 roothub first. 162 * This is sort of silly, because we could just set the HCD driver flags 163 * to say USB 2.0, but I'm not sure what the implications would be in 164 * the other parts of the HCD code. 165 */ 166 retval = usb_hcd_pci_probe(dev, id); 167 168 if (retval) 169 return retval; 170 171 /* USB 2.0 roothub is stored in the PCI device now. */ 172 hcd = dev_get_drvdata(&dev->dev); 173 xhci = hcd_to_xhci(hcd); 174 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, 175 pci_name(dev), hcd); 176 if (!xhci->shared_hcd) { 177 retval = -ENOMEM; 178 goto dealloc_usb2_hcd; 179 } 180 181 /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset) 182 * is called by usb_add_hcd(). 183 */ 184 *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci; 185 186 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 187 IRQF_SHARED); 188 if (retval) 189 goto put_usb3_hcd; 190 /* Roothub already marked as USB 3.0 speed */ 191 192 /* We know the LPM timeout algorithms for this host, let the USB core 193 * enable and disable LPM for devices under the USB 3.0 roothub. 194 */ 195 if (xhci->quirks & XHCI_LPM_SUPPORT) 196 hcd_to_bus(xhci->shared_hcd)->root_hub->lpm_capable = 1; 197 198 return 0; 199 200 put_usb3_hcd: 201 usb_put_hcd(xhci->shared_hcd); 202 dealloc_usb2_hcd: 203 usb_hcd_pci_remove(dev); 204 return retval; 205 } 206 207 static void xhci_pci_remove(struct pci_dev *dev) 208 { 209 struct xhci_hcd *xhci; 210 211 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 212 if (xhci->shared_hcd) { 213 usb_remove_hcd(xhci->shared_hcd); 214 usb_put_hcd(xhci->shared_hcd); 215 } 216 usb_hcd_pci_remove(dev); 217 kfree(xhci); 218 } 219 220 #ifdef CONFIG_PM 221 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 222 { 223 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 224 225 return xhci_suspend(xhci); 226 } 227 228 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 229 { 230 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 231 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 232 int retval = 0; 233 234 /* The BIOS on systems with the Intel Panther Point chipset may or may 235 * not support xHCI natively. That means that during system resume, it 236 * may switch the ports back to EHCI so that users can use their 237 * keyboard to select a kernel from GRUB after resume from hibernate. 238 * 239 * The BIOS is supposed to remember whether the OS had xHCI ports 240 * enabled before resume, and switch the ports back to xHCI when the 241 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 242 * writers. 243 * 244 * Unconditionally switch the ports back to xHCI after a system resume. 245 * We can't tell whether the EHCI or xHCI controller will be resumed 246 * first, so we have to do the port switchover in both drivers. Writing 247 * a '1' to the port switchover registers should have no effect if the 248 * port was already switched over. 249 */ 250 if (usb_is_intel_switchable_xhci(pdev)) 251 usb_enable_xhci_ports(pdev); 252 253 retval = xhci_resume(xhci, hibernated); 254 return retval; 255 } 256 #endif /* CONFIG_PM */ 257 258 static const struct hc_driver xhci_pci_hc_driver = { 259 .description = hcd_name, 260 .product_desc = "xHCI Host Controller", 261 .hcd_priv_size = sizeof(struct xhci_hcd *), 262 263 /* 264 * generic hardware linkage 265 */ 266 .irq = xhci_irq, 267 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED, 268 269 /* 270 * basic lifecycle operations 271 */ 272 .reset = xhci_pci_setup, 273 .start = xhci_run, 274 #ifdef CONFIG_PM 275 .pci_suspend = xhci_pci_suspend, 276 .pci_resume = xhci_pci_resume, 277 #endif 278 .stop = xhci_stop, 279 .shutdown = xhci_shutdown, 280 281 /* 282 * managing i/o requests and associated device resources 283 */ 284 .urb_enqueue = xhci_urb_enqueue, 285 .urb_dequeue = xhci_urb_dequeue, 286 .alloc_dev = xhci_alloc_dev, 287 .free_dev = xhci_free_dev, 288 .alloc_streams = xhci_alloc_streams, 289 .free_streams = xhci_free_streams, 290 .add_endpoint = xhci_add_endpoint, 291 .drop_endpoint = xhci_drop_endpoint, 292 .endpoint_reset = xhci_endpoint_reset, 293 .check_bandwidth = xhci_check_bandwidth, 294 .reset_bandwidth = xhci_reset_bandwidth, 295 .address_device = xhci_address_device, 296 .update_hub_device = xhci_update_hub_device, 297 .reset_device = xhci_discover_or_reset_device, 298 299 /* 300 * scheduling support 301 */ 302 .get_frame_number = xhci_get_frame, 303 304 /* Root hub support */ 305 .hub_control = xhci_hub_control, 306 .hub_status_data = xhci_hub_status_data, 307 .bus_suspend = xhci_bus_suspend, 308 .bus_resume = xhci_bus_resume, 309 /* 310 * call back when device connected and addressed 311 */ 312 .update_device = xhci_update_device, 313 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm, 314 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout, 315 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout, 316 }; 317 318 /*-------------------------------------------------------------------------*/ 319 320 /* PCI driver selection metadata; PCI hotplugging uses this */ 321 static const struct pci_device_id pci_ids[] = { { 322 /* handle any USB 3.0 xHCI controller */ 323 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 324 .driver_data = (unsigned long) &xhci_pci_hc_driver, 325 }, 326 { /* end: all zeroes */ } 327 }; 328 MODULE_DEVICE_TABLE(pci, pci_ids); 329 330 /* pci driver glue; this is a "new style" PCI driver module */ 331 static struct pci_driver xhci_pci_driver = { 332 .name = (char *) hcd_name, 333 .id_table = pci_ids, 334 335 .probe = xhci_pci_probe, 336 .remove = xhci_pci_remove, 337 /* suspend and resume implemented later */ 338 339 .shutdown = usb_hcd_pci_shutdown, 340 #ifdef CONFIG_PM_SLEEP 341 .driver = { 342 .pm = &usb_hcd_pci_pm_ops 343 }, 344 #endif 345 }; 346 347 int __init xhci_register_pci(void) 348 { 349 return pci_register_driver(&xhci_pci_driver); 350 } 351 352 void xhci_unregister_pci(void) 353 { 354 pci_unregister_driver(&xhci_pci_driver); 355 } 356