1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 #include <linux/reset.h> 16 17 #include "xhci.h" 18 #include "xhci-trace.h" 19 #include "xhci-pci.h" 20 21 #define SSIC_PORT_NUM 2 22 #define SSIC_PORT_CFG2 0x880c 23 #define SSIC_PORT_CFG2_OFFSET 0x30 24 #define PROG_DONE (1 << 30) 25 #define SSIC_PORT_UNUSED (1 << 31) 26 27 /* Device for a quirk */ 28 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 29 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 30 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 31 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 32 33 #define PCI_VENDOR_ID_ETRON 0x1b6f 34 #define PCI_DEVICE_ID_EJ168 0x7023 35 36 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 37 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 38 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 39 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 40 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 41 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 42 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 43 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 44 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 45 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 46 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 47 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 48 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 49 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 50 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 51 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 52 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 53 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 54 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af 55 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13 56 57 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 58 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 59 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 60 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 61 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042 62 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 63 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242 64 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142 65 66 static const char hcd_name[] = "xhci_hcd"; 67 68 static struct hc_driver __read_mostly xhci_pci_hc_driver; 69 70 static int xhci_pci_setup(struct usb_hcd *hcd); 71 72 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 73 .reset = xhci_pci_setup, 74 }; 75 76 /* called after powerup, by probe or system-pm "wakeup" */ 77 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 78 { 79 /* 80 * TODO: Implement finding debug ports later. 81 * TODO: see if there are any quirks that need to be added to handle 82 * new extended capabilities. 83 */ 84 85 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 86 if (!pci_set_mwi(pdev)) 87 xhci_dbg(xhci, "MWI active\n"); 88 89 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 90 return 0; 91 } 92 93 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 94 { 95 struct pci_dev *pdev = to_pci_dev(dev); 96 struct xhci_driver_data *driver_data; 97 const struct pci_device_id *id; 98 99 id = pci_match_id(pdev->driver->id_table, pdev); 100 101 if (id && id->driver_data) { 102 driver_data = (struct xhci_driver_data *)id->driver_data; 103 xhci->quirks |= driver_data->quirks; 104 } 105 106 /* Look for vendor-specific quirks */ 107 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 108 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 109 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 110 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 111 pdev->revision == 0x0) { 112 xhci->quirks |= XHCI_RESET_EP_QUIRK; 113 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 114 "QUIRK: Fresco Logic xHC needs configure" 115 " endpoint cmd after reset endpoint"); 116 } 117 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 118 pdev->revision == 0x4) { 119 xhci->quirks |= XHCI_SLOW_SUSPEND; 120 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 121 "QUIRK: Fresco Logic xHC revision %u" 122 "must be suspended extra slowly", 123 pdev->revision); 124 } 125 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 126 xhci->quirks |= XHCI_BROKEN_STREAMS; 127 /* Fresco Logic confirms: all revisions of this chip do not 128 * support MSI, even though some of them claim to in their PCI 129 * capabilities. 130 */ 131 xhci->quirks |= XHCI_BROKEN_MSI; 132 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 133 "QUIRK: Fresco Logic revision %u " 134 "has broken MSI implementation", 135 pdev->revision); 136 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 137 } 138 139 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 140 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 141 xhci->quirks |= XHCI_BROKEN_STREAMS; 142 143 if (pdev->vendor == PCI_VENDOR_ID_NEC) 144 xhci->quirks |= XHCI_NEC_HOST; 145 146 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 147 xhci->quirks |= XHCI_AMD_0x96_HOST; 148 149 /* AMD PLL quirk */ 150 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) 151 xhci->quirks |= XHCI_AMD_PLL_FIX; 152 153 if (pdev->vendor == PCI_VENDOR_ID_AMD && 154 (pdev->device == 0x145c || 155 pdev->device == 0x15e0 || 156 pdev->device == 0x15e1 || 157 pdev->device == 0x43bb)) 158 xhci->quirks |= XHCI_SUSPEND_DELAY; 159 160 if (pdev->vendor == PCI_VENDOR_ID_AMD && 161 (pdev->device == 0x15e0 || pdev->device == 0x15e1)) 162 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; 163 164 if (pdev->vendor == PCI_VENDOR_ID_AMD) 165 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 166 167 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 168 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 169 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 170 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 171 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 172 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 173 174 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 175 xhci->quirks |= XHCI_LPM_SUPPORT; 176 xhci->quirks |= XHCI_INTEL_HOST; 177 xhci->quirks |= XHCI_AVOID_BEI; 178 } 179 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 180 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 181 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 182 xhci->limit_active_eps = 64; 183 xhci->quirks |= XHCI_SW_BW_CHECKING; 184 /* 185 * PPT desktop boards DH77EB and DH77DF will power back on after 186 * a few seconds of being shutdown. The fix for this is to 187 * switch the ports from xHCI to EHCI on shutdown. We can't use 188 * DMI information to find those particular boards (since each 189 * vendor will change the board name), so we have to key off all 190 * PPT chipsets. 191 */ 192 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 193 } 194 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 195 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 196 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 197 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 198 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 199 } 200 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 201 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 202 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 203 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 204 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 205 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 206 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 207 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI || 208 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) { 209 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 210 } 211 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 212 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 213 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 214 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 215 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 216 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 217 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI)) 218 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 219 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 220 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 221 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 222 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 223 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 224 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) 225 xhci->quirks |= XHCI_MISSING_CAS; 226 227 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 228 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 229 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 230 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 231 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 232 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 233 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 234 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || 235 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI || 236 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI)) 237 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 238 239 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 240 pdev->device == PCI_DEVICE_ID_EJ168) { 241 xhci->quirks |= XHCI_RESET_ON_RESUME; 242 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 243 xhci->quirks |= XHCI_BROKEN_STREAMS; 244 } 245 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 246 pdev->device == 0x0014) { 247 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 248 xhci->quirks |= XHCI_ZERO_64B_REGS; 249 } 250 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 251 pdev->device == 0x0015) { 252 xhci->quirks |= XHCI_RESET_ON_RESUME; 253 xhci->quirks |= XHCI_ZERO_64B_REGS; 254 } 255 if (pdev->vendor == PCI_VENDOR_ID_VIA) 256 xhci->quirks |= XHCI_RESET_ON_RESUME; 257 258 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 259 if (pdev->vendor == PCI_VENDOR_ID_VIA && 260 pdev->device == 0x3432) 261 xhci->quirks |= XHCI_BROKEN_STREAMS; 262 263 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) 264 xhci->quirks |= XHCI_LPM_SUPPORT; 265 266 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 267 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) 268 xhci->quirks |= XHCI_BROKEN_STREAMS; 269 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 270 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 271 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 272 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 273 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI || 274 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI)) 275 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 276 277 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 278 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 279 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 280 281 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 282 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 283 284 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 285 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 286 pdev->device == 0x9026) 287 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 288 289 if (xhci->quirks & XHCI_RESET_ON_RESUME) 290 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 291 "QUIRK: Resetting on resume"); 292 } 293 294 #ifdef CONFIG_ACPI 295 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 296 { 297 static const guid_t intel_dsm_guid = 298 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 299 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 300 union acpi_object *obj; 301 302 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 303 NULL); 304 ACPI_FREE(obj); 305 } 306 #else 307 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 308 #endif /* CONFIG_ACPI */ 309 310 /* called during probe() after chip reset completes */ 311 static int xhci_pci_setup(struct usb_hcd *hcd) 312 { 313 struct xhci_hcd *xhci; 314 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 315 int retval; 316 317 xhci = hcd_to_xhci(hcd); 318 if (!xhci->sbrn) 319 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 320 321 /* imod_interval is the interrupt moderation value in nanoseconds. */ 322 xhci->imod_interval = 40000; 323 324 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 325 if (retval) 326 return retval; 327 328 if (!usb_hcd_is_primary_hcd(hcd)) 329 return 0; 330 331 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 332 xhci_pme_acpi_rtd3_enable(pdev); 333 334 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 335 336 /* Find any debug ports */ 337 return xhci_pci_reinit(xhci, pdev); 338 } 339 340 /* 341 * We need to register our own PCI probe function (instead of the USB core's 342 * function) in order to create a second roothub under xHCI. 343 */ 344 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 345 { 346 int retval; 347 struct xhci_hcd *xhci; 348 struct usb_hcd *hcd; 349 struct xhci_driver_data *driver_data; 350 struct reset_control *reset; 351 352 driver_data = (struct xhci_driver_data *)id->driver_data; 353 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) { 354 retval = renesas_xhci_check_request_fw(dev, id); 355 if (retval) 356 return retval; 357 } 358 359 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 360 if (IS_ERR(reset)) 361 return PTR_ERR(reset); 362 reset_control_reset(reset); 363 364 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 365 pm_runtime_get_noresume(&dev->dev); 366 367 /* Register the USB 2.0 roothub. 368 * FIXME: USB core must know to register the USB 2.0 roothub first. 369 * This is sort of silly, because we could just set the HCD driver flags 370 * to say USB 2.0, but I'm not sure what the implications would be in 371 * the other parts of the HCD code. 372 */ 373 retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver); 374 375 if (retval) 376 goto put_runtime_pm; 377 378 /* USB 2.0 roothub is stored in the PCI device now. */ 379 hcd = dev_get_drvdata(&dev->dev); 380 xhci = hcd_to_xhci(hcd); 381 xhci->reset = reset; 382 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev, 383 pci_name(dev), hcd); 384 if (!xhci->shared_hcd) { 385 retval = -ENOMEM; 386 goto dealloc_usb2_hcd; 387 } 388 389 retval = xhci_ext_cap_init(xhci); 390 if (retval) 391 goto put_usb3_hcd; 392 393 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 394 IRQF_SHARED); 395 if (retval) 396 goto put_usb3_hcd; 397 /* Roothub already marked as USB 3.0 speed */ 398 399 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 400 HCC_MAX_PSA(xhci->hcc_params) >= 4) 401 xhci->shared_hcd->can_do_streams = 1; 402 403 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 404 pm_runtime_put_noidle(&dev->dev); 405 406 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 407 pm_runtime_allow(&dev->dev); 408 409 return 0; 410 411 put_usb3_hcd: 412 usb_put_hcd(xhci->shared_hcd); 413 dealloc_usb2_hcd: 414 usb_hcd_pci_remove(dev); 415 put_runtime_pm: 416 pm_runtime_put_noidle(&dev->dev); 417 return retval; 418 } 419 420 static void xhci_pci_remove(struct pci_dev *dev) 421 { 422 struct xhci_hcd *xhci; 423 424 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 425 if (xhci->quirks & XHCI_RENESAS_FW_QUIRK) 426 renesas_xhci_pci_exit(dev); 427 428 xhci->xhc_state |= XHCI_STATE_REMOVING; 429 430 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 431 pm_runtime_forbid(&dev->dev); 432 433 if (xhci->shared_hcd) { 434 usb_remove_hcd(xhci->shared_hcd); 435 usb_put_hcd(xhci->shared_hcd); 436 xhci->shared_hcd = NULL; 437 } 438 439 /* Workaround for spurious wakeups at shutdown with HSW */ 440 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 441 pci_set_power_state(dev, PCI_D3hot); 442 443 usb_hcd_pci_remove(dev); 444 } 445 446 #ifdef CONFIG_PM 447 /* 448 * In some Intel xHCI controllers, in order to get D3 working, 449 * through a vendor specific SSIC CONFIG register at offset 0x883c, 450 * SSIC PORT need to be marked as "unused" before putting xHCI 451 * into D3. After D3 exit, the SSIC port need to be marked as "used". 452 * Without this change, xHCI might not enter D3 state. 453 */ 454 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 455 { 456 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 457 u32 val; 458 void __iomem *reg; 459 int i; 460 461 for (i = 0; i < SSIC_PORT_NUM; i++) { 462 reg = (void __iomem *) xhci->cap_regs + 463 SSIC_PORT_CFG2 + 464 i * SSIC_PORT_CFG2_OFFSET; 465 466 /* Notify SSIC that SSIC profile programming is not done. */ 467 val = readl(reg) & ~PROG_DONE; 468 writel(val, reg); 469 470 /* Mark SSIC port as unused(suspend) or used(resume) */ 471 val = readl(reg); 472 if (suspend) 473 val |= SSIC_PORT_UNUSED; 474 else 475 val &= ~SSIC_PORT_UNUSED; 476 writel(val, reg); 477 478 /* Notify SSIC that SSIC profile programming is done */ 479 val = readl(reg) | PROG_DONE; 480 writel(val, reg); 481 readl(reg); 482 } 483 } 484 485 /* 486 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 487 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 488 */ 489 static void xhci_pme_quirk(struct usb_hcd *hcd) 490 { 491 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 492 void __iomem *reg; 493 u32 val; 494 495 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 496 val = readl(reg); 497 writel(val | BIT(28), reg); 498 readl(reg); 499 } 500 501 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 502 { 503 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 504 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 505 int ret; 506 507 /* 508 * Systems with the TI redriver that loses port status change events 509 * need to have the registers polled during D3, so avoid D3cold. 510 */ 511 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 512 pci_d3cold_disable(pdev); 513 514 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 515 xhci_pme_quirk(hcd); 516 517 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 518 xhci_ssic_port_unused_quirk(hcd, true); 519 520 ret = xhci_suspend(xhci, do_wakeup); 521 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 522 xhci_ssic_port_unused_quirk(hcd, false); 523 524 return ret; 525 } 526 527 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 528 { 529 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 530 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 531 int retval = 0; 532 533 reset_control_reset(xhci->reset); 534 535 /* The BIOS on systems with the Intel Panther Point chipset may or may 536 * not support xHCI natively. That means that during system resume, it 537 * may switch the ports back to EHCI so that users can use their 538 * keyboard to select a kernel from GRUB after resume from hibernate. 539 * 540 * The BIOS is supposed to remember whether the OS had xHCI ports 541 * enabled before resume, and switch the ports back to xHCI when the 542 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 543 * writers. 544 * 545 * Unconditionally switch the ports back to xHCI after a system resume. 546 * It should not matter whether the EHCI or xHCI controller is 547 * resumed first. It's enough to do the switchover in xHCI because 548 * USB core won't notice anything as the hub driver doesn't start 549 * running again until after all the devices (including both EHCI and 550 * xHCI host controllers) have been resumed. 551 */ 552 553 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 554 usb_enable_intel_xhci_ports(pdev); 555 556 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 557 xhci_ssic_port_unused_quirk(hcd, false); 558 559 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 560 xhci_pme_quirk(hcd); 561 562 retval = xhci_resume(xhci, hibernated); 563 return retval; 564 } 565 566 static void xhci_pci_shutdown(struct usb_hcd *hcd) 567 { 568 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 569 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 570 571 xhci_shutdown(hcd); 572 573 /* Yet another workaround for spurious wakeups at shutdown with HSW */ 574 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 575 pci_set_power_state(pdev, PCI_D3hot); 576 } 577 #endif /* CONFIG_PM */ 578 579 /*-------------------------------------------------------------------------*/ 580 581 static const struct xhci_driver_data reneses_data = { 582 .quirks = XHCI_RENESAS_FW_QUIRK, 583 .firmware = "renesas_usb_fw.mem", 584 }; 585 586 /* PCI driver selection metadata; PCI hotplugging uses this */ 587 static const struct pci_device_id pci_ids[] = { 588 { PCI_DEVICE(0x1912, 0x0014), 589 .driver_data = (unsigned long)&reneses_data, 590 }, 591 { PCI_DEVICE(0x1912, 0x0015), 592 .driver_data = (unsigned long)&reneses_data, 593 }, 594 /* handle any USB 3.0 xHCI controller */ 595 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 596 }, 597 { /* end: all zeroes */ } 598 }; 599 MODULE_DEVICE_TABLE(pci, pci_ids); 600 MODULE_FIRMWARE("renesas_usb_fw.mem"); 601 602 /* pci driver glue; this is a "new style" PCI driver module */ 603 static struct pci_driver xhci_pci_driver = { 604 .name = hcd_name, 605 .id_table = pci_ids, 606 607 .probe = xhci_pci_probe, 608 .remove = xhci_pci_remove, 609 /* suspend and resume implemented later */ 610 611 .shutdown = usb_hcd_pci_shutdown, 612 #ifdef CONFIG_PM 613 .driver = { 614 .pm = &usb_hcd_pci_pm_ops 615 }, 616 #endif 617 }; 618 619 static int __init xhci_pci_init(void) 620 { 621 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 622 #ifdef CONFIG_PM 623 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend; 624 xhci_pci_hc_driver.pci_resume = xhci_pci_resume; 625 xhci_pci_hc_driver.shutdown = xhci_pci_shutdown; 626 #endif 627 return pci_register_driver(&xhci_pci_driver); 628 } 629 module_init(xhci_pci_init); 630 631 static void __exit xhci_pci_exit(void) 632 { 633 pci_unregister_driver(&xhci_pci_driver); 634 } 635 module_exit(xhci_pci_exit); 636 637 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 638 MODULE_LICENSE("GPL"); 639