1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 16 #include "xhci.h" 17 #include "xhci-trace.h" 18 19 #define SSIC_PORT_NUM 2 20 #define SSIC_PORT_CFG2 0x880c 21 #define SSIC_PORT_CFG2_OFFSET 0x30 22 #define PROG_DONE (1 << 30) 23 #define SSIC_PORT_UNUSED (1 << 31) 24 25 /* Device for a quirk */ 26 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 27 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 28 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 29 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 30 31 #define PCI_VENDOR_ID_ETRON 0x1b6f 32 #define PCI_DEVICE_ID_EJ168 0x7023 33 34 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 35 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 36 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 37 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 38 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 39 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 40 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 41 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 42 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 43 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 44 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 45 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 46 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 47 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 48 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 49 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 50 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 51 52 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 53 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 54 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 55 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 56 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 57 58 static const char hcd_name[] = "xhci_hcd"; 59 60 static struct hc_driver __read_mostly xhci_pci_hc_driver; 61 62 static int xhci_pci_setup(struct usb_hcd *hcd); 63 64 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 65 .reset = xhci_pci_setup, 66 }; 67 68 /* called after powerup, by probe or system-pm "wakeup" */ 69 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 70 { 71 /* 72 * TODO: Implement finding debug ports later. 73 * TODO: see if there are any quirks that need to be added to handle 74 * new extended capabilities. 75 */ 76 77 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 78 if (!pci_set_mwi(pdev)) 79 xhci_dbg(xhci, "MWI active\n"); 80 81 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 82 return 0; 83 } 84 85 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 86 { 87 struct pci_dev *pdev = to_pci_dev(dev); 88 89 /* Look for vendor-specific quirks */ 90 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 91 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 92 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 93 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 94 pdev->revision == 0x0) { 95 xhci->quirks |= XHCI_RESET_EP_QUIRK; 96 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 97 "QUIRK: Fresco Logic xHC needs configure" 98 " endpoint cmd after reset endpoint"); 99 } 100 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 101 pdev->revision == 0x4) { 102 xhci->quirks |= XHCI_SLOW_SUSPEND; 103 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 104 "QUIRK: Fresco Logic xHC revision %u" 105 "must be suspended extra slowly", 106 pdev->revision); 107 } 108 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 109 xhci->quirks |= XHCI_BROKEN_STREAMS; 110 /* Fresco Logic confirms: all revisions of this chip do not 111 * support MSI, even though some of them claim to in their PCI 112 * capabilities. 113 */ 114 xhci->quirks |= XHCI_BROKEN_MSI; 115 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 116 "QUIRK: Fresco Logic revision %u " 117 "has broken MSI implementation", 118 pdev->revision); 119 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 120 } 121 122 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 123 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 124 xhci->quirks |= XHCI_BROKEN_STREAMS; 125 126 if (pdev->vendor == PCI_VENDOR_ID_NEC) 127 xhci->quirks |= XHCI_NEC_HOST; 128 129 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 130 xhci->quirks |= XHCI_AMD_0x96_HOST; 131 132 /* AMD PLL quirk */ 133 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) 134 xhci->quirks |= XHCI_AMD_PLL_FIX; 135 136 if (pdev->vendor == PCI_VENDOR_ID_AMD && 137 (pdev->device == 0x15e0 || 138 pdev->device == 0x15e1 || 139 pdev->device == 0x43bb)) 140 xhci->quirks |= XHCI_SUSPEND_DELAY; 141 142 if (pdev->vendor == PCI_VENDOR_ID_AMD && 143 (pdev->device == 0x15e0 || pdev->device == 0x15e1)) 144 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; 145 146 if (pdev->vendor == PCI_VENDOR_ID_AMD) 147 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 148 149 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 150 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 151 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 152 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 153 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 154 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 155 156 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 157 xhci->quirks |= XHCI_LPM_SUPPORT; 158 xhci->quirks |= XHCI_INTEL_HOST; 159 xhci->quirks |= XHCI_AVOID_BEI; 160 } 161 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 162 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 163 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 164 xhci->limit_active_eps = 64; 165 xhci->quirks |= XHCI_SW_BW_CHECKING; 166 /* 167 * PPT desktop boards DH77EB and DH77DF will power back on after 168 * a few seconds of being shutdown. The fix for this is to 169 * switch the ports from xHCI to EHCI on shutdown. We can't use 170 * DMI information to find those particular boards (since each 171 * vendor will change the board name), so we have to key off all 172 * PPT chipsets. 173 */ 174 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 175 } 176 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 177 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 178 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 179 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 180 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 181 } 182 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 183 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 184 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 185 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 186 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 187 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 188 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 189 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) { 190 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 191 } 192 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 193 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 194 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 195 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 196 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 197 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 198 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI)) 199 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 200 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 201 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 202 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 203 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 204 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 205 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) 206 xhci->quirks |= XHCI_MISSING_CAS; 207 208 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 209 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 210 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 211 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 212 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 213 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 214 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 215 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI)) 216 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 217 218 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 219 pdev->device == PCI_DEVICE_ID_EJ168) { 220 xhci->quirks |= XHCI_RESET_ON_RESUME; 221 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 222 xhci->quirks |= XHCI_BROKEN_STREAMS; 223 } 224 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 225 pdev->device == 0x0014) { 226 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 227 xhci->quirks |= XHCI_ZERO_64B_REGS; 228 } 229 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 230 pdev->device == 0x0015) { 231 xhci->quirks |= XHCI_RESET_ON_RESUME; 232 xhci->quirks |= XHCI_ZERO_64B_REGS; 233 } 234 if (pdev->vendor == PCI_VENDOR_ID_VIA) 235 xhci->quirks |= XHCI_RESET_ON_RESUME; 236 237 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 238 if (pdev->vendor == PCI_VENDOR_ID_VIA && 239 pdev->device == 0x3432) 240 xhci->quirks |= XHCI_BROKEN_STREAMS; 241 242 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 243 pdev->device == 0x1042) 244 xhci->quirks |= XHCI_BROKEN_STREAMS; 245 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 246 pdev->device == 0x1142) 247 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 248 249 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 250 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 251 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 252 253 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 254 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 255 256 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 257 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 258 pdev->device == 0x9026) 259 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 260 261 if (xhci->quirks & XHCI_RESET_ON_RESUME) 262 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 263 "QUIRK: Resetting on resume"); 264 } 265 266 #ifdef CONFIG_ACPI 267 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 268 { 269 static const guid_t intel_dsm_guid = 270 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 271 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 272 union acpi_object *obj; 273 274 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 275 NULL); 276 ACPI_FREE(obj); 277 } 278 #else 279 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 280 #endif /* CONFIG_ACPI */ 281 282 /* called during probe() after chip reset completes */ 283 static int xhci_pci_setup(struct usb_hcd *hcd) 284 { 285 struct xhci_hcd *xhci; 286 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 287 int retval; 288 289 xhci = hcd_to_xhci(hcd); 290 if (!xhci->sbrn) 291 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 292 293 /* imod_interval is the interrupt moderation value in nanoseconds. */ 294 xhci->imod_interval = 40000; 295 296 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 297 if (retval) 298 return retval; 299 300 if (!usb_hcd_is_primary_hcd(hcd)) 301 return 0; 302 303 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 304 305 /* Find any debug ports */ 306 return xhci_pci_reinit(xhci, pdev); 307 } 308 309 /* 310 * We need to register our own PCI probe function (instead of the USB core's 311 * function) in order to create a second roothub under xHCI. 312 */ 313 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 314 { 315 int retval; 316 struct xhci_hcd *xhci; 317 struct hc_driver *driver; 318 struct usb_hcd *hcd; 319 320 driver = (struct hc_driver *)id->driver_data; 321 322 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 323 pm_runtime_get_noresume(&dev->dev); 324 325 /* Register the USB 2.0 roothub. 326 * FIXME: USB core must know to register the USB 2.0 roothub first. 327 * This is sort of silly, because we could just set the HCD driver flags 328 * to say USB 2.0, but I'm not sure what the implications would be in 329 * the other parts of the HCD code. 330 */ 331 retval = usb_hcd_pci_probe(dev, id); 332 333 if (retval) 334 goto put_runtime_pm; 335 336 /* USB 2.0 roothub is stored in the PCI device now. */ 337 hcd = dev_get_drvdata(&dev->dev); 338 xhci = hcd_to_xhci(hcd); 339 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, 340 pci_name(dev), hcd); 341 if (!xhci->shared_hcd) { 342 retval = -ENOMEM; 343 goto dealloc_usb2_hcd; 344 } 345 346 retval = xhci_ext_cap_init(xhci); 347 if (retval) 348 goto put_usb3_hcd; 349 350 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 351 IRQF_SHARED); 352 if (retval) 353 goto put_usb3_hcd; 354 /* Roothub already marked as USB 3.0 speed */ 355 356 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 357 HCC_MAX_PSA(xhci->hcc_params) >= 4) 358 xhci->shared_hcd->can_do_streams = 1; 359 360 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 361 xhci_pme_acpi_rtd3_enable(dev); 362 363 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 364 pm_runtime_put_noidle(&dev->dev); 365 366 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 367 pm_runtime_allow(&dev->dev); 368 369 return 0; 370 371 put_usb3_hcd: 372 usb_put_hcd(xhci->shared_hcd); 373 dealloc_usb2_hcd: 374 usb_hcd_pci_remove(dev); 375 put_runtime_pm: 376 pm_runtime_put_noidle(&dev->dev); 377 return retval; 378 } 379 380 static void xhci_pci_remove(struct pci_dev *dev) 381 { 382 struct xhci_hcd *xhci; 383 384 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 385 xhci->xhc_state |= XHCI_STATE_REMOVING; 386 387 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 388 pm_runtime_forbid(&dev->dev); 389 390 if (xhci->shared_hcd) { 391 usb_remove_hcd(xhci->shared_hcd); 392 usb_put_hcd(xhci->shared_hcd); 393 xhci->shared_hcd = NULL; 394 } 395 396 /* Workaround for spurious wakeups at shutdown with HSW */ 397 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 398 pci_set_power_state(dev, PCI_D3hot); 399 400 usb_hcd_pci_remove(dev); 401 } 402 403 #ifdef CONFIG_PM 404 /* 405 * In some Intel xHCI controllers, in order to get D3 working, 406 * through a vendor specific SSIC CONFIG register at offset 0x883c, 407 * SSIC PORT need to be marked as "unused" before putting xHCI 408 * into D3. After D3 exit, the SSIC port need to be marked as "used". 409 * Without this change, xHCI might not enter D3 state. 410 */ 411 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 412 { 413 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 414 u32 val; 415 void __iomem *reg; 416 int i; 417 418 for (i = 0; i < SSIC_PORT_NUM; i++) { 419 reg = (void __iomem *) xhci->cap_regs + 420 SSIC_PORT_CFG2 + 421 i * SSIC_PORT_CFG2_OFFSET; 422 423 /* Notify SSIC that SSIC profile programming is not done. */ 424 val = readl(reg) & ~PROG_DONE; 425 writel(val, reg); 426 427 /* Mark SSIC port as unused(suspend) or used(resume) */ 428 val = readl(reg); 429 if (suspend) 430 val |= SSIC_PORT_UNUSED; 431 else 432 val &= ~SSIC_PORT_UNUSED; 433 writel(val, reg); 434 435 /* Notify SSIC that SSIC profile programming is done */ 436 val = readl(reg) | PROG_DONE; 437 writel(val, reg); 438 readl(reg); 439 } 440 } 441 442 /* 443 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 444 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 445 */ 446 static void xhci_pme_quirk(struct usb_hcd *hcd) 447 { 448 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 449 void __iomem *reg; 450 u32 val; 451 452 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 453 val = readl(reg); 454 writel(val | BIT(28), reg); 455 readl(reg); 456 } 457 458 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 459 { 460 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 461 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 462 int ret; 463 464 /* 465 * Systems with the TI redriver that loses port status change events 466 * need to have the registers polled during D3, so avoid D3cold. 467 */ 468 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 469 pci_d3cold_disable(pdev); 470 471 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 472 xhci_pme_quirk(hcd); 473 474 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 475 xhci_ssic_port_unused_quirk(hcd, true); 476 477 ret = xhci_suspend(xhci, do_wakeup); 478 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 479 xhci_ssic_port_unused_quirk(hcd, false); 480 481 return ret; 482 } 483 484 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 485 { 486 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 487 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 488 int retval = 0; 489 490 /* The BIOS on systems with the Intel Panther Point chipset may or may 491 * not support xHCI natively. That means that during system resume, it 492 * may switch the ports back to EHCI so that users can use their 493 * keyboard to select a kernel from GRUB after resume from hibernate. 494 * 495 * The BIOS is supposed to remember whether the OS had xHCI ports 496 * enabled before resume, and switch the ports back to xHCI when the 497 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 498 * writers. 499 * 500 * Unconditionally switch the ports back to xHCI after a system resume. 501 * It should not matter whether the EHCI or xHCI controller is 502 * resumed first. It's enough to do the switchover in xHCI because 503 * USB core won't notice anything as the hub driver doesn't start 504 * running again until after all the devices (including both EHCI and 505 * xHCI host controllers) have been resumed. 506 */ 507 508 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 509 usb_enable_intel_xhci_ports(pdev); 510 511 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 512 xhci_ssic_port_unused_quirk(hcd, false); 513 514 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 515 xhci_pme_quirk(hcd); 516 517 retval = xhci_resume(xhci, hibernated); 518 return retval; 519 } 520 #endif /* CONFIG_PM */ 521 522 /*-------------------------------------------------------------------------*/ 523 524 /* PCI driver selection metadata; PCI hotplugging uses this */ 525 static const struct pci_device_id pci_ids[] = { { 526 /* handle any USB 3.0 xHCI controller */ 527 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 528 .driver_data = (unsigned long) &xhci_pci_hc_driver, 529 }, 530 { /* end: all zeroes */ } 531 }; 532 MODULE_DEVICE_TABLE(pci, pci_ids); 533 534 /* pci driver glue; this is a "new style" PCI driver module */ 535 static struct pci_driver xhci_pci_driver = { 536 .name = (char *) hcd_name, 537 .id_table = pci_ids, 538 539 .probe = xhci_pci_probe, 540 .remove = xhci_pci_remove, 541 /* suspend and resume implemented later */ 542 543 .shutdown = usb_hcd_pci_shutdown, 544 #ifdef CONFIG_PM 545 .driver = { 546 .pm = &usb_hcd_pci_pm_ops 547 }, 548 #endif 549 }; 550 551 static int __init xhci_pci_init(void) 552 { 553 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 554 #ifdef CONFIG_PM 555 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend; 556 xhci_pci_hc_driver.pci_resume = xhci_pci_resume; 557 #endif 558 return pci_register_driver(&xhci_pci_driver); 559 } 560 module_init(xhci_pci_init); 561 562 static void __exit xhci_pci_exit(void) 563 { 564 pci_unregister_driver(&xhci_pci_driver); 565 } 566 module_exit(xhci_pci_exit); 567 568 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 569 MODULE_LICENSE("GPL"); 570