1 /* 2 * xHCI host controller driver PCI Bus Glue. 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/pci.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 27 #include "xhci.h" 28 29 /* Device for a quirk */ 30 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 31 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 32 33 #define PCI_VENDOR_ID_ETRON 0x1b6f 34 #define PCI_DEVICE_ID_ASROCK_P67 0x7023 35 36 static const char hcd_name[] = "xhci_hcd"; 37 38 /* called after powerup, by probe or system-pm "wakeup" */ 39 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 40 { 41 /* 42 * TODO: Implement finding debug ports later. 43 * TODO: see if there are any quirks that need to be added to handle 44 * new extended capabilities. 45 */ 46 47 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 48 if (!pci_set_mwi(pdev)) 49 xhci_dbg(xhci, "MWI active\n"); 50 51 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 52 return 0; 53 } 54 55 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 56 { 57 struct pci_dev *pdev = to_pci_dev(dev); 58 59 /* Look for vendor-specific quirks */ 60 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 61 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) { 62 if (pdev->revision == 0x0) { 63 xhci->quirks |= XHCI_RESET_EP_QUIRK; 64 xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure" 65 " endpoint cmd after reset endpoint\n"); 66 } 67 /* Fresco Logic confirms: all revisions of this chip do not 68 * support MSI, even though some of them claim to in their PCI 69 * capabilities. 70 */ 71 xhci->quirks |= XHCI_BROKEN_MSI; 72 xhci_dbg(xhci, "QUIRK: Fresco Logic revision %u " 73 "has broken MSI implementation\n", 74 pdev->revision); 75 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 76 } 77 78 if (pdev->vendor == PCI_VENDOR_ID_NEC) 79 xhci->quirks |= XHCI_NEC_HOST; 80 81 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 82 xhci->quirks |= XHCI_AMD_0x96_HOST; 83 84 /* AMD PLL quirk */ 85 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info()) 86 xhci->quirks |= XHCI_AMD_PLL_FIX; 87 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 88 xhci->quirks |= XHCI_LPM_SUPPORT; 89 xhci->quirks |= XHCI_INTEL_HOST; 90 } 91 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 92 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 93 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 94 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 95 xhci->limit_active_eps = 64; 96 xhci->quirks |= XHCI_SW_BW_CHECKING; 97 /* 98 * PPT desktop boards DH77EB and DH77DF will power back on after 99 * a few seconds of being shutdown. The fix for this is to 100 * switch the ports from xHCI to EHCI on shutdown. We can't use 101 * DMI information to find those particular boards (since each 102 * vendor will change the board name), so we have to key off all 103 * PPT chipsets. 104 */ 105 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 106 } 107 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 108 pdev->device == PCI_DEVICE_ID_ASROCK_P67) { 109 xhci->quirks |= XHCI_RESET_ON_RESUME; 110 xhci_dbg(xhci, "QUIRK: Resetting on resume\n"); 111 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 112 } 113 if (pdev->vendor == PCI_VENDOR_ID_VIA) 114 xhci->quirks |= XHCI_RESET_ON_RESUME; 115 } 116 117 /* called during probe() after chip reset completes */ 118 static int xhci_pci_setup(struct usb_hcd *hcd) 119 { 120 struct xhci_hcd *xhci; 121 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 122 int retval; 123 124 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 125 if (retval) 126 return retval; 127 128 xhci = hcd_to_xhci(hcd); 129 if (!usb_hcd_is_primary_hcd(hcd)) 130 return 0; 131 132 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 133 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 134 135 /* Find any debug ports */ 136 retval = xhci_pci_reinit(xhci, pdev); 137 if (!retval) 138 return retval; 139 140 kfree(xhci); 141 return retval; 142 } 143 144 /* 145 * We need to register our own PCI probe function (instead of the USB core's 146 * function) in order to create a second roothub under xHCI. 147 */ 148 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 149 { 150 int retval; 151 struct xhci_hcd *xhci; 152 struct hc_driver *driver; 153 struct usb_hcd *hcd; 154 155 driver = (struct hc_driver *)id->driver_data; 156 /* Register the USB 2.0 roothub. 157 * FIXME: USB core must know to register the USB 2.0 roothub first. 158 * This is sort of silly, because we could just set the HCD driver flags 159 * to say USB 2.0, but I'm not sure what the implications would be in 160 * the other parts of the HCD code. 161 */ 162 retval = usb_hcd_pci_probe(dev, id); 163 164 if (retval) 165 return retval; 166 167 /* USB 2.0 roothub is stored in the PCI device now. */ 168 hcd = dev_get_drvdata(&dev->dev); 169 xhci = hcd_to_xhci(hcd); 170 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, 171 pci_name(dev), hcd); 172 if (!xhci->shared_hcd) { 173 retval = -ENOMEM; 174 goto dealloc_usb2_hcd; 175 } 176 177 /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset) 178 * is called by usb_add_hcd(). 179 */ 180 *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci; 181 182 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 183 IRQF_SHARED); 184 if (retval) 185 goto put_usb3_hcd; 186 /* Roothub already marked as USB 3.0 speed */ 187 188 /* We know the LPM timeout algorithms for this host, let the USB core 189 * enable and disable LPM for devices under the USB 3.0 roothub. 190 */ 191 if (xhci->quirks & XHCI_LPM_SUPPORT) 192 hcd_to_bus(xhci->shared_hcd)->root_hub->lpm_capable = 1; 193 194 return 0; 195 196 put_usb3_hcd: 197 usb_put_hcd(xhci->shared_hcd); 198 dealloc_usb2_hcd: 199 usb_hcd_pci_remove(dev); 200 return retval; 201 } 202 203 static void xhci_pci_remove(struct pci_dev *dev) 204 { 205 struct xhci_hcd *xhci; 206 207 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 208 if (xhci->shared_hcd) { 209 usb_remove_hcd(xhci->shared_hcd); 210 usb_put_hcd(xhci->shared_hcd); 211 } 212 usb_hcd_pci_remove(dev); 213 kfree(xhci); 214 } 215 216 #ifdef CONFIG_PM 217 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 218 { 219 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 220 int retval = 0; 221 222 if (hcd->state != HC_STATE_SUSPENDED || 223 xhci->shared_hcd->state != HC_STATE_SUSPENDED) 224 return -EINVAL; 225 226 retval = xhci_suspend(xhci); 227 228 return retval; 229 } 230 231 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 232 { 233 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 234 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 235 int retval = 0; 236 237 /* The BIOS on systems with the Intel Panther Point chipset may or may 238 * not support xHCI natively. That means that during system resume, it 239 * may switch the ports back to EHCI so that users can use their 240 * keyboard to select a kernel from GRUB after resume from hibernate. 241 * 242 * The BIOS is supposed to remember whether the OS had xHCI ports 243 * enabled before resume, and switch the ports back to xHCI when the 244 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 245 * writers. 246 * 247 * Unconditionally switch the ports back to xHCI after a system resume. 248 * We can't tell whether the EHCI or xHCI controller will be resumed 249 * first, so we have to do the port switchover in both drivers. Writing 250 * a '1' to the port switchover registers should have no effect if the 251 * port was already switched over. 252 */ 253 if (usb_is_intel_switchable_xhci(pdev)) 254 usb_enable_xhci_ports(pdev); 255 256 retval = xhci_resume(xhci, hibernated); 257 return retval; 258 } 259 #endif /* CONFIG_PM */ 260 261 static const struct hc_driver xhci_pci_hc_driver = { 262 .description = hcd_name, 263 .product_desc = "xHCI Host Controller", 264 .hcd_priv_size = sizeof(struct xhci_hcd *), 265 266 /* 267 * generic hardware linkage 268 */ 269 .irq = xhci_irq, 270 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED, 271 272 /* 273 * basic lifecycle operations 274 */ 275 .reset = xhci_pci_setup, 276 .start = xhci_run, 277 #ifdef CONFIG_PM 278 .pci_suspend = xhci_pci_suspend, 279 .pci_resume = xhci_pci_resume, 280 #endif 281 .stop = xhci_stop, 282 .shutdown = xhci_shutdown, 283 284 /* 285 * managing i/o requests and associated device resources 286 */ 287 .urb_enqueue = xhci_urb_enqueue, 288 .urb_dequeue = xhci_urb_dequeue, 289 .alloc_dev = xhci_alloc_dev, 290 .free_dev = xhci_free_dev, 291 .alloc_streams = xhci_alloc_streams, 292 .free_streams = xhci_free_streams, 293 .add_endpoint = xhci_add_endpoint, 294 .drop_endpoint = xhci_drop_endpoint, 295 .endpoint_reset = xhci_endpoint_reset, 296 .check_bandwidth = xhci_check_bandwidth, 297 .reset_bandwidth = xhci_reset_bandwidth, 298 .address_device = xhci_address_device, 299 .update_hub_device = xhci_update_hub_device, 300 .reset_device = xhci_discover_or_reset_device, 301 302 /* 303 * scheduling support 304 */ 305 .get_frame_number = xhci_get_frame, 306 307 /* Root hub support */ 308 .hub_control = xhci_hub_control, 309 .hub_status_data = xhci_hub_status_data, 310 .bus_suspend = xhci_bus_suspend, 311 .bus_resume = xhci_bus_resume, 312 /* 313 * call back when device connected and addressed 314 */ 315 .update_device = xhci_update_device, 316 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm, 317 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout, 318 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout, 319 }; 320 321 /*-------------------------------------------------------------------------*/ 322 323 /* PCI driver selection metadata; PCI hotplugging uses this */ 324 static const struct pci_device_id pci_ids[] = { { 325 /* handle any USB 3.0 xHCI controller */ 326 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 327 .driver_data = (unsigned long) &xhci_pci_hc_driver, 328 }, 329 { /* end: all zeroes */ } 330 }; 331 MODULE_DEVICE_TABLE(pci, pci_ids); 332 333 /* pci driver glue; this is a "new style" PCI driver module */ 334 static struct pci_driver xhci_pci_driver = { 335 .name = (char *) hcd_name, 336 .id_table = pci_ids, 337 338 .probe = xhci_pci_probe, 339 .remove = xhci_pci_remove, 340 /* suspend and resume implemented later */ 341 342 .shutdown = usb_hcd_pci_shutdown, 343 #ifdef CONFIG_PM_SLEEP 344 .driver = { 345 .pm = &usb_hcd_pci_pm_ops 346 }, 347 #endif 348 }; 349 350 int __init xhci_register_pci(void) 351 { 352 return pci_register_driver(&xhci_pci_driver); 353 } 354 355 void xhci_unregister_pci(void) 356 { 357 pci_unregister_driver(&xhci_pci_driver); 358 } 359