1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 #include <linux/reset.h> 16 #include <linux/suspend.h> 17 18 #include "xhci.h" 19 #include "xhci-trace.h" 20 #include "xhci-pci.h" 21 22 #define SSIC_PORT_NUM 2 23 #define SSIC_PORT_CFG2 0x880c 24 #define SSIC_PORT_CFG2_OFFSET 0x30 25 #define PROG_DONE (1 << 30) 26 #define SSIC_PORT_UNUSED (1 << 31) 27 #define SPARSE_DISABLE_BIT 17 28 #define SPARSE_CNTL_ENABLE 0xC12C 29 30 /* Device for a quirk */ 31 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 32 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100 35 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 36 37 #define PCI_VENDOR_ID_ETRON 0x1b6f 38 #define PCI_DEVICE_ID_EJ168 0x7023 39 #define PCI_DEVICE_ID_EJ188 0x7052 40 41 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 42 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 43 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 44 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 45 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 46 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 47 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 48 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 49 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 50 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 53 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1 54 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 55 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 56 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 57 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 58 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 59 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 60 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af 61 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13 62 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138 63 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed 64 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI 0x54ed 65 66 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639 67 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 68 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 69 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 70 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 71 72 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042 73 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 74 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242 75 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142 76 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242 77 78 #define PCI_DEVICE_ID_CADENCE 0x17CD 79 #define PCI_DEVICE_ID_CADENCE_SSP 0x0200 80 81 static const char hcd_name[] = "xhci_hcd"; 82 83 static struct hc_driver __read_mostly xhci_pci_hc_driver; 84 85 static int xhci_pci_setup(struct usb_hcd *hcd); 86 static int xhci_pci_run(struct usb_hcd *hcd); 87 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 88 struct usb_tt *tt, gfp_t mem_flags); 89 90 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 91 .reset = xhci_pci_setup, 92 .start = xhci_pci_run, 93 .update_hub_device = xhci_pci_update_hub_device, 94 }; 95 96 static void xhci_msix_sync_irqs(struct xhci_hcd *xhci) 97 { 98 struct usb_hcd *hcd = xhci_to_hcd(xhci); 99 100 if (hcd->msix_enabled) { 101 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 102 int i; 103 104 for (i = 0; i < xhci->msix_count; i++) 105 synchronize_irq(pci_irq_vector(pdev, i)); 106 } 107 } 108 109 /* Free any IRQs and disable MSI-X */ 110 static void xhci_cleanup_msix(struct xhci_hcd *xhci) 111 { 112 struct usb_hcd *hcd = xhci_to_hcd(xhci); 113 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 114 115 /* return if using legacy interrupt */ 116 if (hcd->irq > 0) 117 return; 118 119 if (hcd->msix_enabled) { 120 int i; 121 122 for (i = 0; i < xhci->msix_count; i++) 123 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci)); 124 } else { 125 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci)); 126 } 127 128 pci_free_irq_vectors(pdev); 129 hcd->msix_enabled = 0; 130 } 131 132 /* 133 * Set up MSI 134 */ 135 static int xhci_setup_msi(struct xhci_hcd *xhci) 136 { 137 int ret; 138 /* 139 * TODO:Check with MSI Soc for sysdev 140 */ 141 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); 142 143 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 144 if (ret < 0) { 145 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 146 "failed to allocate MSI entry"); 147 return ret; 148 } 149 150 ret = request_irq(pdev->irq, xhci_msi_irq, 151 0, "xhci_hcd", xhci_to_hcd(xhci)); 152 if (ret) { 153 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 154 "disable MSI interrupt"); 155 pci_free_irq_vectors(pdev); 156 } 157 158 return ret; 159 } 160 161 /* 162 * Set up MSI-X 163 */ 164 static int xhci_setup_msix(struct xhci_hcd *xhci) 165 { 166 int i, ret; 167 struct usb_hcd *hcd = xhci_to_hcd(xhci); 168 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 169 170 /* 171 * calculate number of msi-x vectors supported. 172 * - HCS_MAX_INTRS: the max number of interrupts the host can handle, 173 * with max number of interrupters based on the xhci HCSPARAMS1. 174 * - num_online_cpus: maximum msi-x vectors per CPUs core. 175 * Add additional 1 vector to ensure always available interrupt. 176 */ 177 xhci->msix_count = min(num_online_cpus() + 1, 178 HCS_MAX_INTRS(xhci->hcs_params1)); 179 180 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count, 181 PCI_IRQ_MSIX); 182 if (ret < 0) { 183 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 184 "Failed to enable MSI-X"); 185 return ret; 186 } 187 188 for (i = 0; i < xhci->msix_count; i++) { 189 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0, 190 "xhci_hcd", xhci_to_hcd(xhci)); 191 if (ret) 192 goto disable_msix; 193 } 194 195 hcd->msix_enabled = 1; 196 return ret; 197 198 disable_msix: 199 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt"); 200 while (--i >= 0) 201 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci)); 202 pci_free_irq_vectors(pdev); 203 return ret; 204 } 205 206 static int xhci_try_enable_msi(struct usb_hcd *hcd) 207 { 208 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 209 struct pci_dev *pdev; 210 int ret; 211 212 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); 213 /* 214 * Some Fresco Logic host controllers advertise MSI, but fail to 215 * generate interrupts. Don't even try to enable MSI. 216 */ 217 if (xhci->quirks & XHCI_BROKEN_MSI) 218 goto legacy_irq; 219 220 /* unregister the legacy interrupt */ 221 if (hcd->irq) 222 free_irq(hcd->irq, hcd); 223 hcd->irq = 0; 224 225 ret = xhci_setup_msix(xhci); 226 if (ret) 227 /* fall back to msi*/ 228 ret = xhci_setup_msi(xhci); 229 230 if (!ret) { 231 hcd->msi_enabled = 1; 232 return 0; 233 } 234 235 if (!pdev->irq) { 236 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n"); 237 return -EINVAL; 238 } 239 240 legacy_irq: 241 if (!strlen(hcd->irq_descr)) 242 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d", 243 hcd->driver->description, hcd->self.busnum); 244 245 /* fall back to legacy interrupt*/ 246 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, 247 hcd->irq_descr, hcd); 248 if (ret) { 249 xhci_err(xhci, "request interrupt %d failed\n", 250 pdev->irq); 251 return ret; 252 } 253 hcd->irq = pdev->irq; 254 return 0; 255 } 256 257 static int xhci_pci_run(struct usb_hcd *hcd) 258 { 259 int ret; 260 261 if (usb_hcd_is_primary_hcd(hcd)) { 262 ret = xhci_try_enable_msi(hcd); 263 if (ret) 264 return ret; 265 } 266 267 return xhci_run(hcd); 268 } 269 270 static void xhci_pci_stop(struct usb_hcd *hcd) 271 { 272 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 273 274 xhci_stop(hcd); 275 276 if (usb_hcd_is_primary_hcd(hcd)) 277 xhci_cleanup_msix(xhci); 278 } 279 280 /* called after powerup, by probe or system-pm "wakeup" */ 281 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 282 { 283 /* 284 * TODO: Implement finding debug ports later. 285 * TODO: see if there are any quirks that need to be added to handle 286 * new extended capabilities. 287 */ 288 289 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 290 if (!pci_set_mwi(pdev)) 291 xhci_dbg(xhci, "MWI active\n"); 292 293 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 294 return 0; 295 } 296 297 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 298 { 299 struct pci_dev *pdev = to_pci_dev(dev); 300 struct xhci_driver_data *driver_data; 301 const struct pci_device_id *id; 302 303 id = pci_match_id(to_pci_driver(pdev->dev.driver)->id_table, pdev); 304 305 if (id && id->driver_data) { 306 driver_data = (struct xhci_driver_data *)id->driver_data; 307 xhci->quirks |= driver_data->quirks; 308 } 309 310 /* Look for vendor-specific quirks */ 311 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 312 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 313 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 314 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 315 pdev->revision == 0x0) { 316 xhci->quirks |= XHCI_RESET_EP_QUIRK; 317 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 318 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated"); 319 } 320 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 321 pdev->revision == 0x4) { 322 xhci->quirks |= XHCI_SLOW_SUSPEND; 323 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 324 "QUIRK: Fresco Logic xHC revision %u" 325 "must be suspended extra slowly", 326 pdev->revision); 327 } 328 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 329 xhci->quirks |= XHCI_BROKEN_STREAMS; 330 /* Fresco Logic confirms: all revisions of this chip do not 331 * support MSI, even though some of them claim to in their PCI 332 * capabilities. 333 */ 334 xhci->quirks |= XHCI_BROKEN_MSI; 335 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 336 "QUIRK: Fresco Logic revision %u " 337 "has broken MSI implementation", 338 pdev->revision); 339 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 340 } 341 342 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 343 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 344 xhci->quirks |= XHCI_BROKEN_STREAMS; 345 346 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 347 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100) 348 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 349 350 if (pdev->vendor == PCI_VENDOR_ID_NEC) 351 xhci->quirks |= XHCI_NEC_HOST; 352 353 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 354 xhci->quirks |= XHCI_AMD_0x96_HOST; 355 356 /* AMD PLL quirk */ 357 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) 358 xhci->quirks |= XHCI_AMD_PLL_FIX; 359 360 if (pdev->vendor == PCI_VENDOR_ID_AMD && 361 (pdev->device == 0x145c || 362 pdev->device == 0x15e0 || 363 pdev->device == 0x15e1 || 364 pdev->device == 0x43bb)) 365 xhci->quirks |= XHCI_SUSPEND_DELAY; 366 367 if (pdev->vendor == PCI_VENDOR_ID_AMD && 368 (pdev->device == 0x15e0 || pdev->device == 0x15e1)) 369 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; 370 371 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) { 372 xhci->quirks |= XHCI_DISABLE_SPARSE; 373 xhci->quirks |= XHCI_RESET_ON_RESUME; 374 } 375 376 if (pdev->vendor == PCI_VENDOR_ID_AMD) 377 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 378 379 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 380 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 381 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 382 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 383 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 384 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 385 386 if (pdev->vendor == PCI_VENDOR_ID_AMD && 387 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) 388 xhci->quirks |= XHCI_BROKEN_D3COLD_S2I; 389 390 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 391 xhci->quirks |= XHCI_LPM_SUPPORT; 392 xhci->quirks |= XHCI_INTEL_HOST; 393 xhci->quirks |= XHCI_AVOID_BEI; 394 } 395 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 396 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 397 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 398 xhci->limit_active_eps = 64; 399 xhci->quirks |= XHCI_SW_BW_CHECKING; 400 /* 401 * PPT desktop boards DH77EB and DH77DF will power back on after 402 * a few seconds of being shutdown. The fix for this is to 403 * switch the ports from xHCI to EHCI on shutdown. We can't use 404 * DMI information to find those particular boards (since each 405 * vendor will change the board name), so we have to key off all 406 * PPT chipsets. 407 */ 408 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 409 } 410 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 411 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 412 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 413 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 414 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 415 } 416 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 417 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 418 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 419 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 420 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 421 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 422 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 423 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI || 424 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) { 425 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 426 } 427 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 428 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 429 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 430 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 431 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 432 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 433 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI)) 434 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 435 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 436 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 437 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 438 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 439 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 440 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) 441 xhci->quirks |= XHCI_MISSING_CAS; 442 443 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 444 (pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI || 445 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI)) 446 xhci->quirks |= XHCI_RESET_TO_DEFAULT; 447 448 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 449 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 450 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 451 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI || 452 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 453 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 454 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 455 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 456 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || 457 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI || 458 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI || 459 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI)) 460 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 461 462 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 463 pdev->device == PCI_DEVICE_ID_EJ168) { 464 xhci->quirks |= XHCI_RESET_ON_RESUME; 465 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 466 xhci->quirks |= XHCI_BROKEN_STREAMS; 467 } 468 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 469 pdev->device == PCI_DEVICE_ID_EJ188) { 470 xhci->quirks |= XHCI_RESET_ON_RESUME; 471 xhci->quirks |= XHCI_BROKEN_STREAMS; 472 } 473 474 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 475 pdev->device == 0x0014) { 476 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 477 xhci->quirks |= XHCI_ZERO_64B_REGS; 478 } 479 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 480 pdev->device == 0x0015) { 481 xhci->quirks |= XHCI_RESET_ON_RESUME; 482 xhci->quirks |= XHCI_ZERO_64B_REGS; 483 } 484 if (pdev->vendor == PCI_VENDOR_ID_VIA) 485 xhci->quirks |= XHCI_RESET_ON_RESUME; 486 487 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 488 if (pdev->vendor == PCI_VENDOR_ID_VIA && 489 pdev->device == 0x3432) 490 xhci->quirks |= XHCI_BROKEN_STREAMS; 491 492 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) 493 xhci->quirks |= XHCI_LPM_SUPPORT; 494 495 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 496 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) { 497 /* 498 * try to tame the ASMedia 1042 controller which reports 0.96 499 * but appears to behave more like 1.0 500 */ 501 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 502 xhci->quirks |= XHCI_BROKEN_STREAMS; 503 } 504 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 505 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) { 506 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 507 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 508 } 509 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 510 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI || 511 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI || 512 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI)) 513 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 514 515 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 516 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 517 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 518 519 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 520 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 521 522 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 523 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 524 pdev->device == 0x9026) 525 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 526 527 if (pdev->vendor == PCI_VENDOR_ID_AMD && 528 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 || 529 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4)) 530 xhci->quirks |= XHCI_NO_SOFT_RETRY; 531 532 if (pdev->vendor == PCI_VENDOR_ID_ZHAOXIN) { 533 xhci->quirks |= XHCI_ZHAOXIN_HOST; 534 xhci->quirks |= XHCI_LPM_SUPPORT; 535 536 if (pdev->device == 0x9202) { 537 xhci->quirks |= XHCI_RESET_ON_RESUME; 538 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH; 539 } 540 541 if (pdev->device == 0x9203) 542 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH; 543 } 544 545 if (pdev->vendor == PCI_DEVICE_ID_CADENCE && 546 pdev->device == PCI_DEVICE_ID_CADENCE_SSP) 547 xhci->quirks |= XHCI_CDNS_SCTX_QUIRK; 548 549 /* xHC spec requires PCI devices to support D3hot and D3cold */ 550 if (xhci->hci_version >= 0x120) 551 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 552 553 if (xhci->quirks & XHCI_RESET_ON_RESUME) 554 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 555 "QUIRK: Resetting on resume"); 556 } 557 558 #ifdef CONFIG_ACPI 559 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 560 { 561 static const guid_t intel_dsm_guid = 562 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 563 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 564 union acpi_object *obj; 565 566 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 567 NULL); 568 ACPI_FREE(obj); 569 } 570 571 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) 572 { 573 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 574 struct xhci_hub *rhub = &xhci->usb3_rhub; 575 int ret; 576 int i; 577 578 /* This is not the usb3 roothub we are looking for */ 579 if (hcd != rhub->hcd) 580 return; 581 582 if (hdev->maxchild > rhub->num_ports) { 583 dev_err(&hdev->dev, "USB3 roothub port number mismatch\n"); 584 return; 585 } 586 587 for (i = 0; i < hdev->maxchild; i++) { 588 ret = usb_acpi_port_lpm_incapable(hdev, i); 589 590 dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret); 591 592 if (ret >= 0) { 593 rhub->ports[i]->lpm_incapable = ret; 594 continue; 595 } 596 } 597 } 598 599 #else 600 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 601 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { } 602 #endif /* CONFIG_ACPI */ 603 604 /* called during probe() after chip reset completes */ 605 static int xhci_pci_setup(struct usb_hcd *hcd) 606 { 607 struct xhci_hcd *xhci; 608 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 609 int retval; 610 611 xhci = hcd_to_xhci(hcd); 612 if (!xhci->sbrn) 613 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 614 615 /* imod_interval is the interrupt moderation value in nanoseconds. */ 616 xhci->imod_interval = 40000; 617 618 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 619 if (retval) 620 return retval; 621 622 if (!usb_hcd_is_primary_hcd(hcd)) 623 return 0; 624 625 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 626 xhci_pme_acpi_rtd3_enable(pdev); 627 628 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 629 630 /* Find any debug ports */ 631 return xhci_pci_reinit(xhci, pdev); 632 } 633 634 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 635 struct usb_tt *tt, gfp_t mem_flags) 636 { 637 /* Check if acpi claims some USB3 roothub ports are lpm incapable */ 638 if (!hdev->parent) 639 xhci_find_lpm_incapable_ports(hcd, hdev); 640 641 return xhci_update_hub_device(hcd, hdev, tt, mem_flags); 642 } 643 644 /* 645 * We need to register our own PCI probe function (instead of the USB core's 646 * function) in order to create a second roothub under xHCI. 647 */ 648 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 649 { 650 int retval; 651 struct xhci_hcd *xhci; 652 struct usb_hcd *hcd; 653 struct xhci_driver_data *driver_data; 654 struct reset_control *reset; 655 656 driver_data = (struct xhci_driver_data *)id->driver_data; 657 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) { 658 retval = renesas_xhci_check_request_fw(dev, id); 659 if (retval) 660 return retval; 661 } 662 663 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 664 if (IS_ERR(reset)) 665 return PTR_ERR(reset); 666 reset_control_reset(reset); 667 668 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 669 pm_runtime_get_noresume(&dev->dev); 670 671 /* Register the USB 2.0 roothub. 672 * FIXME: USB core must know to register the USB 2.0 roothub first. 673 * This is sort of silly, because we could just set the HCD driver flags 674 * to say USB 2.0, but I'm not sure what the implications would be in 675 * the other parts of the HCD code. 676 */ 677 retval = usb_hcd_pci_probe(dev, &xhci_pci_hc_driver); 678 679 if (retval) 680 goto put_runtime_pm; 681 682 /* USB 2.0 roothub is stored in the PCI device now. */ 683 hcd = dev_get_drvdata(&dev->dev); 684 xhci = hcd_to_xhci(hcd); 685 xhci->reset = reset; 686 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev, 687 pci_name(dev), hcd); 688 if (!xhci->shared_hcd) { 689 retval = -ENOMEM; 690 goto dealloc_usb2_hcd; 691 } 692 693 retval = xhci_ext_cap_init(xhci); 694 if (retval) 695 goto put_usb3_hcd; 696 697 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 698 IRQF_SHARED); 699 if (retval) 700 goto put_usb3_hcd; 701 /* Roothub already marked as USB 3.0 speed */ 702 703 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 704 HCC_MAX_PSA(xhci->hcc_params) >= 4) 705 xhci->shared_hcd->can_do_streams = 1; 706 707 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 708 pm_runtime_put_noidle(&dev->dev); 709 710 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0) 711 pm_runtime_forbid(&dev->dev); 712 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 713 pm_runtime_allow(&dev->dev); 714 715 dma_set_max_seg_size(&dev->dev, UINT_MAX); 716 717 return 0; 718 719 put_usb3_hcd: 720 usb_put_hcd(xhci->shared_hcd); 721 dealloc_usb2_hcd: 722 usb_hcd_pci_remove(dev); 723 put_runtime_pm: 724 pm_runtime_put_noidle(&dev->dev); 725 return retval; 726 } 727 728 static void xhci_pci_remove(struct pci_dev *dev) 729 { 730 struct xhci_hcd *xhci; 731 bool set_power_d3; 732 733 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 734 set_power_d3 = xhci->quirks & XHCI_SPURIOUS_WAKEUP; 735 736 xhci->xhc_state |= XHCI_STATE_REMOVING; 737 738 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 739 pm_runtime_forbid(&dev->dev); 740 741 if (xhci->shared_hcd) { 742 usb_remove_hcd(xhci->shared_hcd); 743 usb_put_hcd(xhci->shared_hcd); 744 xhci->shared_hcd = NULL; 745 } 746 747 usb_hcd_pci_remove(dev); 748 749 /* Workaround for spurious wakeups at shutdown with HSW */ 750 if (set_power_d3) 751 pci_set_power_state(dev, PCI_D3hot); 752 } 753 754 /* 755 * In some Intel xHCI controllers, in order to get D3 working, 756 * through a vendor specific SSIC CONFIG register at offset 0x883c, 757 * SSIC PORT need to be marked as "unused" before putting xHCI 758 * into D3. After D3 exit, the SSIC port need to be marked as "used". 759 * Without this change, xHCI might not enter D3 state. 760 */ 761 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 762 { 763 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 764 u32 val; 765 void __iomem *reg; 766 int i; 767 768 for (i = 0; i < SSIC_PORT_NUM; i++) { 769 reg = (void __iomem *) xhci->cap_regs + 770 SSIC_PORT_CFG2 + 771 i * SSIC_PORT_CFG2_OFFSET; 772 773 /* Notify SSIC that SSIC profile programming is not done. */ 774 val = readl(reg) & ~PROG_DONE; 775 writel(val, reg); 776 777 /* Mark SSIC port as unused(suspend) or used(resume) */ 778 val = readl(reg); 779 if (suspend) 780 val |= SSIC_PORT_UNUSED; 781 else 782 val &= ~SSIC_PORT_UNUSED; 783 writel(val, reg); 784 785 /* Notify SSIC that SSIC profile programming is done */ 786 val = readl(reg) | PROG_DONE; 787 writel(val, reg); 788 readl(reg); 789 } 790 } 791 792 /* 793 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 794 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 795 */ 796 static void xhci_pme_quirk(struct usb_hcd *hcd) 797 { 798 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 799 void __iomem *reg; 800 u32 val; 801 802 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 803 val = readl(reg); 804 writel(val | BIT(28), reg); 805 readl(reg); 806 } 807 808 static void xhci_sparse_control_quirk(struct usb_hcd *hcd) 809 { 810 u32 reg; 811 812 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE); 813 reg &= ~BIT(SPARSE_DISABLE_BIT); 814 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE); 815 } 816 817 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 818 { 819 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 820 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 821 int ret; 822 823 /* 824 * Systems with the TI redriver that loses port status change events 825 * need to have the registers polled during D3, so avoid D3cold. 826 */ 827 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 828 pci_d3cold_disable(pdev); 829 830 #ifdef CONFIG_SUSPEND 831 /* d3cold is broken, but only when s2idle is used */ 832 if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE && 833 xhci->quirks & (XHCI_BROKEN_D3COLD_S2I)) 834 pci_d3cold_disable(pdev); 835 #endif 836 837 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 838 xhci_pme_quirk(hcd); 839 840 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 841 xhci_ssic_port_unused_quirk(hcd, true); 842 843 if (xhci->quirks & XHCI_DISABLE_SPARSE) 844 xhci_sparse_control_quirk(hcd); 845 846 ret = xhci_suspend(xhci, do_wakeup); 847 848 /* synchronize irq when using MSI-X */ 849 xhci_msix_sync_irqs(xhci); 850 851 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 852 xhci_ssic_port_unused_quirk(hcd, false); 853 854 return ret; 855 } 856 857 static int xhci_pci_resume(struct usb_hcd *hcd, pm_message_t msg) 858 { 859 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 860 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 861 int retval = 0; 862 863 reset_control_reset(xhci->reset); 864 865 /* The BIOS on systems with the Intel Panther Point chipset may or may 866 * not support xHCI natively. That means that during system resume, it 867 * may switch the ports back to EHCI so that users can use their 868 * keyboard to select a kernel from GRUB after resume from hibernate. 869 * 870 * The BIOS is supposed to remember whether the OS had xHCI ports 871 * enabled before resume, and switch the ports back to xHCI when the 872 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 873 * writers. 874 * 875 * Unconditionally switch the ports back to xHCI after a system resume. 876 * It should not matter whether the EHCI or xHCI controller is 877 * resumed first. It's enough to do the switchover in xHCI because 878 * USB core won't notice anything as the hub driver doesn't start 879 * running again until after all the devices (including both EHCI and 880 * xHCI host controllers) have been resumed. 881 */ 882 883 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 884 usb_enable_intel_xhci_ports(pdev); 885 886 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 887 xhci_ssic_port_unused_quirk(hcd, false); 888 889 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 890 xhci_pme_quirk(hcd); 891 892 retval = xhci_resume(xhci, msg); 893 return retval; 894 } 895 896 static int xhci_pci_poweroff_late(struct usb_hcd *hcd, bool do_wakeup) 897 { 898 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 899 struct xhci_port *port; 900 struct usb_device *udev; 901 unsigned int slot_id; 902 u32 portsc; 903 int i; 904 905 /* 906 * Systems with XHCI_RESET_TO_DEFAULT quirk have boot firmware that 907 * cause significant boot delay if usb ports are in suspended U3 state 908 * during boot. Some USB devices survive in U3 state over S4 hibernate 909 * 910 * Disable ports that are in U3 if remote wake is not enabled for either 911 * host controller or connected device 912 */ 913 914 if (!(xhci->quirks & XHCI_RESET_TO_DEFAULT)) 915 return 0; 916 917 for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) { 918 port = &xhci->hw_ports[i]; 919 portsc = readl(port->addr); 920 921 if ((portsc & PORT_PLS_MASK) != XDEV_U3) 922 continue; 923 924 slot_id = xhci_find_slot_id_by_port(port->rhub->hcd, xhci, 925 port->hcd_portnum + 1); 926 if (!slot_id || !xhci->devs[slot_id]) { 927 xhci_err(xhci, "No dev for slot_id %d for port %d-%d in U3\n", 928 slot_id, port->rhub->hcd->self.busnum, port->hcd_portnum + 1); 929 continue; 930 } 931 932 udev = xhci->devs[slot_id]->udev; 933 934 /* if wakeup is enabled then don't disable the port */ 935 if (udev->do_remote_wakeup && do_wakeup) 936 continue; 937 938 xhci_dbg(xhci, "port %d-%d in U3 without wakeup, disable it\n", 939 port->rhub->hcd->self.busnum, port->hcd_portnum + 1); 940 portsc = xhci_port_state_to_neutral(portsc); 941 writel(portsc | PORT_PE, port->addr); 942 } 943 944 return 0; 945 } 946 947 static void xhci_pci_shutdown(struct usb_hcd *hcd) 948 { 949 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 950 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 951 952 xhci_shutdown(hcd); 953 xhci_cleanup_msix(xhci); 954 955 /* Yet another workaround for spurious wakeups at shutdown with HSW */ 956 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 957 pci_set_power_state(pdev, PCI_D3hot); 958 } 959 960 /*-------------------------------------------------------------------------*/ 961 962 static const struct xhci_driver_data reneses_data = { 963 .quirks = XHCI_RENESAS_FW_QUIRK, 964 .firmware = "renesas_usb_fw.mem", 965 }; 966 967 /* PCI driver selection metadata; PCI hotplugging uses this */ 968 static const struct pci_device_id pci_ids[] = { 969 { PCI_DEVICE(0x1912, 0x0014), 970 .driver_data = (unsigned long)&reneses_data, 971 }, 972 { PCI_DEVICE(0x1912, 0x0015), 973 .driver_data = (unsigned long)&reneses_data, 974 }, 975 /* handle any USB 3.0 xHCI controller */ 976 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 977 }, 978 { /* end: all zeroes */ } 979 }; 980 MODULE_DEVICE_TABLE(pci, pci_ids); 981 982 /* 983 * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't 984 * load firmware, so don't encumber the xhci-pci driver with it. 985 */ 986 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS) 987 MODULE_FIRMWARE("renesas_usb_fw.mem"); 988 #endif 989 990 /* pci driver glue; this is a "new style" PCI driver module */ 991 static struct pci_driver xhci_pci_driver = { 992 .name = hcd_name, 993 .id_table = pci_ids, 994 995 .probe = xhci_pci_probe, 996 .remove = xhci_pci_remove, 997 /* suspend and resume implemented later */ 998 999 .shutdown = usb_hcd_pci_shutdown, 1000 .driver = { 1001 .pm = pm_ptr(&usb_hcd_pci_pm_ops), 1002 }, 1003 }; 1004 1005 static int __init xhci_pci_init(void) 1006 { 1007 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 1008 xhci_pci_hc_driver.pci_suspend = pm_ptr(xhci_pci_suspend); 1009 xhci_pci_hc_driver.pci_resume = pm_ptr(xhci_pci_resume); 1010 xhci_pci_hc_driver.pci_poweroff_late = pm_ptr(xhci_pci_poweroff_late); 1011 xhci_pci_hc_driver.shutdown = pm_ptr(xhci_pci_shutdown); 1012 xhci_pci_hc_driver.stop = xhci_pci_stop; 1013 return pci_register_driver(&xhci_pci_driver); 1014 } 1015 module_init(xhci_pci_init); 1016 1017 static void __exit xhci_pci_exit(void) 1018 { 1019 pci_unregister_driver(&xhci_pci_driver); 1020 } 1021 module_exit(xhci_pci_exit); 1022 1023 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 1024 MODULE_LICENSE("GPL"); 1025