1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 #include <linux/reset.h> 16 #include <linux/suspend.h> 17 18 #include "xhci.h" 19 #include "xhci-trace.h" 20 #include "xhci-pci.h" 21 22 #define SSIC_PORT_NUM 2 23 #define SSIC_PORT_CFG2 0x880c 24 #define SSIC_PORT_CFG2_OFFSET 0x30 25 #define PROG_DONE (1 << 30) 26 #define SSIC_PORT_UNUSED (1 << 31) 27 #define SPARSE_DISABLE_BIT 17 28 #define SPARSE_CNTL_ENABLE 0xC12C 29 30 /* Device for a quirk */ 31 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 32 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100 35 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 36 37 #define PCI_VENDOR_ID_ETRON 0x1b6f 38 #define PCI_DEVICE_ID_EJ168 0x7023 39 #define PCI_DEVICE_ID_EJ188 0x7052 40 41 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 42 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 43 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 44 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 45 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 46 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 47 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 48 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 49 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 50 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 53 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1 54 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 55 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 56 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 57 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 58 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 59 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 60 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af 61 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13 62 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138 63 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed 64 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI 0x54ed 65 66 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639 67 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 68 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 69 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 70 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 71 72 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042 73 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 74 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242 75 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142 76 #define PCI_DEVICE_ID_ASMEDIA_3042_XHCI 0x3042 77 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242 78 79 #define PCI_DEVICE_ID_CADENCE 0x17CD 80 #define PCI_DEVICE_ID_CADENCE_SSP 0x0200 81 82 static const char hcd_name[] = "xhci_hcd"; 83 84 static struct hc_driver __read_mostly xhci_pci_hc_driver; 85 86 static int xhci_pci_setup(struct usb_hcd *hcd); 87 static int xhci_pci_run(struct usb_hcd *hcd); 88 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 89 struct usb_tt *tt, gfp_t mem_flags); 90 91 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 92 .reset = xhci_pci_setup, 93 .start = xhci_pci_run, 94 .update_hub_device = xhci_pci_update_hub_device, 95 }; 96 97 static void xhci_msix_sync_irqs(struct xhci_hcd *xhci) 98 { 99 struct usb_hcd *hcd = xhci_to_hcd(xhci); 100 101 if (hcd->msix_enabled) { 102 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 103 int i; 104 105 for (i = 0; i < xhci->msix_count; i++) 106 synchronize_irq(pci_irq_vector(pdev, i)); 107 } 108 } 109 110 /* Free any IRQs and disable MSI-X */ 111 static void xhci_cleanup_msix(struct xhci_hcd *xhci) 112 { 113 struct usb_hcd *hcd = xhci_to_hcd(xhci); 114 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 115 116 /* return if using legacy interrupt */ 117 if (hcd->irq > 0) 118 return; 119 120 if (hcd->msix_enabled) { 121 int i; 122 123 for (i = 0; i < xhci->msix_count; i++) 124 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci)); 125 } else { 126 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci)); 127 } 128 129 pci_free_irq_vectors(pdev); 130 hcd->msix_enabled = 0; 131 } 132 133 /* 134 * Set up MSI 135 */ 136 static int xhci_setup_msi(struct xhci_hcd *xhci) 137 { 138 int ret; 139 /* 140 * TODO:Check with MSI Soc for sysdev 141 */ 142 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); 143 144 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 145 if (ret < 0) { 146 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 147 "failed to allocate MSI entry"); 148 return ret; 149 } 150 151 ret = request_irq(pdev->irq, xhci_msi_irq, 152 0, "xhci_hcd", xhci_to_hcd(xhci)); 153 if (ret) { 154 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 155 "disable MSI interrupt"); 156 pci_free_irq_vectors(pdev); 157 } 158 159 return ret; 160 } 161 162 /* 163 * Set up MSI-X 164 */ 165 static int xhci_setup_msix(struct xhci_hcd *xhci) 166 { 167 int i, ret; 168 struct usb_hcd *hcd = xhci_to_hcd(xhci); 169 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 170 171 /* 172 * calculate number of msi-x vectors supported. 173 * - HCS_MAX_INTRS: the max number of interrupts the host can handle, 174 * with max number of interrupters based on the xhci HCSPARAMS1. 175 * - num_online_cpus: maximum msi-x vectors per CPUs core. 176 * Add additional 1 vector to ensure always available interrupt. 177 */ 178 xhci->msix_count = min(num_online_cpus() + 1, 179 HCS_MAX_INTRS(xhci->hcs_params1)); 180 181 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count, 182 PCI_IRQ_MSIX); 183 if (ret < 0) { 184 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 185 "Failed to enable MSI-X"); 186 return ret; 187 } 188 189 for (i = 0; i < xhci->msix_count; i++) { 190 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0, 191 "xhci_hcd", xhci_to_hcd(xhci)); 192 if (ret) 193 goto disable_msix; 194 } 195 196 hcd->msix_enabled = 1; 197 return ret; 198 199 disable_msix: 200 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt"); 201 while (--i >= 0) 202 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci)); 203 pci_free_irq_vectors(pdev); 204 return ret; 205 } 206 207 static int xhci_try_enable_msi(struct usb_hcd *hcd) 208 { 209 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 210 struct pci_dev *pdev; 211 int ret; 212 213 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); 214 /* 215 * Some Fresco Logic host controllers advertise MSI, but fail to 216 * generate interrupts. Don't even try to enable MSI. 217 */ 218 if (xhci->quirks & XHCI_BROKEN_MSI) 219 goto legacy_irq; 220 221 /* unregister the legacy interrupt */ 222 if (hcd->irq) 223 free_irq(hcd->irq, hcd); 224 hcd->irq = 0; 225 226 ret = xhci_setup_msix(xhci); 227 if (ret) 228 /* fall back to msi*/ 229 ret = xhci_setup_msi(xhci); 230 231 if (!ret) { 232 hcd->msi_enabled = 1; 233 return 0; 234 } 235 236 if (!pdev->irq) { 237 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n"); 238 return -EINVAL; 239 } 240 241 legacy_irq: 242 if (!strlen(hcd->irq_descr)) 243 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d", 244 hcd->driver->description, hcd->self.busnum); 245 246 /* fall back to legacy interrupt*/ 247 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, 248 hcd->irq_descr, hcd); 249 if (ret) { 250 xhci_err(xhci, "request interrupt %d failed\n", 251 pdev->irq); 252 return ret; 253 } 254 hcd->irq = pdev->irq; 255 return 0; 256 } 257 258 static int xhci_pci_run(struct usb_hcd *hcd) 259 { 260 int ret; 261 262 if (usb_hcd_is_primary_hcd(hcd)) { 263 ret = xhci_try_enable_msi(hcd); 264 if (ret) 265 return ret; 266 } 267 268 return xhci_run(hcd); 269 } 270 271 static void xhci_pci_stop(struct usb_hcd *hcd) 272 { 273 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 274 275 xhci_stop(hcd); 276 277 if (usb_hcd_is_primary_hcd(hcd)) 278 xhci_cleanup_msix(xhci); 279 } 280 281 /* called after powerup, by probe or system-pm "wakeup" */ 282 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 283 { 284 /* 285 * TODO: Implement finding debug ports later. 286 * TODO: see if there are any quirks that need to be added to handle 287 * new extended capabilities. 288 */ 289 290 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 291 if (!pci_set_mwi(pdev)) 292 xhci_dbg(xhci, "MWI active\n"); 293 294 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 295 return 0; 296 } 297 298 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 299 { 300 struct pci_dev *pdev = to_pci_dev(dev); 301 struct xhci_driver_data *driver_data; 302 const struct pci_device_id *id; 303 304 id = pci_match_id(to_pci_driver(pdev->dev.driver)->id_table, pdev); 305 306 if (id && id->driver_data) { 307 driver_data = (struct xhci_driver_data *)id->driver_data; 308 xhci->quirks |= driver_data->quirks; 309 } 310 311 /* Look for vendor-specific quirks */ 312 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 313 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 314 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 315 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 316 pdev->revision == 0x0) { 317 xhci->quirks |= XHCI_RESET_EP_QUIRK; 318 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 319 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated"); 320 } 321 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 322 pdev->revision == 0x4) { 323 xhci->quirks |= XHCI_SLOW_SUSPEND; 324 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 325 "QUIRK: Fresco Logic xHC revision %u" 326 "must be suspended extra slowly", 327 pdev->revision); 328 } 329 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 330 xhci->quirks |= XHCI_BROKEN_STREAMS; 331 /* Fresco Logic confirms: all revisions of this chip do not 332 * support MSI, even though some of them claim to in their PCI 333 * capabilities. 334 */ 335 xhci->quirks |= XHCI_BROKEN_MSI; 336 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 337 "QUIRK: Fresco Logic revision %u " 338 "has broken MSI implementation", 339 pdev->revision); 340 } 341 342 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 343 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 344 xhci->quirks |= XHCI_BROKEN_STREAMS; 345 346 if (pdev->vendor == PCI_VENDOR_ID_NEC) 347 xhci->quirks |= XHCI_NEC_HOST; 348 349 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 350 xhci->quirks |= XHCI_AMD_0x96_HOST; 351 352 /* AMD PLL quirk */ 353 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) 354 xhci->quirks |= XHCI_AMD_PLL_FIX; 355 356 if (pdev->vendor == PCI_VENDOR_ID_AMD && 357 (pdev->device == 0x145c || 358 pdev->device == 0x15e0 || 359 pdev->device == 0x15e1 || 360 pdev->device == 0x43bb)) 361 xhci->quirks |= XHCI_SUSPEND_DELAY; 362 363 if (pdev->vendor == PCI_VENDOR_ID_AMD && 364 (pdev->device == 0x15e0 || pdev->device == 0x15e1)) 365 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; 366 367 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) { 368 xhci->quirks |= XHCI_DISABLE_SPARSE; 369 xhci->quirks |= XHCI_RESET_ON_RESUME; 370 } 371 372 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x43f7) 373 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 374 375 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 376 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 377 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 378 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 379 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 380 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 381 382 if (pdev->vendor == PCI_VENDOR_ID_AMD && 383 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) 384 xhci->quirks |= XHCI_BROKEN_D3COLD_S2I; 385 386 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 387 xhci->quirks |= XHCI_LPM_SUPPORT; 388 xhci->quirks |= XHCI_INTEL_HOST; 389 xhci->quirks |= XHCI_AVOID_BEI; 390 } 391 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 392 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 393 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 394 xhci->limit_active_eps = 64; 395 xhci->quirks |= XHCI_SW_BW_CHECKING; 396 /* 397 * PPT desktop boards DH77EB and DH77DF will power back on after 398 * a few seconds of being shutdown. The fix for this is to 399 * switch the ports from xHCI to EHCI on shutdown. We can't use 400 * DMI information to find those particular boards (since each 401 * vendor will change the board name), so we have to key off all 402 * PPT chipsets. 403 */ 404 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 405 } 406 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 407 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 408 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 409 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 410 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 411 } 412 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 413 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 414 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 415 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 416 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 417 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 418 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 419 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI || 420 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) { 421 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 422 } 423 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 424 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 425 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 426 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 427 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 428 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 429 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI)) 430 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 431 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 432 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 433 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 434 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 435 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 436 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) 437 xhci->quirks |= XHCI_MISSING_CAS; 438 439 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 440 (pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI || 441 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI)) 442 xhci->quirks |= XHCI_RESET_TO_DEFAULT; 443 444 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 445 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 446 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 447 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI || 448 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 449 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 450 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 451 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 452 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || 453 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI || 454 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI || 455 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI)) 456 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 457 458 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 459 (pdev->device == PCI_DEVICE_ID_EJ168 || 460 pdev->device == PCI_DEVICE_ID_EJ188)) { 461 xhci->quirks |= XHCI_ETRON_HOST; 462 xhci->quirks |= XHCI_RESET_ON_RESUME; 463 xhci->quirks |= XHCI_BROKEN_STREAMS; 464 } 465 466 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 467 pdev->device == 0x0014) { 468 xhci->quirks |= XHCI_ZERO_64B_REGS; 469 } 470 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 471 pdev->device == 0x0015) { 472 xhci->quirks |= XHCI_RESET_ON_RESUME; 473 xhci->quirks |= XHCI_ZERO_64B_REGS; 474 } 475 if (pdev->vendor == PCI_VENDOR_ID_VIA) 476 xhci->quirks |= XHCI_RESET_ON_RESUME; 477 478 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 479 if (pdev->vendor == PCI_VENDOR_ID_VIA && 480 pdev->device == 0x3432) 481 xhci->quirks |= XHCI_BROKEN_STREAMS; 482 483 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) 484 xhci->quirks |= XHCI_LPM_SUPPORT; 485 486 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 487 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) { 488 /* 489 * try to tame the ASMedia 1042 controller which reports 0.96 490 * but appears to behave more like 1.0 491 */ 492 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 493 xhci->quirks |= XHCI_BROKEN_STREAMS; 494 } 495 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 496 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) { 497 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 498 } 499 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 500 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI || 501 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI || 502 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI)) 503 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 504 505 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 506 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 507 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 508 509 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 510 pdev->device == PCI_DEVICE_ID_ASMEDIA_3042_XHCI) 511 xhci->quirks |= XHCI_RESET_ON_RESUME; 512 513 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 514 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 515 516 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 517 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 518 pdev->device == 0x9026) 519 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 520 521 if (pdev->vendor == PCI_VENDOR_ID_AMD && 522 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 || 523 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4)) 524 xhci->quirks |= XHCI_NO_SOFT_RETRY; 525 526 if (pdev->vendor == PCI_VENDOR_ID_ZHAOXIN) { 527 xhci->quirks |= XHCI_ZHAOXIN_HOST; 528 xhci->quirks |= XHCI_LPM_SUPPORT; 529 530 if (pdev->device == 0x9202) { 531 xhci->quirks |= XHCI_RESET_ON_RESUME; 532 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH; 533 } 534 535 if (pdev->device == 0x9203) 536 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH; 537 } 538 539 if (pdev->vendor == PCI_DEVICE_ID_CADENCE && 540 pdev->device == PCI_DEVICE_ID_CADENCE_SSP) 541 xhci->quirks |= XHCI_CDNS_SCTX_QUIRK; 542 543 /* xHC spec requires PCI devices to support D3hot and D3cold */ 544 if (xhci->hci_version >= 0x120) 545 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 546 547 if (xhci->quirks & XHCI_RESET_ON_RESUME) 548 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 549 "QUIRK: Resetting on resume"); 550 } 551 552 #ifdef CONFIG_ACPI 553 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 554 { 555 static const guid_t intel_dsm_guid = 556 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 557 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 558 union acpi_object *obj; 559 560 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 561 NULL); 562 ACPI_FREE(obj); 563 } 564 565 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) 566 { 567 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 568 struct xhci_hub *rhub = &xhci->usb3_rhub; 569 int ret; 570 int i; 571 572 /* This is not the usb3 roothub we are looking for */ 573 if (hcd != rhub->hcd) 574 return; 575 576 if (hdev->maxchild > rhub->num_ports) { 577 dev_err(&hdev->dev, "USB3 roothub port number mismatch\n"); 578 return; 579 } 580 581 for (i = 0; i < hdev->maxchild; i++) { 582 ret = usb_acpi_port_lpm_incapable(hdev, i); 583 584 dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret); 585 586 if (ret >= 0) { 587 rhub->ports[i]->lpm_incapable = ret; 588 continue; 589 } 590 } 591 } 592 593 #else 594 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 595 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { } 596 #endif /* CONFIG_ACPI */ 597 598 /* called during probe() after chip reset completes */ 599 static int xhci_pci_setup(struct usb_hcd *hcd) 600 { 601 struct xhci_hcd *xhci; 602 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 603 int retval; 604 605 xhci = hcd_to_xhci(hcd); 606 if (!xhci->sbrn) 607 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 608 609 /* imod_interval is the interrupt moderation value in nanoseconds. */ 610 xhci->imod_interval = 40000; 611 612 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 613 if (retval) 614 return retval; 615 616 if (!usb_hcd_is_primary_hcd(hcd)) 617 return 0; 618 619 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 620 xhci_pme_acpi_rtd3_enable(pdev); 621 622 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 623 624 /* Find any debug ports */ 625 return xhci_pci_reinit(xhci, pdev); 626 } 627 628 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 629 struct usb_tt *tt, gfp_t mem_flags) 630 { 631 /* Check if acpi claims some USB3 roothub ports are lpm incapable */ 632 if (!hdev->parent) 633 xhci_find_lpm_incapable_ports(hcd, hdev); 634 635 return xhci_update_hub_device(hcd, hdev, tt, mem_flags); 636 } 637 638 /* 639 * We need to register our own PCI probe function (instead of the USB core's 640 * function) in order to create a second roothub under xHCI. 641 */ 642 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 643 { 644 int retval; 645 struct xhci_hcd *xhci; 646 struct usb_hcd *hcd; 647 struct xhci_driver_data *driver_data; 648 struct reset_control *reset; 649 650 driver_data = (struct xhci_driver_data *)id->driver_data; 651 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) { 652 retval = renesas_xhci_check_request_fw(dev, id); 653 if (retval) 654 return retval; 655 } 656 657 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 658 if (IS_ERR(reset)) 659 return PTR_ERR(reset); 660 reset_control_reset(reset); 661 662 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 663 pm_runtime_get_noresume(&dev->dev); 664 665 /* Register the USB 2.0 roothub. 666 * FIXME: USB core must know to register the USB 2.0 roothub first. 667 * This is sort of silly, because we could just set the HCD driver flags 668 * to say USB 2.0, but I'm not sure what the implications would be in 669 * the other parts of the HCD code. 670 */ 671 retval = usb_hcd_pci_probe(dev, &xhci_pci_hc_driver); 672 673 if (retval) 674 goto put_runtime_pm; 675 676 /* USB 2.0 roothub is stored in the PCI device now. */ 677 hcd = dev_get_drvdata(&dev->dev); 678 xhci = hcd_to_xhci(hcd); 679 xhci->reset = reset; 680 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev, 681 pci_name(dev), hcd); 682 if (!xhci->shared_hcd) { 683 retval = -ENOMEM; 684 goto dealloc_usb2_hcd; 685 } 686 687 retval = xhci_ext_cap_init(xhci); 688 if (retval) 689 goto put_usb3_hcd; 690 691 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 692 IRQF_SHARED); 693 if (retval) 694 goto put_usb3_hcd; 695 /* Roothub already marked as USB 3.0 speed */ 696 697 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 698 HCC_MAX_PSA(xhci->hcc_params) >= 4) 699 xhci->shared_hcd->can_do_streams = 1; 700 701 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 702 pm_runtime_put_noidle(&dev->dev); 703 704 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0) 705 pm_runtime_get(&dev->dev); 706 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 707 pm_runtime_allow(&dev->dev); 708 709 dma_set_max_seg_size(&dev->dev, UINT_MAX); 710 711 return 0; 712 713 put_usb3_hcd: 714 usb_put_hcd(xhci->shared_hcd); 715 dealloc_usb2_hcd: 716 usb_hcd_pci_remove(dev); 717 put_runtime_pm: 718 pm_runtime_put_noidle(&dev->dev); 719 return retval; 720 } 721 722 static void xhci_pci_remove(struct pci_dev *dev) 723 { 724 struct xhci_hcd *xhci; 725 bool set_power_d3; 726 727 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 728 set_power_d3 = xhci->quirks & XHCI_SPURIOUS_WAKEUP; 729 730 xhci->xhc_state |= XHCI_STATE_REMOVING; 731 732 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0) 733 pm_runtime_put(&dev->dev); 734 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 735 pm_runtime_forbid(&dev->dev); 736 737 if (xhci->shared_hcd) { 738 usb_remove_hcd(xhci->shared_hcd); 739 usb_put_hcd(xhci->shared_hcd); 740 xhci->shared_hcd = NULL; 741 } 742 743 usb_hcd_pci_remove(dev); 744 745 /* Workaround for spurious wakeups at shutdown with HSW */ 746 if (set_power_d3) 747 pci_set_power_state(dev, PCI_D3hot); 748 } 749 750 /* 751 * In some Intel xHCI controllers, in order to get D3 working, 752 * through a vendor specific SSIC CONFIG register at offset 0x883c, 753 * SSIC PORT need to be marked as "unused" before putting xHCI 754 * into D3. After D3 exit, the SSIC port need to be marked as "used". 755 * Without this change, xHCI might not enter D3 state. 756 */ 757 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 758 { 759 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 760 u32 val; 761 void __iomem *reg; 762 int i; 763 764 for (i = 0; i < SSIC_PORT_NUM; i++) { 765 reg = (void __iomem *) xhci->cap_regs + 766 SSIC_PORT_CFG2 + 767 i * SSIC_PORT_CFG2_OFFSET; 768 769 /* Notify SSIC that SSIC profile programming is not done. */ 770 val = readl(reg) & ~PROG_DONE; 771 writel(val, reg); 772 773 /* Mark SSIC port as unused(suspend) or used(resume) */ 774 val = readl(reg); 775 if (suspend) 776 val |= SSIC_PORT_UNUSED; 777 else 778 val &= ~SSIC_PORT_UNUSED; 779 writel(val, reg); 780 781 /* Notify SSIC that SSIC profile programming is done */ 782 val = readl(reg) | PROG_DONE; 783 writel(val, reg); 784 readl(reg); 785 } 786 } 787 788 /* 789 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 790 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 791 */ 792 static void xhci_pme_quirk(struct usb_hcd *hcd) 793 { 794 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 795 void __iomem *reg; 796 u32 val; 797 798 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 799 val = readl(reg); 800 writel(val | BIT(28), reg); 801 readl(reg); 802 } 803 804 static void xhci_sparse_control_quirk(struct usb_hcd *hcd) 805 { 806 u32 reg; 807 808 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE); 809 reg &= ~BIT(SPARSE_DISABLE_BIT); 810 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE); 811 } 812 813 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 814 { 815 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 816 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 817 int ret; 818 819 /* 820 * Systems with the TI redriver that loses port status change events 821 * need to have the registers polled during D3, so avoid D3cold. 822 */ 823 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 824 pci_d3cold_disable(pdev); 825 826 #ifdef CONFIG_SUSPEND 827 /* d3cold is broken, but only when s2idle is used */ 828 if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE && 829 xhci->quirks & (XHCI_BROKEN_D3COLD_S2I)) 830 pci_d3cold_disable(pdev); 831 #endif 832 833 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 834 xhci_pme_quirk(hcd); 835 836 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 837 xhci_ssic_port_unused_quirk(hcd, true); 838 839 if (xhci->quirks & XHCI_DISABLE_SPARSE) 840 xhci_sparse_control_quirk(hcd); 841 842 ret = xhci_suspend(xhci, do_wakeup); 843 844 /* synchronize irq when using MSI-X */ 845 xhci_msix_sync_irqs(xhci); 846 847 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 848 xhci_ssic_port_unused_quirk(hcd, false); 849 850 return ret; 851 } 852 853 static int xhci_pci_resume(struct usb_hcd *hcd, pm_message_t msg) 854 { 855 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 856 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 857 int retval = 0; 858 859 reset_control_reset(xhci->reset); 860 861 /* The BIOS on systems with the Intel Panther Point chipset may or may 862 * not support xHCI natively. That means that during system resume, it 863 * may switch the ports back to EHCI so that users can use their 864 * keyboard to select a kernel from GRUB after resume from hibernate. 865 * 866 * The BIOS is supposed to remember whether the OS had xHCI ports 867 * enabled before resume, and switch the ports back to xHCI when the 868 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 869 * writers. 870 * 871 * Unconditionally switch the ports back to xHCI after a system resume. 872 * It should not matter whether the EHCI or xHCI controller is 873 * resumed first. It's enough to do the switchover in xHCI because 874 * USB core won't notice anything as the hub driver doesn't start 875 * running again until after all the devices (including both EHCI and 876 * xHCI host controllers) have been resumed. 877 */ 878 879 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 880 usb_enable_intel_xhci_ports(pdev); 881 882 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 883 xhci_ssic_port_unused_quirk(hcd, false); 884 885 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 886 xhci_pme_quirk(hcd); 887 888 retval = xhci_resume(xhci, msg); 889 return retval; 890 } 891 892 static int xhci_pci_poweroff_late(struct usb_hcd *hcd, bool do_wakeup) 893 { 894 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 895 struct xhci_port *port; 896 struct usb_device *udev; 897 unsigned int slot_id; 898 u32 portsc; 899 int i; 900 901 /* 902 * Systems with XHCI_RESET_TO_DEFAULT quirk have boot firmware that 903 * cause significant boot delay if usb ports are in suspended U3 state 904 * during boot. Some USB devices survive in U3 state over S4 hibernate 905 * 906 * Disable ports that are in U3 if remote wake is not enabled for either 907 * host controller or connected device 908 */ 909 910 if (!(xhci->quirks & XHCI_RESET_TO_DEFAULT)) 911 return 0; 912 913 for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) { 914 port = &xhci->hw_ports[i]; 915 portsc = readl(port->addr); 916 917 if ((portsc & PORT_PLS_MASK) != XDEV_U3) 918 continue; 919 920 slot_id = xhci_find_slot_id_by_port(port->rhub->hcd, xhci, 921 port->hcd_portnum + 1); 922 if (!slot_id || !xhci->devs[slot_id]) { 923 xhci_err(xhci, "No dev for slot_id %d for port %d-%d in U3\n", 924 slot_id, port->rhub->hcd->self.busnum, port->hcd_portnum + 1); 925 continue; 926 } 927 928 udev = xhci->devs[slot_id]->udev; 929 930 /* if wakeup is enabled then don't disable the port */ 931 if (udev->do_remote_wakeup && do_wakeup) 932 continue; 933 934 xhci_dbg(xhci, "port %d-%d in U3 without wakeup, disable it\n", 935 port->rhub->hcd->self.busnum, port->hcd_portnum + 1); 936 portsc = xhci_port_state_to_neutral(portsc); 937 writel(portsc | PORT_PE, port->addr); 938 } 939 940 return 0; 941 } 942 943 static void xhci_pci_shutdown(struct usb_hcd *hcd) 944 { 945 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 946 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 947 948 xhci_shutdown(hcd); 949 xhci_cleanup_msix(xhci); 950 951 /* Yet another workaround for spurious wakeups at shutdown with HSW */ 952 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 953 pci_set_power_state(pdev, PCI_D3hot); 954 } 955 956 /*-------------------------------------------------------------------------*/ 957 958 static const struct xhci_driver_data reneses_data = { 959 .quirks = XHCI_RENESAS_FW_QUIRK, 960 .firmware = "renesas_usb_fw.mem", 961 }; 962 963 /* PCI driver selection metadata; PCI hotplugging uses this */ 964 static const struct pci_device_id pci_ids[] = { 965 { PCI_DEVICE(0x1912, 0x0014), 966 .driver_data = (unsigned long)&reneses_data, 967 }, 968 { PCI_DEVICE(0x1912, 0x0015), 969 .driver_data = (unsigned long)&reneses_data, 970 }, 971 /* handle any USB 3.0 xHCI controller */ 972 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 973 }, 974 { /* end: all zeroes */ } 975 }; 976 MODULE_DEVICE_TABLE(pci, pci_ids); 977 978 /* 979 * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't 980 * load firmware, so don't encumber the xhci-pci driver with it. 981 */ 982 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS) 983 MODULE_FIRMWARE("renesas_usb_fw.mem"); 984 #endif 985 986 /* pci driver glue; this is a "new style" PCI driver module */ 987 static struct pci_driver xhci_pci_driver = { 988 .name = hcd_name, 989 .id_table = pci_ids, 990 991 .probe = xhci_pci_probe, 992 .remove = xhci_pci_remove, 993 /* suspend and resume implemented later */ 994 995 .shutdown = usb_hcd_pci_shutdown, 996 .driver = { 997 .pm = pm_ptr(&usb_hcd_pci_pm_ops), 998 }, 999 }; 1000 1001 static int __init xhci_pci_init(void) 1002 { 1003 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 1004 xhci_pci_hc_driver.pci_suspend = pm_ptr(xhci_pci_suspend); 1005 xhci_pci_hc_driver.pci_resume = pm_ptr(xhci_pci_resume); 1006 xhci_pci_hc_driver.pci_poweroff_late = pm_ptr(xhci_pci_poweroff_late); 1007 xhci_pci_hc_driver.shutdown = pm_ptr(xhci_pci_shutdown); 1008 xhci_pci_hc_driver.stop = xhci_pci_stop; 1009 return pci_register_driver(&xhci_pci_driver); 1010 } 1011 module_init(xhci_pci_init); 1012 1013 static void __exit xhci_pci_exit(void) 1014 { 1015 pci_unregister_driver(&xhci_pci_driver); 1016 } 1017 module_exit(xhci_pci_exit); 1018 1019 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 1020 MODULE_LICENSE("GPL"); 1021