1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 #include <linux/reset.h> 16 17 #include "xhci.h" 18 #include "xhci-trace.h" 19 #include "xhci-pci.h" 20 21 #define SSIC_PORT_NUM 2 22 #define SSIC_PORT_CFG2 0x880c 23 #define SSIC_PORT_CFG2_OFFSET 0x30 24 #define PROG_DONE (1 << 30) 25 #define SSIC_PORT_UNUSED (1 << 31) 26 #define SPARSE_DISABLE_BIT 17 27 #define SPARSE_CNTL_ENABLE 0xC12C 28 29 /* Device for a quirk */ 30 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 31 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 32 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 34 35 #define PCI_VENDOR_ID_ETRON 0x1b6f 36 #define PCI_DEVICE_ID_EJ168 0x7023 37 38 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 39 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 40 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 41 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 42 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 43 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 44 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 45 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 46 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 47 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 48 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 49 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 50 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1 51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 53 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 54 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 55 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 56 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 57 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af 58 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13 59 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138 60 61 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 62 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 63 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 64 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 65 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042 66 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 67 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242 68 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142 69 70 static const char hcd_name[] = "xhci_hcd"; 71 72 static struct hc_driver __read_mostly xhci_pci_hc_driver; 73 74 static int xhci_pci_setup(struct usb_hcd *hcd); 75 76 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 77 .reset = xhci_pci_setup, 78 }; 79 80 /* called after powerup, by probe or system-pm "wakeup" */ 81 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 82 { 83 /* 84 * TODO: Implement finding debug ports later. 85 * TODO: see if there are any quirks that need to be added to handle 86 * new extended capabilities. 87 */ 88 89 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 90 if (!pci_set_mwi(pdev)) 91 xhci_dbg(xhci, "MWI active\n"); 92 93 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 94 return 0; 95 } 96 97 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 98 { 99 struct pci_dev *pdev = to_pci_dev(dev); 100 struct xhci_driver_data *driver_data; 101 const struct pci_device_id *id; 102 103 id = pci_match_id(pdev->driver->id_table, pdev); 104 105 if (id && id->driver_data) { 106 driver_data = (struct xhci_driver_data *)id->driver_data; 107 xhci->quirks |= driver_data->quirks; 108 } 109 110 /* Look for vendor-specific quirks */ 111 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 112 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 113 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 114 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 115 pdev->revision == 0x0) { 116 xhci->quirks |= XHCI_RESET_EP_QUIRK; 117 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 118 "QUIRK: Fresco Logic xHC needs configure" 119 " endpoint cmd after reset endpoint"); 120 } 121 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 122 pdev->revision == 0x4) { 123 xhci->quirks |= XHCI_SLOW_SUSPEND; 124 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 125 "QUIRK: Fresco Logic xHC revision %u" 126 "must be suspended extra slowly", 127 pdev->revision); 128 } 129 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 130 xhci->quirks |= XHCI_BROKEN_STREAMS; 131 /* Fresco Logic confirms: all revisions of this chip do not 132 * support MSI, even though some of them claim to in their PCI 133 * capabilities. 134 */ 135 xhci->quirks |= XHCI_BROKEN_MSI; 136 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 137 "QUIRK: Fresco Logic revision %u " 138 "has broken MSI implementation", 139 pdev->revision); 140 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 141 } 142 143 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 144 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 145 xhci->quirks |= XHCI_BROKEN_STREAMS; 146 147 if (pdev->vendor == PCI_VENDOR_ID_NEC) 148 xhci->quirks |= XHCI_NEC_HOST; 149 150 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 151 xhci->quirks |= XHCI_AMD_0x96_HOST; 152 153 /* AMD PLL quirk */ 154 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) 155 xhci->quirks |= XHCI_AMD_PLL_FIX; 156 157 if (pdev->vendor == PCI_VENDOR_ID_AMD && 158 (pdev->device == 0x145c || 159 pdev->device == 0x15e0 || 160 pdev->device == 0x15e1 || 161 pdev->device == 0x43bb)) 162 xhci->quirks |= XHCI_SUSPEND_DELAY; 163 164 if (pdev->vendor == PCI_VENDOR_ID_AMD && 165 (pdev->device == 0x15e0 || pdev->device == 0x15e1)) 166 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; 167 168 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) 169 xhci->quirks |= XHCI_DISABLE_SPARSE; 170 171 if (pdev->vendor == PCI_VENDOR_ID_AMD) 172 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 173 174 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 175 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 176 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 177 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 178 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 179 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 180 181 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 182 xhci->quirks |= XHCI_LPM_SUPPORT; 183 xhci->quirks |= XHCI_INTEL_HOST; 184 xhci->quirks |= XHCI_AVOID_BEI; 185 } 186 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 187 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 188 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 189 xhci->limit_active_eps = 64; 190 xhci->quirks |= XHCI_SW_BW_CHECKING; 191 /* 192 * PPT desktop boards DH77EB and DH77DF will power back on after 193 * a few seconds of being shutdown. The fix for this is to 194 * switch the ports from xHCI to EHCI on shutdown. We can't use 195 * DMI information to find those particular boards (since each 196 * vendor will change the board name), so we have to key off all 197 * PPT chipsets. 198 */ 199 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 200 } 201 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 202 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 203 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 204 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 205 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 206 } 207 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 208 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 209 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 210 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 211 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 212 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 213 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 214 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI || 215 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) { 216 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 217 } 218 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 219 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 220 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 221 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 222 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 223 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 224 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI)) 225 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 226 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 227 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 228 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 229 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 230 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 231 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) 232 xhci->quirks |= XHCI_MISSING_CAS; 233 234 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 235 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 236 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 237 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI || 238 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 239 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 240 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 241 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 242 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || 243 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI || 244 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI || 245 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI)) 246 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 247 248 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 249 pdev->device == PCI_DEVICE_ID_EJ168) { 250 xhci->quirks |= XHCI_RESET_ON_RESUME; 251 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 252 xhci->quirks |= XHCI_BROKEN_STREAMS; 253 } 254 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 255 pdev->device == 0x0014) { 256 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 257 xhci->quirks |= XHCI_ZERO_64B_REGS; 258 } 259 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 260 pdev->device == 0x0015) { 261 xhci->quirks |= XHCI_RESET_ON_RESUME; 262 xhci->quirks |= XHCI_ZERO_64B_REGS; 263 } 264 if (pdev->vendor == PCI_VENDOR_ID_VIA) 265 xhci->quirks |= XHCI_RESET_ON_RESUME; 266 267 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 268 if (pdev->vendor == PCI_VENDOR_ID_VIA && 269 pdev->device == 0x3432) 270 xhci->quirks |= XHCI_BROKEN_STREAMS; 271 272 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) 273 xhci->quirks |= XHCI_LPM_SUPPORT; 274 275 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 276 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) 277 xhci->quirks |= XHCI_BROKEN_STREAMS; 278 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 279 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 280 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 281 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 282 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI || 283 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI)) 284 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 285 286 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 287 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 288 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 289 290 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 291 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 292 293 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 294 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 295 pdev->device == 0x9026) 296 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 297 298 if (xhci->quirks & XHCI_RESET_ON_RESUME) 299 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 300 "QUIRK: Resetting on resume"); 301 } 302 303 #ifdef CONFIG_ACPI 304 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 305 { 306 static const guid_t intel_dsm_guid = 307 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 308 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 309 union acpi_object *obj; 310 311 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 312 NULL); 313 ACPI_FREE(obj); 314 } 315 #else 316 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 317 #endif /* CONFIG_ACPI */ 318 319 /* called during probe() after chip reset completes */ 320 static int xhci_pci_setup(struct usb_hcd *hcd) 321 { 322 struct xhci_hcd *xhci; 323 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 324 int retval; 325 326 xhci = hcd_to_xhci(hcd); 327 if (!xhci->sbrn) 328 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 329 330 /* imod_interval is the interrupt moderation value in nanoseconds. */ 331 xhci->imod_interval = 40000; 332 333 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 334 if (retval) 335 return retval; 336 337 if (!usb_hcd_is_primary_hcd(hcd)) 338 return 0; 339 340 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 341 xhci_pme_acpi_rtd3_enable(pdev); 342 343 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 344 345 /* Find any debug ports */ 346 return xhci_pci_reinit(xhci, pdev); 347 } 348 349 /* 350 * We need to register our own PCI probe function (instead of the USB core's 351 * function) in order to create a second roothub under xHCI. 352 */ 353 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 354 { 355 int retval; 356 struct xhci_hcd *xhci; 357 struct usb_hcd *hcd; 358 struct xhci_driver_data *driver_data; 359 struct reset_control *reset; 360 361 driver_data = (struct xhci_driver_data *)id->driver_data; 362 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) { 363 retval = renesas_xhci_check_request_fw(dev, id); 364 if (retval) 365 return retval; 366 } 367 368 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 369 if (IS_ERR(reset)) 370 return PTR_ERR(reset); 371 reset_control_reset(reset); 372 373 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 374 pm_runtime_get_noresume(&dev->dev); 375 376 /* Register the USB 2.0 roothub. 377 * FIXME: USB core must know to register the USB 2.0 roothub first. 378 * This is sort of silly, because we could just set the HCD driver flags 379 * to say USB 2.0, but I'm not sure what the implications would be in 380 * the other parts of the HCD code. 381 */ 382 retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver); 383 384 if (retval) 385 goto put_runtime_pm; 386 387 /* USB 2.0 roothub is stored in the PCI device now. */ 388 hcd = dev_get_drvdata(&dev->dev); 389 xhci = hcd_to_xhci(hcd); 390 xhci->reset = reset; 391 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev, 392 pci_name(dev), hcd); 393 if (!xhci->shared_hcd) { 394 retval = -ENOMEM; 395 goto dealloc_usb2_hcd; 396 } 397 398 retval = xhci_ext_cap_init(xhci); 399 if (retval) 400 goto put_usb3_hcd; 401 402 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 403 IRQF_SHARED); 404 if (retval) 405 goto put_usb3_hcd; 406 /* Roothub already marked as USB 3.0 speed */ 407 408 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 409 HCC_MAX_PSA(xhci->hcc_params) >= 4) 410 xhci->shared_hcd->can_do_streams = 1; 411 412 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 413 pm_runtime_put_noidle(&dev->dev); 414 415 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 416 pm_runtime_allow(&dev->dev); 417 418 return 0; 419 420 put_usb3_hcd: 421 usb_put_hcd(xhci->shared_hcd); 422 dealloc_usb2_hcd: 423 usb_hcd_pci_remove(dev); 424 put_runtime_pm: 425 pm_runtime_put_noidle(&dev->dev); 426 return retval; 427 } 428 429 static void xhci_pci_remove(struct pci_dev *dev) 430 { 431 struct xhci_hcd *xhci; 432 433 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 434 if (xhci->quirks & XHCI_RENESAS_FW_QUIRK) 435 renesas_xhci_pci_exit(dev); 436 437 xhci->xhc_state |= XHCI_STATE_REMOVING; 438 439 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 440 pm_runtime_forbid(&dev->dev); 441 442 if (xhci->shared_hcd) { 443 usb_remove_hcd(xhci->shared_hcd); 444 usb_put_hcd(xhci->shared_hcd); 445 xhci->shared_hcd = NULL; 446 } 447 448 /* Workaround for spurious wakeups at shutdown with HSW */ 449 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 450 pci_set_power_state(dev, PCI_D3hot); 451 452 usb_hcd_pci_remove(dev); 453 } 454 455 #ifdef CONFIG_PM 456 /* 457 * In some Intel xHCI controllers, in order to get D3 working, 458 * through a vendor specific SSIC CONFIG register at offset 0x883c, 459 * SSIC PORT need to be marked as "unused" before putting xHCI 460 * into D3. After D3 exit, the SSIC port need to be marked as "used". 461 * Without this change, xHCI might not enter D3 state. 462 */ 463 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 464 { 465 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 466 u32 val; 467 void __iomem *reg; 468 int i; 469 470 for (i = 0; i < SSIC_PORT_NUM; i++) { 471 reg = (void __iomem *) xhci->cap_regs + 472 SSIC_PORT_CFG2 + 473 i * SSIC_PORT_CFG2_OFFSET; 474 475 /* Notify SSIC that SSIC profile programming is not done. */ 476 val = readl(reg) & ~PROG_DONE; 477 writel(val, reg); 478 479 /* Mark SSIC port as unused(suspend) or used(resume) */ 480 val = readl(reg); 481 if (suspend) 482 val |= SSIC_PORT_UNUSED; 483 else 484 val &= ~SSIC_PORT_UNUSED; 485 writel(val, reg); 486 487 /* Notify SSIC that SSIC profile programming is done */ 488 val = readl(reg) | PROG_DONE; 489 writel(val, reg); 490 readl(reg); 491 } 492 } 493 494 /* 495 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 496 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 497 */ 498 static void xhci_pme_quirk(struct usb_hcd *hcd) 499 { 500 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 501 void __iomem *reg; 502 u32 val; 503 504 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 505 val = readl(reg); 506 writel(val | BIT(28), reg); 507 readl(reg); 508 } 509 510 static void xhci_sparse_control_quirk(struct usb_hcd *hcd) 511 { 512 u32 reg; 513 514 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE); 515 reg &= ~BIT(SPARSE_DISABLE_BIT); 516 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE); 517 } 518 519 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 520 { 521 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 522 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 523 int ret; 524 525 /* 526 * Systems with the TI redriver that loses port status change events 527 * need to have the registers polled during D3, so avoid D3cold. 528 */ 529 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 530 pci_d3cold_disable(pdev); 531 532 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 533 xhci_pme_quirk(hcd); 534 535 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 536 xhci_ssic_port_unused_quirk(hcd, true); 537 538 if (xhci->quirks & XHCI_DISABLE_SPARSE) 539 xhci_sparse_control_quirk(hcd); 540 541 ret = xhci_suspend(xhci, do_wakeup); 542 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 543 xhci_ssic_port_unused_quirk(hcd, false); 544 545 return ret; 546 } 547 548 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 549 { 550 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 551 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 552 int retval = 0; 553 554 reset_control_reset(xhci->reset); 555 556 /* The BIOS on systems with the Intel Panther Point chipset may or may 557 * not support xHCI natively. That means that during system resume, it 558 * may switch the ports back to EHCI so that users can use their 559 * keyboard to select a kernel from GRUB after resume from hibernate. 560 * 561 * The BIOS is supposed to remember whether the OS had xHCI ports 562 * enabled before resume, and switch the ports back to xHCI when the 563 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 564 * writers. 565 * 566 * Unconditionally switch the ports back to xHCI after a system resume. 567 * It should not matter whether the EHCI or xHCI controller is 568 * resumed first. It's enough to do the switchover in xHCI because 569 * USB core won't notice anything as the hub driver doesn't start 570 * running again until after all the devices (including both EHCI and 571 * xHCI host controllers) have been resumed. 572 */ 573 574 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 575 usb_enable_intel_xhci_ports(pdev); 576 577 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 578 xhci_ssic_port_unused_quirk(hcd, false); 579 580 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 581 xhci_pme_quirk(hcd); 582 583 retval = xhci_resume(xhci, hibernated); 584 return retval; 585 } 586 587 static void xhci_pci_shutdown(struct usb_hcd *hcd) 588 { 589 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 590 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 591 592 xhci_shutdown(hcd); 593 594 /* Yet another workaround for spurious wakeups at shutdown with HSW */ 595 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 596 pci_set_power_state(pdev, PCI_D3hot); 597 } 598 #endif /* CONFIG_PM */ 599 600 /*-------------------------------------------------------------------------*/ 601 602 static const struct xhci_driver_data reneses_data = { 603 .quirks = XHCI_RENESAS_FW_QUIRK, 604 .firmware = "renesas_usb_fw.mem", 605 }; 606 607 /* PCI driver selection metadata; PCI hotplugging uses this */ 608 static const struct pci_device_id pci_ids[] = { 609 { PCI_DEVICE(0x1912, 0x0014), 610 .driver_data = (unsigned long)&reneses_data, 611 }, 612 { PCI_DEVICE(0x1912, 0x0015), 613 .driver_data = (unsigned long)&reneses_data, 614 }, 615 /* handle any USB 3.0 xHCI controller */ 616 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 617 }, 618 { /* end: all zeroes */ } 619 }; 620 MODULE_DEVICE_TABLE(pci, pci_ids); 621 MODULE_FIRMWARE("renesas_usb_fw.mem"); 622 623 /* pci driver glue; this is a "new style" PCI driver module */ 624 static struct pci_driver xhci_pci_driver = { 625 .name = hcd_name, 626 .id_table = pci_ids, 627 628 .probe = xhci_pci_probe, 629 .remove = xhci_pci_remove, 630 /* suspend and resume implemented later */ 631 632 .shutdown = usb_hcd_pci_shutdown, 633 #ifdef CONFIG_PM 634 .driver = { 635 .pm = &usb_hcd_pci_pm_ops 636 }, 637 #endif 638 }; 639 640 static int __init xhci_pci_init(void) 641 { 642 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 643 #ifdef CONFIG_PM 644 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend; 645 xhci_pci_hc_driver.pci_resume = xhci_pci_resume; 646 xhci_pci_hc_driver.shutdown = xhci_pci_shutdown; 647 #endif 648 return pci_register_driver(&xhci_pci_driver); 649 } 650 module_init(xhci_pci_init); 651 652 static void __exit xhci_pci_exit(void) 653 { 654 pci_unregister_driver(&xhci_pci_driver); 655 } 656 module_exit(xhci_pci_exit); 657 658 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 659 MODULE_LICENSE("GPL"); 660