1 /* 2 * xHCI host controller driver PCI Bus Glue. 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/pci.h> 24 #include <linux/slab.h> 25 26 #include "xhci.h" 27 28 /* Device for a quirk */ 29 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 30 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 31 32 #define PCI_VENDOR_ID_ETRON 0x1b6f 33 #define PCI_DEVICE_ID_ASROCK_P67 0x7023 34 35 static const char hcd_name[] = "xhci_hcd"; 36 37 /* called after powerup, by probe or system-pm "wakeup" */ 38 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 39 { 40 /* 41 * TODO: Implement finding debug ports later. 42 * TODO: see if there are any quirks that need to be added to handle 43 * new extended capabilities. 44 */ 45 46 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 47 if (!pci_set_mwi(pdev)) 48 xhci_dbg(xhci, "MWI active\n"); 49 50 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 51 return 0; 52 } 53 54 /* called during probe() after chip reset completes */ 55 static int xhci_pci_setup(struct usb_hcd *hcd) 56 { 57 struct xhci_hcd *xhci; 58 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 59 int retval; 60 u32 temp; 61 62 hcd->self.sg_tablesize = TRBS_PER_SEGMENT - 2; 63 64 if (usb_hcd_is_primary_hcd(hcd)) { 65 xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL); 66 if (!xhci) 67 return -ENOMEM; 68 *((struct xhci_hcd **) hcd->hcd_priv) = xhci; 69 xhci->main_hcd = hcd; 70 /* Mark the first roothub as being USB 2.0. 71 * The xHCI driver will register the USB 3.0 roothub. 72 */ 73 hcd->speed = HCD_USB2; 74 hcd->self.root_hub->speed = USB_SPEED_HIGH; 75 /* 76 * USB 2.0 roothub under xHCI has an integrated TT, 77 * (rate matching hub) as opposed to having an OHCI/UHCI 78 * companion controller. 79 */ 80 hcd->has_tt = 1; 81 } else { 82 /* xHCI private pointer was set in xhci_pci_probe for the second 83 * registered roothub. 84 */ 85 xhci = hcd_to_xhci(hcd); 86 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params); 87 if (HCC_64BIT_ADDR(temp)) { 88 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n"); 89 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)); 90 } else { 91 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32)); 92 } 93 return 0; 94 } 95 96 xhci->cap_regs = hcd->regs; 97 xhci->op_regs = hcd->regs + 98 HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase)); 99 xhci->run_regs = hcd->regs + 100 (xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK); 101 /* Cache read-only capability registers */ 102 xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1); 103 xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2); 104 xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3); 105 xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hc_capbase); 106 xhci->hci_version = HC_VERSION(xhci->hcc_params); 107 xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params); 108 xhci_print_registers(xhci); 109 110 /* Look for vendor-specific quirks */ 111 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 112 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) { 113 if (pdev->revision == 0x0) { 114 xhci->quirks |= XHCI_RESET_EP_QUIRK; 115 xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure" 116 " endpoint cmd after reset endpoint\n"); 117 } 118 /* Fresco Logic confirms: all revisions of this chip do not 119 * support MSI, even though some of them claim to in their PCI 120 * capabilities. 121 */ 122 xhci->quirks |= XHCI_BROKEN_MSI; 123 xhci_dbg(xhci, "QUIRK: Fresco Logic revision %u " 124 "has broken MSI implementation\n", 125 pdev->revision); 126 } 127 128 if (pdev->vendor == PCI_VENDOR_ID_NEC) 129 xhci->quirks |= XHCI_NEC_HOST; 130 131 /* AMD PLL quirk */ 132 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info()) 133 xhci->quirks |= XHCI_AMD_PLL_FIX; 134 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 135 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 136 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 137 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 138 xhci->limit_active_eps = 64; 139 } 140 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 141 pdev->device == PCI_DEVICE_ID_ASROCK_P67) { 142 xhci->quirks |= XHCI_RESET_ON_RESUME; 143 xhci_dbg(xhci, "QUIRK: Resetting on resume\n"); 144 } 145 146 /* Make sure the HC is halted. */ 147 retval = xhci_halt(xhci); 148 if (retval) 149 goto error; 150 151 xhci_dbg(xhci, "Resetting HCD\n"); 152 /* Reset the internal HC memory state and registers. */ 153 retval = xhci_reset(xhci); 154 if (retval) 155 goto error; 156 xhci_dbg(xhci, "Reset complete\n"); 157 158 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params); 159 if (HCC_64BIT_ADDR(temp)) { 160 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n"); 161 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)); 162 } else { 163 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32)); 164 } 165 166 xhci_dbg(xhci, "Calling HCD init\n"); 167 /* Initialize HCD and host controller data structures. */ 168 retval = xhci_init(hcd); 169 if (retval) 170 goto error; 171 xhci_dbg(xhci, "Called HCD init\n"); 172 173 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 174 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 175 176 /* Find any debug ports */ 177 retval = xhci_pci_reinit(xhci, pdev); 178 if (!retval) 179 return retval; 180 181 error: 182 kfree(xhci); 183 return retval; 184 } 185 186 /* 187 * We need to register our own PCI probe function (instead of the USB core's 188 * function) in order to create a second roothub under xHCI. 189 */ 190 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 191 { 192 int retval; 193 struct xhci_hcd *xhci; 194 struct hc_driver *driver; 195 struct usb_hcd *hcd; 196 197 driver = (struct hc_driver *)id->driver_data; 198 /* Register the USB 2.0 roothub. 199 * FIXME: USB core must know to register the USB 2.0 roothub first. 200 * This is sort of silly, because we could just set the HCD driver flags 201 * to say USB 2.0, but I'm not sure what the implications would be in 202 * the other parts of the HCD code. 203 */ 204 retval = usb_hcd_pci_probe(dev, id); 205 206 if (retval) 207 return retval; 208 209 /* USB 2.0 roothub is stored in the PCI device now. */ 210 hcd = dev_get_drvdata(&dev->dev); 211 xhci = hcd_to_xhci(hcd); 212 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, 213 pci_name(dev), hcd); 214 if (!xhci->shared_hcd) { 215 retval = -ENOMEM; 216 goto dealloc_usb2_hcd; 217 } 218 219 /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset) 220 * is called by usb_add_hcd(). 221 */ 222 *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci; 223 224 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 225 IRQF_DISABLED | IRQF_SHARED); 226 if (retval) 227 goto put_usb3_hcd; 228 /* Roothub already marked as USB 3.0 speed */ 229 return 0; 230 231 put_usb3_hcd: 232 usb_put_hcd(xhci->shared_hcd); 233 dealloc_usb2_hcd: 234 usb_hcd_pci_remove(dev); 235 return retval; 236 } 237 238 static void xhci_pci_remove(struct pci_dev *dev) 239 { 240 struct xhci_hcd *xhci; 241 242 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 243 if (xhci->shared_hcd) { 244 usb_remove_hcd(xhci->shared_hcd); 245 usb_put_hcd(xhci->shared_hcd); 246 } 247 usb_hcd_pci_remove(dev); 248 kfree(xhci); 249 } 250 251 #ifdef CONFIG_PM 252 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 253 { 254 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 255 int retval = 0; 256 257 if (hcd->state != HC_STATE_SUSPENDED || 258 xhci->shared_hcd->state != HC_STATE_SUSPENDED) 259 return -EINVAL; 260 261 retval = xhci_suspend(xhci); 262 263 return retval; 264 } 265 266 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 267 { 268 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 269 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 270 int retval = 0; 271 272 /* The BIOS on systems with the Intel Panther Point chipset may or may 273 * not support xHCI natively. That means that during system resume, it 274 * may switch the ports back to EHCI so that users can use their 275 * keyboard to select a kernel from GRUB after resume from hibernate. 276 * 277 * The BIOS is supposed to remember whether the OS had xHCI ports 278 * enabled before resume, and switch the ports back to xHCI when the 279 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 280 * writers. 281 * 282 * Unconditionally switch the ports back to xHCI after a system resume. 283 * We can't tell whether the EHCI or xHCI controller will be resumed 284 * first, so we have to do the port switchover in both drivers. Writing 285 * a '1' to the port switchover registers should have no effect if the 286 * port was already switched over. 287 */ 288 if (usb_is_intel_switchable_xhci(pdev)) 289 usb_enable_xhci_ports(pdev); 290 291 retval = xhci_resume(xhci, hibernated); 292 return retval; 293 } 294 #endif /* CONFIG_PM */ 295 296 static const struct hc_driver xhci_pci_hc_driver = { 297 .description = hcd_name, 298 .product_desc = "xHCI Host Controller", 299 .hcd_priv_size = sizeof(struct xhci_hcd *), 300 301 /* 302 * generic hardware linkage 303 */ 304 .irq = xhci_irq, 305 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED, 306 307 /* 308 * basic lifecycle operations 309 */ 310 .reset = xhci_pci_setup, 311 .start = xhci_run, 312 #ifdef CONFIG_PM 313 .pci_suspend = xhci_pci_suspend, 314 .pci_resume = xhci_pci_resume, 315 #endif 316 .stop = xhci_stop, 317 .shutdown = xhci_shutdown, 318 319 /* 320 * managing i/o requests and associated device resources 321 */ 322 .urb_enqueue = xhci_urb_enqueue, 323 .urb_dequeue = xhci_urb_dequeue, 324 .alloc_dev = xhci_alloc_dev, 325 .free_dev = xhci_free_dev, 326 .alloc_streams = xhci_alloc_streams, 327 .free_streams = xhci_free_streams, 328 .add_endpoint = xhci_add_endpoint, 329 .drop_endpoint = xhci_drop_endpoint, 330 .endpoint_reset = xhci_endpoint_reset, 331 .check_bandwidth = xhci_check_bandwidth, 332 .reset_bandwidth = xhci_reset_bandwidth, 333 .address_device = xhci_address_device, 334 .update_hub_device = xhci_update_hub_device, 335 .reset_device = xhci_discover_or_reset_device, 336 337 /* 338 * scheduling support 339 */ 340 .get_frame_number = xhci_get_frame, 341 342 /* Root hub support */ 343 .hub_control = xhci_hub_control, 344 .hub_status_data = xhci_hub_status_data, 345 .bus_suspend = xhci_bus_suspend, 346 .bus_resume = xhci_bus_resume, 347 }; 348 349 /*-------------------------------------------------------------------------*/ 350 351 /* PCI driver selection metadata; PCI hotplugging uses this */ 352 static const struct pci_device_id pci_ids[] = { { 353 /* handle any USB 3.0 xHCI controller */ 354 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 355 .driver_data = (unsigned long) &xhci_pci_hc_driver, 356 }, 357 { /* end: all zeroes */ } 358 }; 359 MODULE_DEVICE_TABLE(pci, pci_ids); 360 361 /* pci driver glue; this is a "new style" PCI driver module */ 362 static struct pci_driver xhci_pci_driver = { 363 .name = (char *) hcd_name, 364 .id_table = pci_ids, 365 366 .probe = xhci_pci_probe, 367 .remove = xhci_pci_remove, 368 /* suspend and resume implemented later */ 369 370 .shutdown = usb_hcd_pci_shutdown, 371 #ifdef CONFIG_PM_SLEEP 372 .driver = { 373 .pm = &usb_hcd_pci_pm_ops 374 }, 375 #endif 376 }; 377 378 int xhci_register_pci(void) 379 { 380 return pci_register_driver(&xhci_pci_driver); 381 } 382 383 void xhci_unregister_pci(void) 384 { 385 pci_unregister_driver(&xhci_pci_driver); 386 } 387