1 /* 2 * xHCI host controller driver PCI Bus Glue. 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/pci.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 27 #include "xhci.h" 28 29 /* Device for a quirk */ 30 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 31 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 32 33 #define PCI_VENDOR_ID_ETRON 0x1b6f 34 #define PCI_DEVICE_ID_ASROCK_P67 0x7023 35 36 static const char hcd_name[] = "xhci_hcd"; 37 38 /* called after powerup, by probe or system-pm "wakeup" */ 39 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 40 { 41 /* 42 * TODO: Implement finding debug ports later. 43 * TODO: see if there are any quirks that need to be added to handle 44 * new extended capabilities. 45 */ 46 47 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 48 if (!pci_set_mwi(pdev)) 49 xhci_dbg(xhci, "MWI active\n"); 50 51 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 52 return 0; 53 } 54 55 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 56 { 57 struct pci_dev *pdev = to_pci_dev(dev); 58 59 /* Look for vendor-specific quirks */ 60 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 61 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) { 62 if (pdev->revision == 0x0) { 63 xhci->quirks |= XHCI_RESET_EP_QUIRK; 64 xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure" 65 " endpoint cmd after reset endpoint\n"); 66 } 67 /* Fresco Logic confirms: all revisions of this chip do not 68 * support MSI, even though some of them claim to in their PCI 69 * capabilities. 70 */ 71 xhci->quirks |= XHCI_BROKEN_MSI; 72 xhci_dbg(xhci, "QUIRK: Fresco Logic revision %u " 73 "has broken MSI implementation\n", 74 pdev->revision); 75 } 76 77 if (pdev->vendor == PCI_VENDOR_ID_NEC) 78 xhci->quirks |= XHCI_NEC_HOST; 79 80 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 81 xhci->quirks |= XHCI_AMD_0x96_HOST; 82 83 /* AMD PLL quirk */ 84 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info()) 85 xhci->quirks |= XHCI_AMD_PLL_FIX; 86 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 87 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 88 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 89 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 90 xhci->limit_active_eps = 64; 91 xhci->quirks |= XHCI_SW_BW_CHECKING; 92 } 93 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 94 pdev->device == PCI_DEVICE_ID_ASROCK_P67) { 95 xhci->quirks |= XHCI_RESET_ON_RESUME; 96 xhci_dbg(xhci, "QUIRK: Resetting on resume\n"); 97 } 98 } 99 100 /* called during probe() after chip reset completes */ 101 static int xhci_pci_setup(struct usb_hcd *hcd) 102 { 103 struct xhci_hcd *xhci; 104 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 105 int retval; 106 107 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 108 if (retval) 109 return retval; 110 111 xhci = hcd_to_xhci(hcd); 112 if (!usb_hcd_is_primary_hcd(hcd)) 113 return 0; 114 115 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 116 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 117 118 /* Find any debug ports */ 119 retval = xhci_pci_reinit(xhci, pdev); 120 if (!retval) 121 return retval; 122 123 kfree(xhci); 124 return retval; 125 } 126 127 /* 128 * We need to register our own PCI probe function (instead of the USB core's 129 * function) in order to create a second roothub under xHCI. 130 */ 131 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 132 { 133 int retval; 134 struct xhci_hcd *xhci; 135 struct hc_driver *driver; 136 struct usb_hcd *hcd; 137 138 driver = (struct hc_driver *)id->driver_data; 139 /* Register the USB 2.0 roothub. 140 * FIXME: USB core must know to register the USB 2.0 roothub first. 141 * This is sort of silly, because we could just set the HCD driver flags 142 * to say USB 2.0, but I'm not sure what the implications would be in 143 * the other parts of the HCD code. 144 */ 145 retval = usb_hcd_pci_probe(dev, id); 146 147 if (retval) 148 return retval; 149 150 /* USB 2.0 roothub is stored in the PCI device now. */ 151 hcd = dev_get_drvdata(&dev->dev); 152 xhci = hcd_to_xhci(hcd); 153 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, 154 pci_name(dev), hcd); 155 if (!xhci->shared_hcd) { 156 retval = -ENOMEM; 157 goto dealloc_usb2_hcd; 158 } 159 160 /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset) 161 * is called by usb_add_hcd(). 162 */ 163 *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci; 164 165 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 166 IRQF_SHARED); 167 if (retval) 168 goto put_usb3_hcd; 169 /* Roothub already marked as USB 3.0 speed */ 170 return 0; 171 172 put_usb3_hcd: 173 usb_put_hcd(xhci->shared_hcd); 174 dealloc_usb2_hcd: 175 usb_hcd_pci_remove(dev); 176 return retval; 177 } 178 179 static void xhci_pci_remove(struct pci_dev *dev) 180 { 181 struct xhci_hcd *xhci; 182 183 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 184 if (xhci->shared_hcd) { 185 usb_remove_hcd(xhci->shared_hcd); 186 usb_put_hcd(xhci->shared_hcd); 187 } 188 usb_hcd_pci_remove(dev); 189 kfree(xhci); 190 } 191 192 #ifdef CONFIG_PM 193 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 194 { 195 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 196 int retval = 0; 197 198 if (hcd->state != HC_STATE_SUSPENDED || 199 xhci->shared_hcd->state != HC_STATE_SUSPENDED) 200 return -EINVAL; 201 202 retval = xhci_suspend(xhci); 203 204 return retval; 205 } 206 207 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 208 { 209 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 210 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 211 int retval = 0; 212 213 /* The BIOS on systems with the Intel Panther Point chipset may or may 214 * not support xHCI natively. That means that during system resume, it 215 * may switch the ports back to EHCI so that users can use their 216 * keyboard to select a kernel from GRUB after resume from hibernate. 217 * 218 * The BIOS is supposed to remember whether the OS had xHCI ports 219 * enabled before resume, and switch the ports back to xHCI when the 220 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 221 * writers. 222 * 223 * Unconditionally switch the ports back to xHCI after a system resume. 224 * We can't tell whether the EHCI or xHCI controller will be resumed 225 * first, so we have to do the port switchover in both drivers. Writing 226 * a '1' to the port switchover registers should have no effect if the 227 * port was already switched over. 228 */ 229 if (usb_is_intel_switchable_xhci(pdev)) 230 usb_enable_xhci_ports(pdev); 231 232 retval = xhci_resume(xhci, hibernated); 233 return retval; 234 } 235 #endif /* CONFIG_PM */ 236 237 static const struct hc_driver xhci_pci_hc_driver = { 238 .description = hcd_name, 239 .product_desc = "xHCI Host Controller", 240 .hcd_priv_size = sizeof(struct xhci_hcd *), 241 242 /* 243 * generic hardware linkage 244 */ 245 .irq = xhci_irq, 246 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED, 247 248 /* 249 * basic lifecycle operations 250 */ 251 .reset = xhci_pci_setup, 252 .start = xhci_run, 253 #ifdef CONFIG_PM 254 .pci_suspend = xhci_pci_suspend, 255 .pci_resume = xhci_pci_resume, 256 #endif 257 .stop = xhci_stop, 258 .shutdown = xhci_shutdown, 259 260 /* 261 * managing i/o requests and associated device resources 262 */ 263 .urb_enqueue = xhci_urb_enqueue, 264 .urb_dequeue = xhci_urb_dequeue, 265 .alloc_dev = xhci_alloc_dev, 266 .free_dev = xhci_free_dev, 267 .alloc_streams = xhci_alloc_streams, 268 .free_streams = xhci_free_streams, 269 .add_endpoint = xhci_add_endpoint, 270 .drop_endpoint = xhci_drop_endpoint, 271 .endpoint_reset = xhci_endpoint_reset, 272 .check_bandwidth = xhci_check_bandwidth, 273 .reset_bandwidth = xhci_reset_bandwidth, 274 .address_device = xhci_address_device, 275 .update_hub_device = xhci_update_hub_device, 276 .reset_device = xhci_discover_or_reset_device, 277 278 /* 279 * scheduling support 280 */ 281 .get_frame_number = xhci_get_frame, 282 283 /* Root hub support */ 284 .hub_control = xhci_hub_control, 285 .hub_status_data = xhci_hub_status_data, 286 .bus_suspend = xhci_bus_suspend, 287 .bus_resume = xhci_bus_resume, 288 /* 289 * call back when device connected and addressed 290 */ 291 .update_device = xhci_update_device, 292 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm, 293 }; 294 295 /*-------------------------------------------------------------------------*/ 296 297 /* PCI driver selection metadata; PCI hotplugging uses this */ 298 static const struct pci_device_id pci_ids[] = { { 299 /* handle any USB 3.0 xHCI controller */ 300 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 301 .driver_data = (unsigned long) &xhci_pci_hc_driver, 302 }, 303 { /* end: all zeroes */ } 304 }; 305 MODULE_DEVICE_TABLE(pci, pci_ids); 306 307 /* pci driver glue; this is a "new style" PCI driver module */ 308 static struct pci_driver xhci_pci_driver = { 309 .name = (char *) hcd_name, 310 .id_table = pci_ids, 311 312 .probe = xhci_pci_probe, 313 .remove = xhci_pci_remove, 314 /* suspend and resume implemented later */ 315 316 .shutdown = usb_hcd_pci_shutdown, 317 #ifdef CONFIG_PM_SLEEP 318 .driver = { 319 .pm = &usb_hcd_pci_pm_ops 320 }, 321 #endif 322 }; 323 324 int __init xhci_register_pci(void) 325 { 326 return pci_register_driver(&xhci_pci_driver); 327 } 328 329 void __exit xhci_unregister_pci(void) 330 { 331 pci_unregister_driver(&xhci_pci_driver); 332 } 333