1 /* 2 * xHCI host controller driver PCI Bus Glue. 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/pci.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/acpi.h> 27 28 #include "xhci.h" 29 #include "xhci-trace.h" 30 31 #define SSIC_PORT_NUM 2 32 #define SSIC_PORT_CFG2 0x880c 33 #define SSIC_PORT_CFG2_OFFSET 0x30 34 #define PROG_DONE (1 << 30) 35 #define SSIC_PORT_UNUSED (1 << 31) 36 37 /* Device for a quirk */ 38 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 39 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 40 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 41 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 42 43 #define PCI_VENDOR_ID_ETRON 0x1b6f 44 #define PCI_DEVICE_ID_EJ168 0x7023 45 46 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 47 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 48 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 49 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 50 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 51 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 52 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 53 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 54 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 55 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 56 57 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 58 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 59 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 60 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 61 62 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 63 64 static const char hcd_name[] = "xhci_hcd"; 65 66 static struct hc_driver __read_mostly xhci_pci_hc_driver; 67 68 static int xhci_pci_setup(struct usb_hcd *hcd); 69 70 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 71 .reset = xhci_pci_setup, 72 }; 73 74 /* called after powerup, by probe or system-pm "wakeup" */ 75 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 76 { 77 /* 78 * TODO: Implement finding debug ports later. 79 * TODO: see if there are any quirks that need to be added to handle 80 * new extended capabilities. 81 */ 82 83 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 84 if (!pci_set_mwi(pdev)) 85 xhci_dbg(xhci, "MWI active\n"); 86 87 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 88 return 0; 89 } 90 91 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 92 { 93 struct pci_dev *pdev = to_pci_dev(dev); 94 95 /* Look for vendor-specific quirks */ 96 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 97 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 98 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 99 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 100 pdev->revision == 0x0) { 101 xhci->quirks |= XHCI_RESET_EP_QUIRK; 102 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 103 "QUIRK: Fresco Logic xHC needs configure" 104 " endpoint cmd after reset endpoint"); 105 } 106 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 107 pdev->revision == 0x4) { 108 xhci->quirks |= XHCI_SLOW_SUSPEND; 109 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 110 "QUIRK: Fresco Logic xHC revision %u" 111 "must be suspended extra slowly", 112 pdev->revision); 113 } 114 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 115 xhci->quirks |= XHCI_BROKEN_STREAMS; 116 /* Fresco Logic confirms: all revisions of this chip do not 117 * support MSI, even though some of them claim to in their PCI 118 * capabilities. 119 */ 120 xhci->quirks |= XHCI_BROKEN_MSI; 121 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 122 "QUIRK: Fresco Logic revision %u " 123 "has broken MSI implementation", 124 pdev->revision); 125 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 126 } 127 128 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 129 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 130 xhci->quirks |= XHCI_BROKEN_STREAMS; 131 132 if (pdev->vendor == PCI_VENDOR_ID_NEC) 133 xhci->quirks |= XHCI_NEC_HOST; 134 135 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 136 xhci->quirks |= XHCI_AMD_0x96_HOST; 137 138 /* AMD PLL quirk */ 139 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info()) 140 xhci->quirks |= XHCI_AMD_PLL_FIX; 141 142 if (pdev->vendor == PCI_VENDOR_ID_AMD) 143 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 144 145 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 146 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 147 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 148 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 149 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 150 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 151 152 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 153 xhci->quirks |= XHCI_LPM_SUPPORT; 154 xhci->quirks |= XHCI_INTEL_HOST; 155 xhci->quirks |= XHCI_AVOID_BEI; 156 } 157 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 158 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 159 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 160 xhci->limit_active_eps = 64; 161 xhci->quirks |= XHCI_SW_BW_CHECKING; 162 /* 163 * PPT desktop boards DH77EB and DH77DF will power back on after 164 * a few seconds of being shutdown. The fix for this is to 165 * switch the ports from xHCI to EHCI on shutdown. We can't use 166 * DMI information to find those particular boards (since each 167 * vendor will change the board name), so we have to key off all 168 * PPT chipsets. 169 */ 170 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 171 } 172 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 173 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 174 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 175 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 176 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 177 } 178 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 179 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 180 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 181 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 182 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 183 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 184 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 185 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) { 186 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 187 } 188 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 189 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) { 190 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 191 } 192 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 193 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 194 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 195 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) 196 xhci->quirks |= XHCI_MISSING_CAS; 197 198 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 199 pdev->device == PCI_DEVICE_ID_EJ168) { 200 xhci->quirks |= XHCI_RESET_ON_RESUME; 201 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 202 xhci->quirks |= XHCI_BROKEN_STREAMS; 203 } 204 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 205 pdev->device == 0x0015) 206 xhci->quirks |= XHCI_RESET_ON_RESUME; 207 if (pdev->vendor == PCI_VENDOR_ID_VIA) 208 xhci->quirks |= XHCI_RESET_ON_RESUME; 209 210 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 211 if (pdev->vendor == PCI_VENDOR_ID_VIA && 212 pdev->device == 0x3432) 213 xhci->quirks |= XHCI_BROKEN_STREAMS; 214 215 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 216 pdev->device == 0x1042) 217 xhci->quirks |= XHCI_BROKEN_STREAMS; 218 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 219 pdev->device == 0x1142) 220 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 221 222 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 223 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 224 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 225 226 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 227 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 228 229 if (xhci->quirks & XHCI_RESET_ON_RESUME) 230 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 231 "QUIRK: Resetting on resume"); 232 } 233 234 #ifdef CONFIG_ACPI 235 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 236 { 237 static const guid_t intel_dsm_guid = 238 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 239 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 240 union acpi_object *obj; 241 242 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 243 NULL); 244 ACPI_FREE(obj); 245 } 246 #else 247 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 248 #endif /* CONFIG_ACPI */ 249 250 /* called during probe() after chip reset completes */ 251 static int xhci_pci_setup(struct usb_hcd *hcd) 252 { 253 struct xhci_hcd *xhci; 254 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 255 int retval; 256 257 xhci = hcd_to_xhci(hcd); 258 if (!xhci->sbrn) 259 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 260 261 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 262 if (retval) 263 return retval; 264 265 if (!usb_hcd_is_primary_hcd(hcd)) 266 return 0; 267 268 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 269 270 /* Find any debug ports */ 271 return xhci_pci_reinit(xhci, pdev); 272 } 273 274 /* 275 * We need to register our own PCI probe function (instead of the USB core's 276 * function) in order to create a second roothub under xHCI. 277 */ 278 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 279 { 280 int retval; 281 struct xhci_hcd *xhci; 282 struct hc_driver *driver; 283 struct usb_hcd *hcd; 284 285 driver = (struct hc_driver *)id->driver_data; 286 287 /* For some HW implementation, a XHCI reset is just not enough... */ 288 if (usb_xhci_needs_pci_reset(dev)) { 289 dev_info(&dev->dev, "Resetting\n"); 290 if (pci_reset_function_locked(dev)) 291 dev_warn(&dev->dev, "Reset failed"); 292 } 293 294 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 295 pm_runtime_get_noresume(&dev->dev); 296 297 /* Register the USB 2.0 roothub. 298 * FIXME: USB core must know to register the USB 2.0 roothub first. 299 * This is sort of silly, because we could just set the HCD driver flags 300 * to say USB 2.0, but I'm not sure what the implications would be in 301 * the other parts of the HCD code. 302 */ 303 retval = usb_hcd_pci_probe(dev, id); 304 305 if (retval) 306 goto put_runtime_pm; 307 308 /* USB 2.0 roothub is stored in the PCI device now. */ 309 hcd = dev_get_drvdata(&dev->dev); 310 xhci = hcd_to_xhci(hcd); 311 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, 312 pci_name(dev), hcd); 313 if (!xhci->shared_hcd) { 314 retval = -ENOMEM; 315 goto dealloc_usb2_hcd; 316 } 317 318 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 319 IRQF_SHARED); 320 if (retval) 321 goto put_usb3_hcd; 322 /* Roothub already marked as USB 3.0 speed */ 323 324 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 325 HCC_MAX_PSA(xhci->hcc_params) >= 4) 326 xhci->shared_hcd->can_do_streams = 1; 327 328 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 329 xhci_pme_acpi_rtd3_enable(dev); 330 331 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 332 pm_runtime_put_noidle(&dev->dev); 333 334 return 0; 335 336 put_usb3_hcd: 337 usb_put_hcd(xhci->shared_hcd); 338 dealloc_usb2_hcd: 339 usb_hcd_pci_remove(dev); 340 put_runtime_pm: 341 pm_runtime_put_noidle(&dev->dev); 342 return retval; 343 } 344 345 static void xhci_pci_remove(struct pci_dev *dev) 346 { 347 struct xhci_hcd *xhci; 348 349 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 350 xhci->xhc_state |= XHCI_STATE_REMOVING; 351 if (xhci->shared_hcd) { 352 usb_remove_hcd(xhci->shared_hcd); 353 usb_put_hcd(xhci->shared_hcd); 354 } 355 356 /* Workaround for spurious wakeups at shutdown with HSW */ 357 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 358 pci_set_power_state(dev, PCI_D3hot); 359 360 usb_hcd_pci_remove(dev); 361 } 362 363 #ifdef CONFIG_PM 364 /* 365 * In some Intel xHCI controllers, in order to get D3 working, 366 * through a vendor specific SSIC CONFIG register at offset 0x883c, 367 * SSIC PORT need to be marked as "unused" before putting xHCI 368 * into D3. After D3 exit, the SSIC port need to be marked as "used". 369 * Without this change, xHCI might not enter D3 state. 370 */ 371 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 372 { 373 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 374 u32 val; 375 void __iomem *reg; 376 int i; 377 378 for (i = 0; i < SSIC_PORT_NUM; i++) { 379 reg = (void __iomem *) xhci->cap_regs + 380 SSIC_PORT_CFG2 + 381 i * SSIC_PORT_CFG2_OFFSET; 382 383 /* Notify SSIC that SSIC profile programming is not done. */ 384 val = readl(reg) & ~PROG_DONE; 385 writel(val, reg); 386 387 /* Mark SSIC port as unused(suspend) or used(resume) */ 388 val = readl(reg); 389 if (suspend) 390 val |= SSIC_PORT_UNUSED; 391 else 392 val &= ~SSIC_PORT_UNUSED; 393 writel(val, reg); 394 395 /* Notify SSIC that SSIC profile programming is done */ 396 val = readl(reg) | PROG_DONE; 397 writel(val, reg); 398 readl(reg); 399 } 400 } 401 402 /* 403 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 404 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 405 */ 406 static void xhci_pme_quirk(struct usb_hcd *hcd) 407 { 408 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 409 void __iomem *reg; 410 u32 val; 411 412 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 413 val = readl(reg); 414 writel(val | BIT(28), reg); 415 readl(reg); 416 } 417 418 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 419 { 420 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 421 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 422 int ret; 423 424 /* 425 * Systems with the TI redriver that loses port status change events 426 * need to have the registers polled during D3, so avoid D3cold. 427 */ 428 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 429 pci_d3cold_disable(pdev); 430 431 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 432 xhci_pme_quirk(hcd); 433 434 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 435 xhci_ssic_port_unused_quirk(hcd, true); 436 437 ret = xhci_suspend(xhci, do_wakeup); 438 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 439 xhci_ssic_port_unused_quirk(hcd, false); 440 441 return ret; 442 } 443 444 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 445 { 446 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 447 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 448 int retval = 0; 449 450 /* The BIOS on systems with the Intel Panther Point chipset may or may 451 * not support xHCI natively. That means that during system resume, it 452 * may switch the ports back to EHCI so that users can use their 453 * keyboard to select a kernel from GRUB after resume from hibernate. 454 * 455 * The BIOS is supposed to remember whether the OS had xHCI ports 456 * enabled before resume, and switch the ports back to xHCI when the 457 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 458 * writers. 459 * 460 * Unconditionally switch the ports back to xHCI after a system resume. 461 * It should not matter whether the EHCI or xHCI controller is 462 * resumed first. It's enough to do the switchover in xHCI because 463 * USB core won't notice anything as the hub driver doesn't start 464 * running again until after all the devices (including both EHCI and 465 * xHCI host controllers) have been resumed. 466 */ 467 468 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 469 usb_enable_intel_xhci_ports(pdev); 470 471 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 472 xhci_ssic_port_unused_quirk(hcd, false); 473 474 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 475 xhci_pme_quirk(hcd); 476 477 retval = xhci_resume(xhci, hibernated); 478 return retval; 479 } 480 #endif /* CONFIG_PM */ 481 482 /*-------------------------------------------------------------------------*/ 483 484 /* PCI driver selection metadata; PCI hotplugging uses this */ 485 static const struct pci_device_id pci_ids[] = { { 486 /* handle any USB 3.0 xHCI controller */ 487 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 488 .driver_data = (unsigned long) &xhci_pci_hc_driver, 489 }, 490 { /* end: all zeroes */ } 491 }; 492 MODULE_DEVICE_TABLE(pci, pci_ids); 493 494 /* pci driver glue; this is a "new style" PCI driver module */ 495 static struct pci_driver xhci_pci_driver = { 496 .name = (char *) hcd_name, 497 .id_table = pci_ids, 498 499 .probe = xhci_pci_probe, 500 .remove = xhci_pci_remove, 501 /* suspend and resume implemented later */ 502 503 .shutdown = usb_hcd_pci_shutdown, 504 #ifdef CONFIG_PM 505 .driver = { 506 .pm = &usb_hcd_pci_pm_ops 507 }, 508 #endif 509 }; 510 511 static int __init xhci_pci_init(void) 512 { 513 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 514 #ifdef CONFIG_PM 515 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend; 516 xhci_pci_hc_driver.pci_resume = xhci_pci_resume; 517 #endif 518 return pci_register_driver(&xhci_pci_driver); 519 } 520 module_init(xhci_pci_init); 521 522 static void __exit xhci_pci_exit(void) 523 { 524 pci_unregister_driver(&xhci_pci_driver); 525 } 526 module_exit(xhci_pci_exit); 527 528 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 529 MODULE_LICENSE("GPL"); 530