1 /* 2 * xHCI host controller driver PCI Bus Glue. 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/pci.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 27 #include "xhci.h" 28 #include "xhci-trace.h" 29 30 /* Device for a quirk */ 31 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 32 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 34 35 #define PCI_VENDOR_ID_ETRON 0x1b6f 36 #define PCI_DEVICE_ID_EJ168 0x7023 37 38 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 39 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 40 41 static const char hcd_name[] = "xhci_hcd"; 42 43 /* called after powerup, by probe or system-pm "wakeup" */ 44 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 45 { 46 /* 47 * TODO: Implement finding debug ports later. 48 * TODO: see if there are any quirks that need to be added to handle 49 * new extended capabilities. 50 */ 51 52 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 53 if (!pci_set_mwi(pdev)) 54 xhci_dbg(xhci, "MWI active\n"); 55 56 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 57 return 0; 58 } 59 60 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 61 { 62 struct pci_dev *pdev = to_pci_dev(dev); 63 64 /* Look for vendor-specific quirks */ 65 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 66 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 67 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 68 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 69 pdev->revision == 0x0) { 70 xhci->quirks |= XHCI_RESET_EP_QUIRK; 71 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 72 "QUIRK: Fresco Logic xHC needs configure" 73 " endpoint cmd after reset endpoint"); 74 } 75 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 76 pdev->revision == 0x4) { 77 xhci->quirks |= XHCI_SLOW_SUSPEND; 78 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 79 "QUIRK: Fresco Logic xHC revision %u" 80 "must be suspended extra slowly", 81 pdev->revision); 82 } 83 /* Fresco Logic confirms: all revisions of this chip do not 84 * support MSI, even though some of them claim to in their PCI 85 * capabilities. 86 */ 87 xhci->quirks |= XHCI_BROKEN_MSI; 88 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 89 "QUIRK: Fresco Logic revision %u " 90 "has broken MSI implementation", 91 pdev->revision); 92 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 93 } 94 95 if (pdev->vendor == PCI_VENDOR_ID_NEC) 96 xhci->quirks |= XHCI_NEC_HOST; 97 98 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 99 xhci->quirks |= XHCI_AMD_0x96_HOST; 100 101 /* AMD PLL quirk */ 102 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info()) 103 xhci->quirks |= XHCI_AMD_PLL_FIX; 104 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 105 xhci->quirks |= XHCI_LPM_SUPPORT; 106 xhci->quirks |= XHCI_INTEL_HOST; 107 } 108 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 109 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 110 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 111 xhci->limit_active_eps = 64; 112 xhci->quirks |= XHCI_SW_BW_CHECKING; 113 /* 114 * PPT desktop boards DH77EB and DH77DF will power back on after 115 * a few seconds of being shutdown. The fix for this is to 116 * switch the ports from xHCI to EHCI on shutdown. We can't use 117 * DMI information to find those particular boards (since each 118 * vendor will change the board name), so we have to key off all 119 * PPT chipsets. 120 */ 121 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 122 xhci->quirks |= XHCI_AVOID_BEI; 123 } 124 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 125 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI || 126 pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI)) { 127 /* Workaround for occasional spurious wakeups from S5 (or 128 * any other sleep) on Haswell machines with LPT and LPT-LP 129 * with the new Intel BIOS 130 */ 131 /* Limit the quirk to only known vendors, as this triggers 132 * yet another BIOS bug on some other machines 133 * https://bugzilla.kernel.org/show_bug.cgi?id=66171 134 */ 135 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP) 136 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 137 } 138 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 139 pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI) { 140 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 141 } 142 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 143 pdev->device == PCI_DEVICE_ID_EJ168) { 144 xhci->quirks |= XHCI_RESET_ON_RESUME; 145 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 146 xhci->quirks |= XHCI_BROKEN_STREAMS; 147 } 148 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 149 pdev->device == 0x0015) 150 xhci->quirks |= XHCI_RESET_ON_RESUME; 151 if (pdev->vendor == PCI_VENDOR_ID_VIA) 152 xhci->quirks |= XHCI_RESET_ON_RESUME; 153 154 if (xhci->quirks & XHCI_RESET_ON_RESUME) 155 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 156 "QUIRK: Resetting on resume"); 157 } 158 159 /* called during probe() after chip reset completes */ 160 static int xhci_pci_setup(struct usb_hcd *hcd) 161 { 162 struct xhci_hcd *xhci; 163 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 164 int retval; 165 166 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 167 if (retval) 168 return retval; 169 170 xhci = hcd_to_xhci(hcd); 171 if (!usb_hcd_is_primary_hcd(hcd)) 172 return 0; 173 174 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 175 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 176 177 /* Find any debug ports */ 178 retval = xhci_pci_reinit(xhci, pdev); 179 if (!retval) 180 return retval; 181 182 kfree(xhci); 183 return retval; 184 } 185 186 /* 187 * We need to register our own PCI probe function (instead of the USB core's 188 * function) in order to create a second roothub under xHCI. 189 */ 190 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 191 { 192 int retval; 193 struct xhci_hcd *xhci; 194 struct hc_driver *driver; 195 struct usb_hcd *hcd; 196 197 driver = (struct hc_driver *)id->driver_data; 198 199 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 200 pm_runtime_get_noresume(&dev->dev); 201 202 /* Register the USB 2.0 roothub. 203 * FIXME: USB core must know to register the USB 2.0 roothub first. 204 * This is sort of silly, because we could just set the HCD driver flags 205 * to say USB 2.0, but I'm not sure what the implications would be in 206 * the other parts of the HCD code. 207 */ 208 retval = usb_hcd_pci_probe(dev, id); 209 210 if (retval) 211 goto put_runtime_pm; 212 213 /* USB 2.0 roothub is stored in the PCI device now. */ 214 hcd = dev_get_drvdata(&dev->dev); 215 xhci = hcd_to_xhci(hcd); 216 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, 217 pci_name(dev), hcd); 218 if (!xhci->shared_hcd) { 219 retval = -ENOMEM; 220 goto dealloc_usb2_hcd; 221 } 222 223 /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset) 224 * is called by usb_add_hcd(). 225 */ 226 *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci; 227 228 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 229 IRQF_SHARED); 230 if (retval) 231 goto put_usb3_hcd; 232 /* Roothub already marked as USB 3.0 speed */ 233 234 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 235 HCC_MAX_PSA(xhci->hcc_params) >= 4) 236 xhci->shared_hcd->can_do_streams = 1; 237 238 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 239 pm_runtime_put_noidle(&dev->dev); 240 241 return 0; 242 243 put_usb3_hcd: 244 usb_put_hcd(xhci->shared_hcd); 245 dealloc_usb2_hcd: 246 usb_hcd_pci_remove(dev); 247 put_runtime_pm: 248 pm_runtime_put_noidle(&dev->dev); 249 return retval; 250 } 251 252 static void xhci_pci_remove(struct pci_dev *dev) 253 { 254 struct xhci_hcd *xhci; 255 256 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 257 if (xhci->shared_hcd) { 258 usb_remove_hcd(xhci->shared_hcd); 259 usb_put_hcd(xhci->shared_hcd); 260 } 261 usb_hcd_pci_remove(dev); 262 263 /* Workaround for spurious wakeups at shutdown with HSW */ 264 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 265 pci_set_power_state(dev, PCI_D3hot); 266 267 kfree(xhci); 268 } 269 270 #ifdef CONFIG_PM 271 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 272 { 273 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 274 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 275 276 /* 277 * Systems with the TI redriver that loses port status change events 278 * need to have the registers polled during D3, so avoid D3cold. 279 */ 280 if (xhci_compliance_mode_recovery_timer_quirk_check()) 281 pdev->no_d3cold = true; 282 283 return xhci_suspend(xhci); 284 } 285 286 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 287 { 288 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 289 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 290 int retval = 0; 291 292 /* The BIOS on systems with the Intel Panther Point chipset may or may 293 * not support xHCI natively. That means that during system resume, it 294 * may switch the ports back to EHCI so that users can use their 295 * keyboard to select a kernel from GRUB after resume from hibernate. 296 * 297 * The BIOS is supposed to remember whether the OS had xHCI ports 298 * enabled before resume, and switch the ports back to xHCI when the 299 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 300 * writers. 301 * 302 * Unconditionally switch the ports back to xHCI after a system resume. 303 * It should not matter whether the EHCI or xHCI controller is 304 * resumed first. It's enough to do the switchover in xHCI because 305 * USB core won't notice anything as the hub driver doesn't start 306 * running again until after all the devices (including both EHCI and 307 * xHCI host controllers) have been resumed. 308 */ 309 310 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 311 usb_enable_intel_xhci_ports(pdev); 312 313 retval = xhci_resume(xhci, hibernated); 314 return retval; 315 } 316 #endif /* CONFIG_PM */ 317 318 static const struct hc_driver xhci_pci_hc_driver = { 319 .description = hcd_name, 320 .product_desc = "xHCI Host Controller", 321 .hcd_priv_size = sizeof(struct xhci_hcd *), 322 323 /* 324 * generic hardware linkage 325 */ 326 .irq = xhci_irq, 327 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED, 328 329 /* 330 * basic lifecycle operations 331 */ 332 .reset = xhci_pci_setup, 333 .start = xhci_run, 334 #ifdef CONFIG_PM 335 .pci_suspend = xhci_pci_suspend, 336 .pci_resume = xhci_pci_resume, 337 #endif 338 .stop = xhci_stop, 339 .shutdown = xhci_shutdown, 340 341 /* 342 * managing i/o requests and associated device resources 343 */ 344 .urb_enqueue = xhci_urb_enqueue, 345 .urb_dequeue = xhci_urb_dequeue, 346 .alloc_dev = xhci_alloc_dev, 347 .free_dev = xhci_free_dev, 348 .alloc_streams = xhci_alloc_streams, 349 .free_streams = xhci_free_streams, 350 .add_endpoint = xhci_add_endpoint, 351 .drop_endpoint = xhci_drop_endpoint, 352 .endpoint_reset = xhci_endpoint_reset, 353 .check_bandwidth = xhci_check_bandwidth, 354 .reset_bandwidth = xhci_reset_bandwidth, 355 .address_device = xhci_address_device, 356 .enable_device = xhci_enable_device, 357 .update_hub_device = xhci_update_hub_device, 358 .reset_device = xhci_discover_or_reset_device, 359 360 /* 361 * scheduling support 362 */ 363 .get_frame_number = xhci_get_frame, 364 365 /* Root hub support */ 366 .hub_control = xhci_hub_control, 367 .hub_status_data = xhci_hub_status_data, 368 .bus_suspend = xhci_bus_suspend, 369 .bus_resume = xhci_bus_resume, 370 /* 371 * call back when device connected and addressed 372 */ 373 .update_device = xhci_update_device, 374 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm, 375 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout, 376 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout, 377 .find_raw_port_number = xhci_find_raw_port_number, 378 }; 379 380 /*-------------------------------------------------------------------------*/ 381 382 /* PCI driver selection metadata; PCI hotplugging uses this */ 383 static const struct pci_device_id pci_ids[] = { { 384 /* handle any USB 3.0 xHCI controller */ 385 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 386 .driver_data = (unsigned long) &xhci_pci_hc_driver, 387 }, 388 { /* end: all zeroes */ } 389 }; 390 MODULE_DEVICE_TABLE(pci, pci_ids); 391 392 /* pci driver glue; this is a "new style" PCI driver module */ 393 static struct pci_driver xhci_pci_driver = { 394 .name = (char *) hcd_name, 395 .id_table = pci_ids, 396 397 .probe = xhci_pci_probe, 398 .remove = xhci_pci_remove, 399 /* suspend and resume implemented later */ 400 401 .shutdown = usb_hcd_pci_shutdown, 402 #ifdef CONFIG_PM 403 .driver = { 404 .pm = &usb_hcd_pci_pm_ops 405 }, 406 #endif 407 }; 408 409 int __init xhci_register_pci(void) 410 { 411 return pci_register_driver(&xhci_pci_driver); 412 } 413 414 void xhci_unregister_pci(void) 415 { 416 pci_unregister_driver(&xhci_pci_driver); 417 } 418