1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 #include <linux/reset.h> 16 #include <linux/suspend.h> 17 18 #include "xhci.h" 19 #include "xhci-trace.h" 20 #include "xhci-pci.h" 21 22 #define SSIC_PORT_NUM 2 23 #define SSIC_PORT_CFG2 0x880c 24 #define SSIC_PORT_CFG2_OFFSET 0x30 25 #define PROG_DONE (1 << 30) 26 #define SSIC_PORT_UNUSED (1 << 31) 27 #define SPARSE_DISABLE_BIT 17 28 #define SPARSE_CNTL_ENABLE 0xC12C 29 30 /* Device for a quirk */ 31 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 32 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100 35 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 36 37 #define PCI_VENDOR_ID_ETRON 0x1b6f 38 #define PCI_DEVICE_ID_EJ168 0x7023 39 40 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 41 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 42 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 43 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 44 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 45 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 46 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 47 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 48 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 49 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 50 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1 53 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 54 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 55 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 56 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 57 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 58 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 59 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af 60 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13 61 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138 62 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed 63 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI 0x54ed 64 65 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639 66 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 67 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 68 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 69 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 70 71 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042 72 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 73 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242 74 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142 75 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242 76 77 static const char hcd_name[] = "xhci_hcd"; 78 79 static struct hc_driver __read_mostly xhci_pci_hc_driver; 80 81 static int xhci_pci_setup(struct usb_hcd *hcd); 82 static int xhci_pci_run(struct usb_hcd *hcd); 83 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 84 struct usb_tt *tt, gfp_t mem_flags); 85 86 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 87 .reset = xhci_pci_setup, 88 .start = xhci_pci_run, 89 .update_hub_device = xhci_pci_update_hub_device, 90 }; 91 92 static void xhci_msix_sync_irqs(struct xhci_hcd *xhci) 93 { 94 struct usb_hcd *hcd = xhci_to_hcd(xhci); 95 96 if (hcd->msix_enabled) { 97 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 98 int i; 99 100 for (i = 0; i < xhci->msix_count; i++) 101 synchronize_irq(pci_irq_vector(pdev, i)); 102 } 103 } 104 105 /* Free any IRQs and disable MSI-X */ 106 static void xhci_cleanup_msix(struct xhci_hcd *xhci) 107 { 108 struct usb_hcd *hcd = xhci_to_hcd(xhci); 109 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 110 111 if (xhci->quirks & XHCI_PLAT) 112 return; 113 114 /* return if using legacy interrupt */ 115 if (hcd->irq > 0) 116 return; 117 118 if (hcd->msix_enabled) { 119 int i; 120 121 for (i = 0; i < xhci->msix_count; i++) 122 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci)); 123 } else { 124 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci)); 125 } 126 127 pci_free_irq_vectors(pdev); 128 hcd->msix_enabled = 0; 129 } 130 131 /* 132 * Set up MSI 133 */ 134 static int xhci_setup_msi(struct xhci_hcd *xhci) 135 { 136 int ret; 137 /* 138 * TODO:Check with MSI Soc for sysdev 139 */ 140 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); 141 142 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 143 if (ret < 0) { 144 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 145 "failed to allocate MSI entry"); 146 return ret; 147 } 148 149 ret = request_irq(pdev->irq, xhci_msi_irq, 150 0, "xhci_hcd", xhci_to_hcd(xhci)); 151 if (ret) { 152 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 153 "disable MSI interrupt"); 154 pci_free_irq_vectors(pdev); 155 } 156 157 return ret; 158 } 159 160 /* 161 * Set up MSI-X 162 */ 163 static int xhci_setup_msix(struct xhci_hcd *xhci) 164 { 165 int i, ret; 166 struct usb_hcd *hcd = xhci_to_hcd(xhci); 167 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 168 169 /* 170 * calculate number of msi-x vectors supported. 171 * - HCS_MAX_INTRS: the max number of interrupts the host can handle, 172 * with max number of interrupters based on the xhci HCSPARAMS1. 173 * - num_online_cpus: maximum msi-x vectors per CPUs core. 174 * Add additional 1 vector to ensure always available interrupt. 175 */ 176 xhci->msix_count = min(num_online_cpus() + 1, 177 HCS_MAX_INTRS(xhci->hcs_params1)); 178 179 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count, 180 PCI_IRQ_MSIX); 181 if (ret < 0) { 182 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 183 "Failed to enable MSI-X"); 184 return ret; 185 } 186 187 for (i = 0; i < xhci->msix_count; i++) { 188 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0, 189 "xhci_hcd", xhci_to_hcd(xhci)); 190 if (ret) 191 goto disable_msix; 192 } 193 194 hcd->msix_enabled = 1; 195 return ret; 196 197 disable_msix: 198 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt"); 199 while (--i >= 0) 200 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci)); 201 pci_free_irq_vectors(pdev); 202 return ret; 203 } 204 205 static int xhci_try_enable_msi(struct usb_hcd *hcd) 206 { 207 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 208 struct pci_dev *pdev; 209 int ret; 210 211 /* The xhci platform device has set up IRQs through usb_add_hcd. */ 212 if (xhci->quirks & XHCI_PLAT) 213 return 0; 214 215 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); 216 /* 217 * Some Fresco Logic host controllers advertise MSI, but fail to 218 * generate interrupts. Don't even try to enable MSI. 219 */ 220 if (xhci->quirks & XHCI_BROKEN_MSI) 221 goto legacy_irq; 222 223 /* unregister the legacy interrupt */ 224 if (hcd->irq) 225 free_irq(hcd->irq, hcd); 226 hcd->irq = 0; 227 228 ret = xhci_setup_msix(xhci); 229 if (ret) 230 /* fall back to msi*/ 231 ret = xhci_setup_msi(xhci); 232 233 if (!ret) { 234 hcd->msi_enabled = 1; 235 return 0; 236 } 237 238 if (!pdev->irq) { 239 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n"); 240 return -EINVAL; 241 } 242 243 legacy_irq: 244 if (!strlen(hcd->irq_descr)) 245 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d", 246 hcd->driver->description, hcd->self.busnum); 247 248 /* fall back to legacy interrupt*/ 249 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, 250 hcd->irq_descr, hcd); 251 if (ret) { 252 xhci_err(xhci, "request interrupt %d failed\n", 253 pdev->irq); 254 return ret; 255 } 256 hcd->irq = pdev->irq; 257 return 0; 258 } 259 260 static int xhci_pci_run(struct usb_hcd *hcd) 261 { 262 int ret; 263 264 if (usb_hcd_is_primary_hcd(hcd)) { 265 ret = xhci_try_enable_msi(hcd); 266 if (ret) 267 return ret; 268 } 269 270 return xhci_run(hcd); 271 } 272 273 static void xhci_pci_stop(struct usb_hcd *hcd) 274 { 275 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 276 277 xhci_stop(hcd); 278 279 if (usb_hcd_is_primary_hcd(hcd)) 280 xhci_cleanup_msix(xhci); 281 } 282 283 /* called after powerup, by probe or system-pm "wakeup" */ 284 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 285 { 286 /* 287 * TODO: Implement finding debug ports later. 288 * TODO: see if there are any quirks that need to be added to handle 289 * new extended capabilities. 290 */ 291 292 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 293 if (!pci_set_mwi(pdev)) 294 xhci_dbg(xhci, "MWI active\n"); 295 296 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 297 return 0; 298 } 299 300 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 301 { 302 struct pci_dev *pdev = to_pci_dev(dev); 303 struct xhci_driver_data *driver_data; 304 const struct pci_device_id *id; 305 306 id = pci_match_id(to_pci_driver(pdev->dev.driver)->id_table, pdev); 307 308 if (id && id->driver_data) { 309 driver_data = (struct xhci_driver_data *)id->driver_data; 310 xhci->quirks |= driver_data->quirks; 311 } 312 313 /* Look for vendor-specific quirks */ 314 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 315 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 316 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 317 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 318 pdev->revision == 0x0) { 319 xhci->quirks |= XHCI_RESET_EP_QUIRK; 320 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 321 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated"); 322 } 323 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 324 pdev->revision == 0x4) { 325 xhci->quirks |= XHCI_SLOW_SUSPEND; 326 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 327 "QUIRK: Fresco Logic xHC revision %u" 328 "must be suspended extra slowly", 329 pdev->revision); 330 } 331 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 332 xhci->quirks |= XHCI_BROKEN_STREAMS; 333 /* Fresco Logic confirms: all revisions of this chip do not 334 * support MSI, even though some of them claim to in their PCI 335 * capabilities. 336 */ 337 xhci->quirks |= XHCI_BROKEN_MSI; 338 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 339 "QUIRK: Fresco Logic revision %u " 340 "has broken MSI implementation", 341 pdev->revision); 342 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 343 } 344 345 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 346 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 347 xhci->quirks |= XHCI_BROKEN_STREAMS; 348 349 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 350 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100) 351 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 352 353 if (pdev->vendor == PCI_VENDOR_ID_NEC) 354 xhci->quirks |= XHCI_NEC_HOST; 355 356 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 357 xhci->quirks |= XHCI_AMD_0x96_HOST; 358 359 /* AMD PLL quirk */ 360 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) 361 xhci->quirks |= XHCI_AMD_PLL_FIX; 362 363 if (pdev->vendor == PCI_VENDOR_ID_AMD && 364 (pdev->device == 0x145c || 365 pdev->device == 0x15e0 || 366 pdev->device == 0x15e1 || 367 pdev->device == 0x43bb)) 368 xhci->quirks |= XHCI_SUSPEND_DELAY; 369 370 if (pdev->vendor == PCI_VENDOR_ID_AMD && 371 (pdev->device == 0x15e0 || pdev->device == 0x15e1)) 372 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; 373 374 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) { 375 xhci->quirks |= XHCI_DISABLE_SPARSE; 376 xhci->quirks |= XHCI_RESET_ON_RESUME; 377 } 378 379 if (pdev->vendor == PCI_VENDOR_ID_AMD) 380 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 381 382 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 383 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 384 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 385 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 386 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 387 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 388 389 if (pdev->vendor == PCI_VENDOR_ID_AMD && 390 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) 391 xhci->quirks |= XHCI_BROKEN_D3COLD_S2I; 392 393 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 394 xhci->quirks |= XHCI_LPM_SUPPORT; 395 xhci->quirks |= XHCI_INTEL_HOST; 396 xhci->quirks |= XHCI_AVOID_BEI; 397 } 398 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 399 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 400 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 401 xhci->limit_active_eps = 64; 402 xhci->quirks |= XHCI_SW_BW_CHECKING; 403 /* 404 * PPT desktop boards DH77EB and DH77DF will power back on after 405 * a few seconds of being shutdown. The fix for this is to 406 * switch the ports from xHCI to EHCI on shutdown. We can't use 407 * DMI information to find those particular boards (since each 408 * vendor will change the board name), so we have to key off all 409 * PPT chipsets. 410 */ 411 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 412 } 413 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 414 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 415 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 416 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 417 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 418 } 419 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 420 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 421 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 422 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 423 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 424 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 425 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 426 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI || 427 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) { 428 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 429 } 430 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 431 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 432 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 433 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 434 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 435 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 436 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI)) 437 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 438 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 439 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 440 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 441 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 442 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 443 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) 444 xhci->quirks |= XHCI_MISSING_CAS; 445 446 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 447 (pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI || 448 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI)) 449 xhci->quirks |= XHCI_RESET_TO_DEFAULT; 450 451 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 452 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 453 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 454 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI || 455 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 456 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 457 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 458 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 459 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || 460 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI || 461 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI || 462 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI)) 463 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 464 465 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 466 pdev->device == PCI_DEVICE_ID_EJ168) { 467 xhci->quirks |= XHCI_RESET_ON_RESUME; 468 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 469 xhci->quirks |= XHCI_BROKEN_STREAMS; 470 } 471 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 472 pdev->device == 0x0014) { 473 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 474 xhci->quirks |= XHCI_ZERO_64B_REGS; 475 } 476 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 477 pdev->device == 0x0015) { 478 xhci->quirks |= XHCI_RESET_ON_RESUME; 479 xhci->quirks |= XHCI_ZERO_64B_REGS; 480 } 481 if (pdev->vendor == PCI_VENDOR_ID_VIA) 482 xhci->quirks |= XHCI_RESET_ON_RESUME; 483 484 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 485 if (pdev->vendor == PCI_VENDOR_ID_VIA && 486 pdev->device == 0x3432) 487 xhci->quirks |= XHCI_BROKEN_STREAMS; 488 489 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) { 490 xhci->quirks |= XHCI_LPM_SUPPORT; 491 xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS; 492 } 493 494 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 495 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) { 496 /* 497 * try to tame the ASMedia 1042 controller which reports 0.96 498 * but appears to behave more like 1.0 499 */ 500 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 501 xhci->quirks |= XHCI_BROKEN_STREAMS; 502 } 503 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 504 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) { 505 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 506 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 507 } 508 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 509 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI || 510 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI || 511 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI)) 512 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 513 514 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 515 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 516 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 517 518 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 519 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 520 521 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 522 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 523 pdev->device == 0x9026) 524 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 525 526 if (pdev->vendor == PCI_VENDOR_ID_AMD && 527 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 || 528 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4)) 529 xhci->quirks |= XHCI_NO_SOFT_RETRY; 530 531 /* xHC spec requires PCI devices to support D3hot and D3cold */ 532 if (xhci->hci_version >= 0x120) 533 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 534 535 if (xhci->quirks & XHCI_RESET_ON_RESUME) 536 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 537 "QUIRK: Resetting on resume"); 538 } 539 540 #ifdef CONFIG_ACPI 541 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 542 { 543 static const guid_t intel_dsm_guid = 544 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 545 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 546 union acpi_object *obj; 547 548 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 549 NULL); 550 ACPI_FREE(obj); 551 } 552 553 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) 554 { 555 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 556 struct xhci_hub *rhub = &xhci->usb3_rhub; 557 int ret; 558 int i; 559 560 /* This is not the usb3 roothub we are looking for */ 561 if (hcd != rhub->hcd) 562 return; 563 564 if (hdev->maxchild > rhub->num_ports) { 565 dev_err(&hdev->dev, "USB3 roothub port number mismatch\n"); 566 return; 567 } 568 569 for (i = 0; i < hdev->maxchild; i++) { 570 ret = usb_acpi_port_lpm_incapable(hdev, i); 571 572 dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret); 573 574 if (ret >= 0) { 575 rhub->ports[i]->lpm_incapable = ret; 576 continue; 577 } 578 } 579 } 580 581 #else 582 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 583 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { } 584 #endif /* CONFIG_ACPI */ 585 586 /* called during probe() after chip reset completes */ 587 static int xhci_pci_setup(struct usb_hcd *hcd) 588 { 589 struct xhci_hcd *xhci; 590 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 591 int retval; 592 593 xhci = hcd_to_xhci(hcd); 594 if (!xhci->sbrn) 595 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 596 597 /* imod_interval is the interrupt moderation value in nanoseconds. */ 598 xhci->imod_interval = 40000; 599 600 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 601 if (retval) 602 return retval; 603 604 if (!usb_hcd_is_primary_hcd(hcd)) 605 return 0; 606 607 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 608 xhci_pme_acpi_rtd3_enable(pdev); 609 610 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 611 612 /* Find any debug ports */ 613 return xhci_pci_reinit(xhci, pdev); 614 } 615 616 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 617 struct usb_tt *tt, gfp_t mem_flags) 618 { 619 /* Check if acpi claims some USB3 roothub ports are lpm incapable */ 620 if (!hdev->parent) 621 xhci_find_lpm_incapable_ports(hcd, hdev); 622 623 return xhci_update_hub_device(hcd, hdev, tt, mem_flags); 624 } 625 626 /* 627 * We need to register our own PCI probe function (instead of the USB core's 628 * function) in order to create a second roothub under xHCI. 629 */ 630 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 631 { 632 int retval; 633 struct xhci_hcd *xhci; 634 struct usb_hcd *hcd; 635 struct xhci_driver_data *driver_data; 636 struct reset_control *reset; 637 638 driver_data = (struct xhci_driver_data *)id->driver_data; 639 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) { 640 retval = renesas_xhci_check_request_fw(dev, id); 641 if (retval) 642 return retval; 643 } 644 645 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 646 if (IS_ERR(reset)) 647 return PTR_ERR(reset); 648 reset_control_reset(reset); 649 650 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 651 pm_runtime_get_noresume(&dev->dev); 652 653 /* Register the USB 2.0 roothub. 654 * FIXME: USB core must know to register the USB 2.0 roothub first. 655 * This is sort of silly, because we could just set the HCD driver flags 656 * to say USB 2.0, but I'm not sure what the implications would be in 657 * the other parts of the HCD code. 658 */ 659 retval = usb_hcd_pci_probe(dev, &xhci_pci_hc_driver); 660 661 if (retval) 662 goto put_runtime_pm; 663 664 /* USB 2.0 roothub is stored in the PCI device now. */ 665 hcd = dev_get_drvdata(&dev->dev); 666 xhci = hcd_to_xhci(hcd); 667 xhci->reset = reset; 668 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev, 669 pci_name(dev), hcd); 670 if (!xhci->shared_hcd) { 671 retval = -ENOMEM; 672 goto dealloc_usb2_hcd; 673 } 674 675 retval = xhci_ext_cap_init(xhci); 676 if (retval) 677 goto put_usb3_hcd; 678 679 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 680 IRQF_SHARED); 681 if (retval) 682 goto put_usb3_hcd; 683 /* Roothub already marked as USB 3.0 speed */ 684 685 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 686 HCC_MAX_PSA(xhci->hcc_params) >= 4) 687 xhci->shared_hcd->can_do_streams = 1; 688 689 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 690 pm_runtime_put_noidle(&dev->dev); 691 692 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 693 pm_runtime_allow(&dev->dev); 694 695 dma_set_max_seg_size(&dev->dev, UINT_MAX); 696 697 return 0; 698 699 put_usb3_hcd: 700 usb_put_hcd(xhci->shared_hcd); 701 dealloc_usb2_hcd: 702 usb_hcd_pci_remove(dev); 703 put_runtime_pm: 704 pm_runtime_put_noidle(&dev->dev); 705 return retval; 706 } 707 708 static void xhci_pci_remove(struct pci_dev *dev) 709 { 710 struct xhci_hcd *xhci; 711 712 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 713 714 xhci->xhc_state |= XHCI_STATE_REMOVING; 715 716 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 717 pm_runtime_forbid(&dev->dev); 718 719 if (xhci->shared_hcd) { 720 usb_remove_hcd(xhci->shared_hcd); 721 usb_put_hcd(xhci->shared_hcd); 722 xhci->shared_hcd = NULL; 723 } 724 725 /* Workaround for spurious wakeups at shutdown with HSW */ 726 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 727 pci_set_power_state(dev, PCI_D3hot); 728 729 usb_hcd_pci_remove(dev); 730 } 731 732 /* 733 * In some Intel xHCI controllers, in order to get D3 working, 734 * through a vendor specific SSIC CONFIG register at offset 0x883c, 735 * SSIC PORT need to be marked as "unused" before putting xHCI 736 * into D3. After D3 exit, the SSIC port need to be marked as "used". 737 * Without this change, xHCI might not enter D3 state. 738 */ 739 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 740 { 741 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 742 u32 val; 743 void __iomem *reg; 744 int i; 745 746 for (i = 0; i < SSIC_PORT_NUM; i++) { 747 reg = (void __iomem *) xhci->cap_regs + 748 SSIC_PORT_CFG2 + 749 i * SSIC_PORT_CFG2_OFFSET; 750 751 /* Notify SSIC that SSIC profile programming is not done. */ 752 val = readl(reg) & ~PROG_DONE; 753 writel(val, reg); 754 755 /* Mark SSIC port as unused(suspend) or used(resume) */ 756 val = readl(reg); 757 if (suspend) 758 val |= SSIC_PORT_UNUSED; 759 else 760 val &= ~SSIC_PORT_UNUSED; 761 writel(val, reg); 762 763 /* Notify SSIC that SSIC profile programming is done */ 764 val = readl(reg) | PROG_DONE; 765 writel(val, reg); 766 readl(reg); 767 } 768 } 769 770 /* 771 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 772 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 773 */ 774 static void xhci_pme_quirk(struct usb_hcd *hcd) 775 { 776 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 777 void __iomem *reg; 778 u32 val; 779 780 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 781 val = readl(reg); 782 writel(val | BIT(28), reg); 783 readl(reg); 784 } 785 786 static void xhci_sparse_control_quirk(struct usb_hcd *hcd) 787 { 788 u32 reg; 789 790 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE); 791 reg &= ~BIT(SPARSE_DISABLE_BIT); 792 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE); 793 } 794 795 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 796 { 797 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 798 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 799 int ret; 800 801 /* 802 * Systems with the TI redriver that loses port status change events 803 * need to have the registers polled during D3, so avoid D3cold. 804 */ 805 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 806 pci_d3cold_disable(pdev); 807 808 #ifdef CONFIG_SUSPEND 809 /* d3cold is broken, but only when s2idle is used */ 810 if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE && 811 xhci->quirks & (XHCI_BROKEN_D3COLD_S2I)) 812 pci_d3cold_disable(pdev); 813 #endif 814 815 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 816 xhci_pme_quirk(hcd); 817 818 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 819 xhci_ssic_port_unused_quirk(hcd, true); 820 821 if (xhci->quirks & XHCI_DISABLE_SPARSE) 822 xhci_sparse_control_quirk(hcd); 823 824 ret = xhci_suspend(xhci, do_wakeup); 825 826 /* synchronize irq when using MSI-X */ 827 xhci_msix_sync_irqs(xhci); 828 829 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 830 xhci_ssic_port_unused_quirk(hcd, false); 831 832 return ret; 833 } 834 835 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 836 { 837 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 838 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 839 int retval = 0; 840 841 reset_control_reset(xhci->reset); 842 843 /* The BIOS on systems with the Intel Panther Point chipset may or may 844 * not support xHCI natively. That means that during system resume, it 845 * may switch the ports back to EHCI so that users can use their 846 * keyboard to select a kernel from GRUB after resume from hibernate. 847 * 848 * The BIOS is supposed to remember whether the OS had xHCI ports 849 * enabled before resume, and switch the ports back to xHCI when the 850 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 851 * writers. 852 * 853 * Unconditionally switch the ports back to xHCI after a system resume. 854 * It should not matter whether the EHCI or xHCI controller is 855 * resumed first. It's enough to do the switchover in xHCI because 856 * USB core won't notice anything as the hub driver doesn't start 857 * running again until after all the devices (including both EHCI and 858 * xHCI host controllers) have been resumed. 859 */ 860 861 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 862 usb_enable_intel_xhci_ports(pdev); 863 864 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 865 xhci_ssic_port_unused_quirk(hcd, false); 866 867 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 868 xhci_pme_quirk(hcd); 869 870 retval = xhci_resume(xhci, hibernated); 871 return retval; 872 } 873 874 static int xhci_pci_poweroff_late(struct usb_hcd *hcd, bool do_wakeup) 875 { 876 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 877 struct xhci_port *port; 878 struct usb_device *udev; 879 unsigned int slot_id; 880 u32 portsc; 881 int i; 882 883 /* 884 * Systems with XHCI_RESET_TO_DEFAULT quirk have boot firmware that 885 * cause significant boot delay if usb ports are in suspended U3 state 886 * during boot. Some USB devices survive in U3 state over S4 hibernate 887 * 888 * Disable ports that are in U3 if remote wake is not enabled for either 889 * host controller or connected device 890 */ 891 892 if (!(xhci->quirks & XHCI_RESET_TO_DEFAULT)) 893 return 0; 894 895 for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) { 896 port = &xhci->hw_ports[i]; 897 portsc = readl(port->addr); 898 899 if ((portsc & PORT_PLS_MASK) != XDEV_U3) 900 continue; 901 902 slot_id = xhci_find_slot_id_by_port(port->rhub->hcd, xhci, 903 port->hcd_portnum + 1); 904 if (!slot_id || !xhci->devs[slot_id]) { 905 xhci_err(xhci, "No dev for slot_id %d for port %d-%d in U3\n", 906 slot_id, port->rhub->hcd->self.busnum, port->hcd_portnum + 1); 907 continue; 908 } 909 910 udev = xhci->devs[slot_id]->udev; 911 912 /* if wakeup is enabled then don't disable the port */ 913 if (udev->do_remote_wakeup && do_wakeup) 914 continue; 915 916 xhci_dbg(xhci, "port %d-%d in U3 without wakeup, disable it\n", 917 port->rhub->hcd->self.busnum, port->hcd_portnum + 1); 918 portsc = xhci_port_state_to_neutral(portsc); 919 writel(portsc | PORT_PE, port->addr); 920 } 921 922 return 0; 923 } 924 925 static void xhci_pci_shutdown(struct usb_hcd *hcd) 926 { 927 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 928 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 929 930 xhci_shutdown(hcd); 931 xhci_cleanup_msix(xhci); 932 933 /* Yet another workaround for spurious wakeups at shutdown with HSW */ 934 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 935 pci_set_power_state(pdev, PCI_D3hot); 936 } 937 938 /*-------------------------------------------------------------------------*/ 939 940 static const struct xhci_driver_data reneses_data = { 941 .quirks = XHCI_RENESAS_FW_QUIRK, 942 .firmware = "renesas_usb_fw.mem", 943 }; 944 945 /* PCI driver selection metadata; PCI hotplugging uses this */ 946 static const struct pci_device_id pci_ids[] = { 947 { PCI_DEVICE(0x1912, 0x0014), 948 .driver_data = (unsigned long)&reneses_data, 949 }, 950 { PCI_DEVICE(0x1912, 0x0015), 951 .driver_data = (unsigned long)&reneses_data, 952 }, 953 /* handle any USB 3.0 xHCI controller */ 954 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 955 }, 956 { /* end: all zeroes */ } 957 }; 958 MODULE_DEVICE_TABLE(pci, pci_ids); 959 960 /* 961 * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't 962 * load firmware, so don't encumber the xhci-pci driver with it. 963 */ 964 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS) 965 MODULE_FIRMWARE("renesas_usb_fw.mem"); 966 #endif 967 968 /* pci driver glue; this is a "new style" PCI driver module */ 969 static struct pci_driver xhci_pci_driver = { 970 .name = hcd_name, 971 .id_table = pci_ids, 972 973 .probe = xhci_pci_probe, 974 .remove = xhci_pci_remove, 975 /* suspend and resume implemented later */ 976 977 .shutdown = usb_hcd_pci_shutdown, 978 .driver = { 979 .pm = pm_ptr(&usb_hcd_pci_pm_ops), 980 }, 981 }; 982 983 static int __init xhci_pci_init(void) 984 { 985 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 986 xhci_pci_hc_driver.pci_suspend = pm_ptr(xhci_pci_suspend); 987 xhci_pci_hc_driver.pci_resume = pm_ptr(xhci_pci_resume); 988 xhci_pci_hc_driver.pci_poweroff_late = pm_ptr(xhci_pci_poweroff_late); 989 xhci_pci_hc_driver.shutdown = pm_ptr(xhci_pci_shutdown); 990 xhci_pci_hc_driver.stop = xhci_pci_stop; 991 return pci_register_driver(&xhci_pci_driver); 992 } 993 module_init(xhci_pci_init); 994 995 static void __exit xhci_pci_exit(void) 996 { 997 pci_unregister_driver(&xhci_pci_driver); 998 } 999 module_exit(xhci_pci_exit); 1000 1001 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 1002 MODULE_LICENSE("GPL"); 1003