1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 16 #include "xhci.h" 17 #include "xhci-trace.h" 18 19 #define SSIC_PORT_NUM 2 20 #define SSIC_PORT_CFG2 0x880c 21 #define SSIC_PORT_CFG2_OFFSET 0x30 22 #define PROG_DONE (1 << 30) 23 #define SSIC_PORT_UNUSED (1 << 31) 24 25 /* Device for a quirk */ 26 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 27 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 28 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 29 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 30 31 #define PCI_VENDOR_ID_ETRON 0x1b6f 32 #define PCI_DEVICE_ID_EJ168 0x7023 33 34 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 35 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 36 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 37 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 38 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 39 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 40 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 41 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 42 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 43 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 44 45 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 46 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 47 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 48 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 49 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 50 51 static const char hcd_name[] = "xhci_hcd"; 52 53 static struct hc_driver __read_mostly xhci_pci_hc_driver; 54 55 static int xhci_pci_setup(struct usb_hcd *hcd); 56 57 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 58 .reset = xhci_pci_setup, 59 }; 60 61 /* called after powerup, by probe or system-pm "wakeup" */ 62 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 63 { 64 /* 65 * TODO: Implement finding debug ports later. 66 * TODO: see if there are any quirks that need to be added to handle 67 * new extended capabilities. 68 */ 69 70 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 71 if (!pci_set_mwi(pdev)) 72 xhci_dbg(xhci, "MWI active\n"); 73 74 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 75 return 0; 76 } 77 78 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 79 { 80 struct pci_dev *pdev = to_pci_dev(dev); 81 82 /* Look for vendor-specific quirks */ 83 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 84 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 85 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 86 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 87 pdev->revision == 0x0) { 88 xhci->quirks |= XHCI_RESET_EP_QUIRK; 89 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 90 "QUIRK: Fresco Logic xHC needs configure" 91 " endpoint cmd after reset endpoint"); 92 } 93 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 94 pdev->revision == 0x4) { 95 xhci->quirks |= XHCI_SLOW_SUSPEND; 96 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 97 "QUIRK: Fresco Logic xHC revision %u" 98 "must be suspended extra slowly", 99 pdev->revision); 100 } 101 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 102 xhci->quirks |= XHCI_BROKEN_STREAMS; 103 /* Fresco Logic confirms: all revisions of this chip do not 104 * support MSI, even though some of them claim to in their PCI 105 * capabilities. 106 */ 107 xhci->quirks |= XHCI_BROKEN_MSI; 108 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 109 "QUIRK: Fresco Logic revision %u " 110 "has broken MSI implementation", 111 pdev->revision); 112 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 113 } 114 115 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 116 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 117 xhci->quirks |= XHCI_BROKEN_STREAMS; 118 119 if (pdev->vendor == PCI_VENDOR_ID_NEC) 120 xhci->quirks |= XHCI_NEC_HOST; 121 122 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 123 xhci->quirks |= XHCI_AMD_0x96_HOST; 124 125 /* AMD PLL quirk */ 126 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info()) 127 xhci->quirks |= XHCI_AMD_PLL_FIX; 128 129 if (pdev->vendor == PCI_VENDOR_ID_AMD && 130 (pdev->device == 0x15e0 || 131 pdev->device == 0x15e1 || 132 pdev->device == 0x43bb)) 133 xhci->quirks |= XHCI_SUSPEND_DELAY; 134 135 if (pdev->vendor == PCI_VENDOR_ID_AMD) 136 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 137 138 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 139 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 140 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 141 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 142 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 143 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 144 145 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 146 xhci->quirks |= XHCI_LPM_SUPPORT; 147 xhci->quirks |= XHCI_INTEL_HOST; 148 xhci->quirks |= XHCI_AVOID_BEI; 149 } 150 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 151 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 152 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 153 xhci->limit_active_eps = 64; 154 xhci->quirks |= XHCI_SW_BW_CHECKING; 155 /* 156 * PPT desktop boards DH77EB and DH77DF will power back on after 157 * a few seconds of being shutdown. The fix for this is to 158 * switch the ports from xHCI to EHCI on shutdown. We can't use 159 * DMI information to find those particular boards (since each 160 * vendor will change the board name), so we have to key off all 161 * PPT chipsets. 162 */ 163 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 164 } 165 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 166 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 167 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 168 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 169 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 170 } 171 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 172 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 173 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 174 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 175 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 176 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 177 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 178 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) { 179 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 180 } 181 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 182 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) { 183 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 184 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 185 } 186 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 187 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 188 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 189 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 190 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 191 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) 192 xhci->quirks |= XHCI_MISSING_CAS; 193 194 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 195 pdev->device == PCI_DEVICE_ID_EJ168) { 196 xhci->quirks |= XHCI_RESET_ON_RESUME; 197 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 198 xhci->quirks |= XHCI_BROKEN_STREAMS; 199 } 200 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 201 pdev->device == 0x0014) { 202 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 203 xhci->quirks |= XHCI_ZERO_64B_REGS; 204 } 205 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 206 pdev->device == 0x0015) { 207 xhci->quirks |= XHCI_RESET_ON_RESUME; 208 xhci->quirks |= XHCI_ZERO_64B_REGS; 209 } 210 if (pdev->vendor == PCI_VENDOR_ID_VIA) 211 xhci->quirks |= XHCI_RESET_ON_RESUME; 212 213 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 214 if (pdev->vendor == PCI_VENDOR_ID_VIA && 215 pdev->device == 0x3432) 216 xhci->quirks |= XHCI_BROKEN_STREAMS; 217 218 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 219 pdev->device == 0x1042) 220 xhci->quirks |= XHCI_BROKEN_STREAMS; 221 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 222 pdev->device == 0x1142) 223 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 224 225 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 226 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 227 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 228 229 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 230 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 231 232 if (xhci->quirks & XHCI_RESET_ON_RESUME) 233 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 234 "QUIRK: Resetting on resume"); 235 } 236 237 #ifdef CONFIG_ACPI 238 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 239 { 240 static const guid_t intel_dsm_guid = 241 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 242 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 243 union acpi_object *obj; 244 245 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 246 NULL); 247 ACPI_FREE(obj); 248 } 249 #else 250 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 251 #endif /* CONFIG_ACPI */ 252 253 /* called during probe() after chip reset completes */ 254 static int xhci_pci_setup(struct usb_hcd *hcd) 255 { 256 struct xhci_hcd *xhci; 257 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 258 int retval; 259 260 xhci = hcd_to_xhci(hcd); 261 if (!xhci->sbrn) 262 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 263 264 /* imod_interval is the interrupt moderation value in nanoseconds. */ 265 xhci->imod_interval = 40000; 266 267 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 268 if (retval) 269 return retval; 270 271 if (!usb_hcd_is_primary_hcd(hcd)) 272 return 0; 273 274 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 275 276 /* Find any debug ports */ 277 return xhci_pci_reinit(xhci, pdev); 278 } 279 280 /* 281 * We need to register our own PCI probe function (instead of the USB core's 282 * function) in order to create a second roothub under xHCI. 283 */ 284 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 285 { 286 int retval; 287 struct xhci_hcd *xhci; 288 struct hc_driver *driver; 289 struct usb_hcd *hcd; 290 291 driver = (struct hc_driver *)id->driver_data; 292 293 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 294 pm_runtime_get_noresume(&dev->dev); 295 296 /* Register the USB 2.0 roothub. 297 * FIXME: USB core must know to register the USB 2.0 roothub first. 298 * This is sort of silly, because we could just set the HCD driver flags 299 * to say USB 2.0, but I'm not sure what the implications would be in 300 * the other parts of the HCD code. 301 */ 302 retval = usb_hcd_pci_probe(dev, id); 303 304 if (retval) 305 goto put_runtime_pm; 306 307 /* USB 2.0 roothub is stored in the PCI device now. */ 308 hcd = dev_get_drvdata(&dev->dev); 309 xhci = hcd_to_xhci(hcd); 310 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, 311 pci_name(dev), hcd); 312 if (!xhci->shared_hcd) { 313 retval = -ENOMEM; 314 goto dealloc_usb2_hcd; 315 } 316 317 retval = xhci_ext_cap_init(xhci); 318 if (retval) 319 goto put_usb3_hcd; 320 321 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 322 IRQF_SHARED); 323 if (retval) 324 goto put_usb3_hcd; 325 /* Roothub already marked as USB 3.0 speed */ 326 327 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 328 HCC_MAX_PSA(xhci->hcc_params) >= 4) 329 xhci->shared_hcd->can_do_streams = 1; 330 331 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 332 xhci_pme_acpi_rtd3_enable(dev); 333 334 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 335 pm_runtime_put_noidle(&dev->dev); 336 337 return 0; 338 339 put_usb3_hcd: 340 usb_put_hcd(xhci->shared_hcd); 341 dealloc_usb2_hcd: 342 usb_hcd_pci_remove(dev); 343 put_runtime_pm: 344 pm_runtime_put_noidle(&dev->dev); 345 return retval; 346 } 347 348 static void xhci_pci_remove(struct pci_dev *dev) 349 { 350 struct xhci_hcd *xhci; 351 352 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 353 xhci->xhc_state |= XHCI_STATE_REMOVING; 354 if (xhci->shared_hcd) { 355 usb_remove_hcd(xhci->shared_hcd); 356 usb_put_hcd(xhci->shared_hcd); 357 } 358 359 /* Workaround for spurious wakeups at shutdown with HSW */ 360 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 361 pci_set_power_state(dev, PCI_D3hot); 362 363 usb_hcd_pci_remove(dev); 364 } 365 366 #ifdef CONFIG_PM 367 /* 368 * In some Intel xHCI controllers, in order to get D3 working, 369 * through a vendor specific SSIC CONFIG register at offset 0x883c, 370 * SSIC PORT need to be marked as "unused" before putting xHCI 371 * into D3. After D3 exit, the SSIC port need to be marked as "used". 372 * Without this change, xHCI might not enter D3 state. 373 */ 374 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 375 { 376 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 377 u32 val; 378 void __iomem *reg; 379 int i; 380 381 for (i = 0; i < SSIC_PORT_NUM; i++) { 382 reg = (void __iomem *) xhci->cap_regs + 383 SSIC_PORT_CFG2 + 384 i * SSIC_PORT_CFG2_OFFSET; 385 386 /* Notify SSIC that SSIC profile programming is not done. */ 387 val = readl(reg) & ~PROG_DONE; 388 writel(val, reg); 389 390 /* Mark SSIC port as unused(suspend) or used(resume) */ 391 val = readl(reg); 392 if (suspend) 393 val |= SSIC_PORT_UNUSED; 394 else 395 val &= ~SSIC_PORT_UNUSED; 396 writel(val, reg); 397 398 /* Notify SSIC that SSIC profile programming is done */ 399 val = readl(reg) | PROG_DONE; 400 writel(val, reg); 401 readl(reg); 402 } 403 } 404 405 /* 406 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 407 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 408 */ 409 static void xhci_pme_quirk(struct usb_hcd *hcd) 410 { 411 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 412 void __iomem *reg; 413 u32 val; 414 415 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 416 val = readl(reg); 417 writel(val | BIT(28), reg); 418 readl(reg); 419 } 420 421 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 422 { 423 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 424 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 425 int ret; 426 427 /* 428 * Systems with the TI redriver that loses port status change events 429 * need to have the registers polled during D3, so avoid D3cold. 430 */ 431 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 432 pci_d3cold_disable(pdev); 433 434 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 435 xhci_pme_quirk(hcd); 436 437 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 438 xhci_ssic_port_unused_quirk(hcd, true); 439 440 ret = xhci_suspend(xhci, do_wakeup); 441 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 442 xhci_ssic_port_unused_quirk(hcd, false); 443 444 return ret; 445 } 446 447 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 448 { 449 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 450 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 451 int retval = 0; 452 453 /* The BIOS on systems with the Intel Panther Point chipset may or may 454 * not support xHCI natively. That means that during system resume, it 455 * may switch the ports back to EHCI so that users can use their 456 * keyboard to select a kernel from GRUB after resume from hibernate. 457 * 458 * The BIOS is supposed to remember whether the OS had xHCI ports 459 * enabled before resume, and switch the ports back to xHCI when the 460 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 461 * writers. 462 * 463 * Unconditionally switch the ports back to xHCI after a system resume. 464 * It should not matter whether the EHCI or xHCI controller is 465 * resumed first. It's enough to do the switchover in xHCI because 466 * USB core won't notice anything as the hub driver doesn't start 467 * running again until after all the devices (including both EHCI and 468 * xHCI host controllers) have been resumed. 469 */ 470 471 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 472 usb_enable_intel_xhci_ports(pdev); 473 474 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 475 xhci_ssic_port_unused_quirk(hcd, false); 476 477 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 478 xhci_pme_quirk(hcd); 479 480 retval = xhci_resume(xhci, hibernated); 481 return retval; 482 } 483 #endif /* CONFIG_PM */ 484 485 /*-------------------------------------------------------------------------*/ 486 487 /* PCI driver selection metadata; PCI hotplugging uses this */ 488 static const struct pci_device_id pci_ids[] = { { 489 /* handle any USB 3.0 xHCI controller */ 490 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 491 .driver_data = (unsigned long) &xhci_pci_hc_driver, 492 }, 493 { /* end: all zeroes */ } 494 }; 495 MODULE_DEVICE_TABLE(pci, pci_ids); 496 497 /* pci driver glue; this is a "new style" PCI driver module */ 498 static struct pci_driver xhci_pci_driver = { 499 .name = (char *) hcd_name, 500 .id_table = pci_ids, 501 502 .probe = xhci_pci_probe, 503 .remove = xhci_pci_remove, 504 /* suspend and resume implemented later */ 505 506 .shutdown = usb_hcd_pci_shutdown, 507 #ifdef CONFIG_PM 508 .driver = { 509 .pm = &usb_hcd_pci_pm_ops 510 }, 511 #endif 512 }; 513 514 static int __init xhci_pci_init(void) 515 { 516 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 517 #ifdef CONFIG_PM 518 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend; 519 xhci_pci_hc_driver.pci_resume = xhci_pci_resume; 520 #endif 521 return pci_register_driver(&xhci_pci_driver); 522 } 523 module_init(xhci_pci_init); 524 525 static void __exit xhci_pci_exit(void) 526 { 527 pci_unregister_driver(&xhci_pci_driver); 528 } 529 module_exit(xhci_pci_exit); 530 531 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 532 MODULE_LICENSE("GPL"); 533