1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 #include <linux/reset.h> 16 17 #include "xhci.h" 18 #include "xhci-trace.h" 19 #include "xhci-pci.h" 20 21 #define SSIC_PORT_NUM 2 22 #define SSIC_PORT_CFG2 0x880c 23 #define SSIC_PORT_CFG2_OFFSET 0x30 24 #define PROG_DONE (1 << 30) 25 #define SSIC_PORT_UNUSED (1 << 31) 26 #define SPARSE_DISABLE_BIT 17 27 #define SPARSE_CNTL_ENABLE 0xC12C 28 29 /* Device for a quirk */ 30 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 31 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 32 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100 34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 35 36 #define PCI_VENDOR_ID_ETRON 0x1b6f 37 #define PCI_DEVICE_ID_EJ168 0x7023 38 39 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 40 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 41 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 42 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 43 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 44 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 45 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 46 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 47 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 48 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 49 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 50 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1 52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 53 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 54 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 55 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 56 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 57 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 58 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af 59 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13 60 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138 61 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed 62 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI 0x54ed 63 64 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639 65 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 66 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 67 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 68 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 69 70 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042 71 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 72 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242 73 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142 74 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242 75 76 static const char hcd_name[] = "xhci_hcd"; 77 78 static struct hc_driver __read_mostly xhci_pci_hc_driver; 79 80 static int xhci_pci_setup(struct usb_hcd *hcd); 81 82 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 83 .reset = xhci_pci_setup, 84 }; 85 86 /* called after powerup, by probe or system-pm "wakeup" */ 87 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 88 { 89 /* 90 * TODO: Implement finding debug ports later. 91 * TODO: see if there are any quirks that need to be added to handle 92 * new extended capabilities. 93 */ 94 95 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 96 if (!pci_set_mwi(pdev)) 97 xhci_dbg(xhci, "MWI active\n"); 98 99 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 100 return 0; 101 } 102 103 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 104 { 105 struct pci_dev *pdev = to_pci_dev(dev); 106 struct xhci_driver_data *driver_data; 107 const struct pci_device_id *id; 108 109 id = pci_match_id(to_pci_driver(pdev->dev.driver)->id_table, pdev); 110 111 if (id && id->driver_data) { 112 driver_data = (struct xhci_driver_data *)id->driver_data; 113 xhci->quirks |= driver_data->quirks; 114 } 115 116 /* Look for vendor-specific quirks */ 117 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 118 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 119 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 120 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 121 pdev->revision == 0x0) { 122 xhci->quirks |= XHCI_RESET_EP_QUIRK; 123 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 124 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated"); 125 } 126 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 127 pdev->revision == 0x4) { 128 xhci->quirks |= XHCI_SLOW_SUSPEND; 129 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 130 "QUIRK: Fresco Logic xHC revision %u" 131 "must be suspended extra slowly", 132 pdev->revision); 133 } 134 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 135 xhci->quirks |= XHCI_BROKEN_STREAMS; 136 /* Fresco Logic confirms: all revisions of this chip do not 137 * support MSI, even though some of them claim to in their PCI 138 * capabilities. 139 */ 140 xhci->quirks |= XHCI_BROKEN_MSI; 141 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 142 "QUIRK: Fresco Logic revision %u " 143 "has broken MSI implementation", 144 pdev->revision); 145 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 146 } 147 148 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 149 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 150 xhci->quirks |= XHCI_BROKEN_STREAMS; 151 152 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 153 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100) 154 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 155 156 if (pdev->vendor == PCI_VENDOR_ID_NEC) 157 xhci->quirks |= XHCI_NEC_HOST; 158 159 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 160 xhci->quirks |= XHCI_AMD_0x96_HOST; 161 162 /* AMD PLL quirk */ 163 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) 164 xhci->quirks |= XHCI_AMD_PLL_FIX; 165 166 if (pdev->vendor == PCI_VENDOR_ID_AMD && 167 (pdev->device == 0x145c || 168 pdev->device == 0x15e0 || 169 pdev->device == 0x15e1 || 170 pdev->device == 0x43bb)) 171 xhci->quirks |= XHCI_SUSPEND_DELAY; 172 173 if (pdev->vendor == PCI_VENDOR_ID_AMD && 174 (pdev->device == 0x15e0 || pdev->device == 0x15e1)) 175 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; 176 177 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) { 178 xhci->quirks |= XHCI_DISABLE_SPARSE; 179 xhci->quirks |= XHCI_RESET_ON_RESUME; 180 } 181 182 if (pdev->vendor == PCI_VENDOR_ID_AMD) 183 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 184 185 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 186 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 187 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 188 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 189 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 190 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 191 192 if (pdev->vendor == PCI_VENDOR_ID_AMD && 193 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) 194 xhci->quirks |= XHCI_BROKEN_D3COLD; 195 196 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 197 xhci->quirks |= XHCI_LPM_SUPPORT; 198 xhci->quirks |= XHCI_INTEL_HOST; 199 xhci->quirks |= XHCI_AVOID_BEI; 200 } 201 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 202 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 203 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 204 xhci->limit_active_eps = 64; 205 xhci->quirks |= XHCI_SW_BW_CHECKING; 206 /* 207 * PPT desktop boards DH77EB and DH77DF will power back on after 208 * a few seconds of being shutdown. The fix for this is to 209 * switch the ports from xHCI to EHCI on shutdown. We can't use 210 * DMI information to find those particular boards (since each 211 * vendor will change the board name), so we have to key off all 212 * PPT chipsets. 213 */ 214 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 215 } 216 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 217 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 218 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 219 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 220 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 221 } 222 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 223 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 224 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 225 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 226 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 227 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 228 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 229 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI || 230 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) { 231 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 232 } 233 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 234 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 235 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 236 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 237 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 238 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 239 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI)) 240 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 241 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 242 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 243 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 244 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 245 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 246 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) 247 xhci->quirks |= XHCI_MISSING_CAS; 248 249 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 250 (pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI || 251 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI)) 252 xhci->quirks |= XHCI_RESET_TO_DEFAULT; 253 254 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 255 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 256 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 257 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI || 258 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 259 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 260 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 261 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 262 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || 263 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI || 264 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI || 265 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI)) 266 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 267 268 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 269 pdev->device == PCI_DEVICE_ID_EJ168) { 270 xhci->quirks |= XHCI_RESET_ON_RESUME; 271 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 272 xhci->quirks |= XHCI_BROKEN_STREAMS; 273 } 274 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 275 pdev->device == 0x0014) { 276 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 277 xhci->quirks |= XHCI_ZERO_64B_REGS; 278 } 279 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 280 pdev->device == 0x0015) { 281 xhci->quirks |= XHCI_RESET_ON_RESUME; 282 xhci->quirks |= XHCI_ZERO_64B_REGS; 283 } 284 if (pdev->vendor == PCI_VENDOR_ID_VIA) 285 xhci->quirks |= XHCI_RESET_ON_RESUME; 286 287 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 288 if (pdev->vendor == PCI_VENDOR_ID_VIA && 289 pdev->device == 0x3432) 290 xhci->quirks |= XHCI_BROKEN_STREAMS; 291 292 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) { 293 xhci->quirks |= XHCI_LPM_SUPPORT; 294 xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS; 295 } 296 297 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 298 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) { 299 /* 300 * try to tame the ASMedia 1042 controller which reports 0.96 301 * but appears to behave more like 1.0 302 */ 303 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 304 xhci->quirks |= XHCI_BROKEN_STREAMS; 305 } 306 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 307 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) { 308 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 309 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 310 } 311 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 312 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI || 313 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI || 314 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI)) 315 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 316 317 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 318 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 319 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 320 321 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 322 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 323 324 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 325 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 326 pdev->device == 0x9026) 327 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 328 329 if (pdev->vendor == PCI_VENDOR_ID_AMD && 330 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 || 331 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4)) 332 xhci->quirks |= XHCI_NO_SOFT_RETRY; 333 334 /* xHC spec requires PCI devices to support D3hot and D3cold */ 335 if (xhci->hci_version >= 0x120) 336 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 337 338 if (xhci->quirks & XHCI_RESET_ON_RESUME) 339 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 340 "QUIRK: Resetting on resume"); 341 } 342 343 #ifdef CONFIG_ACPI 344 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 345 { 346 static const guid_t intel_dsm_guid = 347 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 348 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 349 union acpi_object *obj; 350 351 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 352 NULL); 353 ACPI_FREE(obj); 354 } 355 #else 356 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 357 #endif /* CONFIG_ACPI */ 358 359 /* called during probe() after chip reset completes */ 360 static int xhci_pci_setup(struct usb_hcd *hcd) 361 { 362 struct xhci_hcd *xhci; 363 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 364 int retval; 365 366 xhci = hcd_to_xhci(hcd); 367 if (!xhci->sbrn) 368 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 369 370 /* imod_interval is the interrupt moderation value in nanoseconds. */ 371 xhci->imod_interval = 40000; 372 373 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 374 if (retval) 375 return retval; 376 377 if (!usb_hcd_is_primary_hcd(hcd)) 378 return 0; 379 380 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 381 xhci_pme_acpi_rtd3_enable(pdev); 382 383 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 384 385 /* Find any debug ports */ 386 return xhci_pci_reinit(xhci, pdev); 387 } 388 389 /* 390 * We need to register our own PCI probe function (instead of the USB core's 391 * function) in order to create a second roothub under xHCI. 392 */ 393 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 394 { 395 int retval; 396 struct xhci_hcd *xhci; 397 struct usb_hcd *hcd; 398 struct xhci_driver_data *driver_data; 399 struct reset_control *reset; 400 401 driver_data = (struct xhci_driver_data *)id->driver_data; 402 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) { 403 retval = renesas_xhci_check_request_fw(dev, id); 404 if (retval) 405 return retval; 406 } 407 408 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 409 if (IS_ERR(reset)) 410 return PTR_ERR(reset); 411 reset_control_reset(reset); 412 413 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 414 pm_runtime_get_noresume(&dev->dev); 415 416 /* Register the USB 2.0 roothub. 417 * FIXME: USB core must know to register the USB 2.0 roothub first. 418 * This is sort of silly, because we could just set the HCD driver flags 419 * to say USB 2.0, but I'm not sure what the implications would be in 420 * the other parts of the HCD code. 421 */ 422 retval = usb_hcd_pci_probe(dev, &xhci_pci_hc_driver); 423 424 if (retval) 425 goto put_runtime_pm; 426 427 /* USB 2.0 roothub is stored in the PCI device now. */ 428 hcd = dev_get_drvdata(&dev->dev); 429 xhci = hcd_to_xhci(hcd); 430 xhci->reset = reset; 431 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev, 432 pci_name(dev), hcd); 433 if (!xhci->shared_hcd) { 434 retval = -ENOMEM; 435 goto dealloc_usb2_hcd; 436 } 437 438 retval = xhci_ext_cap_init(xhci); 439 if (retval) 440 goto put_usb3_hcd; 441 442 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 443 IRQF_SHARED); 444 if (retval) 445 goto put_usb3_hcd; 446 /* Roothub already marked as USB 3.0 speed */ 447 448 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 449 HCC_MAX_PSA(xhci->hcc_params) >= 4) 450 xhci->shared_hcd->can_do_streams = 1; 451 452 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 453 pm_runtime_put_noidle(&dev->dev); 454 455 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 456 pm_runtime_allow(&dev->dev); 457 458 return 0; 459 460 put_usb3_hcd: 461 usb_put_hcd(xhci->shared_hcd); 462 dealloc_usb2_hcd: 463 usb_hcd_pci_remove(dev); 464 put_runtime_pm: 465 pm_runtime_put_noidle(&dev->dev); 466 return retval; 467 } 468 469 static void xhci_pci_remove(struct pci_dev *dev) 470 { 471 struct xhci_hcd *xhci; 472 473 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 474 475 xhci->xhc_state |= XHCI_STATE_REMOVING; 476 477 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 478 pm_runtime_forbid(&dev->dev); 479 480 if (xhci->shared_hcd) { 481 usb_remove_hcd(xhci->shared_hcd); 482 usb_put_hcd(xhci->shared_hcd); 483 xhci->shared_hcd = NULL; 484 } 485 486 /* Workaround for spurious wakeups at shutdown with HSW */ 487 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 488 pci_set_power_state(dev, PCI_D3hot); 489 490 usb_hcd_pci_remove(dev); 491 } 492 493 #ifdef CONFIG_PM 494 /* 495 * In some Intel xHCI controllers, in order to get D3 working, 496 * through a vendor specific SSIC CONFIG register at offset 0x883c, 497 * SSIC PORT need to be marked as "unused" before putting xHCI 498 * into D3. After D3 exit, the SSIC port need to be marked as "used". 499 * Without this change, xHCI might not enter D3 state. 500 */ 501 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 502 { 503 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 504 u32 val; 505 void __iomem *reg; 506 int i; 507 508 for (i = 0; i < SSIC_PORT_NUM; i++) { 509 reg = (void __iomem *) xhci->cap_regs + 510 SSIC_PORT_CFG2 + 511 i * SSIC_PORT_CFG2_OFFSET; 512 513 /* Notify SSIC that SSIC profile programming is not done. */ 514 val = readl(reg) & ~PROG_DONE; 515 writel(val, reg); 516 517 /* Mark SSIC port as unused(suspend) or used(resume) */ 518 val = readl(reg); 519 if (suspend) 520 val |= SSIC_PORT_UNUSED; 521 else 522 val &= ~SSIC_PORT_UNUSED; 523 writel(val, reg); 524 525 /* Notify SSIC that SSIC profile programming is done */ 526 val = readl(reg) | PROG_DONE; 527 writel(val, reg); 528 readl(reg); 529 } 530 } 531 532 /* 533 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 534 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 535 */ 536 static void xhci_pme_quirk(struct usb_hcd *hcd) 537 { 538 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 539 void __iomem *reg; 540 u32 val; 541 542 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 543 val = readl(reg); 544 writel(val | BIT(28), reg); 545 readl(reg); 546 } 547 548 static void xhci_sparse_control_quirk(struct usb_hcd *hcd) 549 { 550 u32 reg; 551 552 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE); 553 reg &= ~BIT(SPARSE_DISABLE_BIT); 554 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE); 555 } 556 557 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 558 { 559 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 560 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 561 int ret; 562 563 /* 564 * Systems with the TI redriver that loses port status change events 565 * need to have the registers polled during D3, so avoid D3cold. 566 */ 567 if (xhci->quirks & (XHCI_COMP_MODE_QUIRK | XHCI_BROKEN_D3COLD)) 568 pci_d3cold_disable(pdev); 569 570 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 571 xhci_pme_quirk(hcd); 572 573 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 574 xhci_ssic_port_unused_quirk(hcd, true); 575 576 if (xhci->quirks & XHCI_DISABLE_SPARSE) 577 xhci_sparse_control_quirk(hcd); 578 579 ret = xhci_suspend(xhci, do_wakeup); 580 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 581 xhci_ssic_port_unused_quirk(hcd, false); 582 583 return ret; 584 } 585 586 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 587 { 588 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 589 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 590 int retval = 0; 591 592 reset_control_reset(xhci->reset); 593 594 /* The BIOS on systems with the Intel Panther Point chipset may or may 595 * not support xHCI natively. That means that during system resume, it 596 * may switch the ports back to EHCI so that users can use their 597 * keyboard to select a kernel from GRUB after resume from hibernate. 598 * 599 * The BIOS is supposed to remember whether the OS had xHCI ports 600 * enabled before resume, and switch the ports back to xHCI when the 601 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 602 * writers. 603 * 604 * Unconditionally switch the ports back to xHCI after a system resume. 605 * It should not matter whether the EHCI or xHCI controller is 606 * resumed first. It's enough to do the switchover in xHCI because 607 * USB core won't notice anything as the hub driver doesn't start 608 * running again until after all the devices (including both EHCI and 609 * xHCI host controllers) have been resumed. 610 */ 611 612 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 613 usb_enable_intel_xhci_ports(pdev); 614 615 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 616 xhci_ssic_port_unused_quirk(hcd, false); 617 618 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 619 xhci_pme_quirk(hcd); 620 621 retval = xhci_resume(xhci, hibernated); 622 return retval; 623 } 624 625 static int xhci_pci_poweroff_late(struct usb_hcd *hcd, bool do_wakeup) 626 { 627 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 628 struct xhci_port *port; 629 struct usb_device *udev; 630 unsigned int slot_id; 631 u32 portsc; 632 int i; 633 634 /* 635 * Systems with XHCI_RESET_TO_DEFAULT quirk have boot firmware that 636 * cause significant boot delay if usb ports are in suspended U3 state 637 * during boot. Some USB devices survive in U3 state over S4 hibernate 638 * 639 * Disable ports that are in U3 if remote wake is not enabled for either 640 * host controller or connected device 641 */ 642 643 if (!(xhci->quirks & XHCI_RESET_TO_DEFAULT)) 644 return 0; 645 646 for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) { 647 port = &xhci->hw_ports[i]; 648 portsc = readl(port->addr); 649 650 if ((portsc & PORT_PLS_MASK) != XDEV_U3) 651 continue; 652 653 slot_id = xhci_find_slot_id_by_port(port->rhub->hcd, xhci, 654 port->hcd_portnum + 1); 655 if (!slot_id || !xhci->devs[slot_id]) { 656 xhci_err(xhci, "No dev for slot_id %d for port %d-%d in U3\n", 657 slot_id, port->rhub->hcd->self.busnum, port->hcd_portnum + 1); 658 continue; 659 } 660 661 udev = xhci->devs[slot_id]->udev; 662 663 /* if wakeup is enabled then don't disable the port */ 664 if (udev->do_remote_wakeup && do_wakeup) 665 continue; 666 667 xhci_dbg(xhci, "port %d-%d in U3 without wakeup, disable it\n", 668 port->rhub->hcd->self.busnum, port->hcd_portnum + 1); 669 portsc = xhci_port_state_to_neutral(portsc); 670 writel(portsc | PORT_PE, port->addr); 671 } 672 673 return 0; 674 } 675 676 static void xhci_pci_shutdown(struct usb_hcd *hcd) 677 { 678 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 679 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 680 681 xhci_shutdown(hcd); 682 683 /* Yet another workaround for spurious wakeups at shutdown with HSW */ 684 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 685 pci_set_power_state(pdev, PCI_D3hot); 686 } 687 #endif /* CONFIG_PM */ 688 689 /*-------------------------------------------------------------------------*/ 690 691 static const struct xhci_driver_data reneses_data = { 692 .quirks = XHCI_RENESAS_FW_QUIRK, 693 .firmware = "renesas_usb_fw.mem", 694 }; 695 696 /* PCI driver selection metadata; PCI hotplugging uses this */ 697 static const struct pci_device_id pci_ids[] = { 698 { PCI_DEVICE(0x1912, 0x0014), 699 .driver_data = (unsigned long)&reneses_data, 700 }, 701 { PCI_DEVICE(0x1912, 0x0015), 702 .driver_data = (unsigned long)&reneses_data, 703 }, 704 /* handle any USB 3.0 xHCI controller */ 705 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 706 }, 707 { /* end: all zeroes */ } 708 }; 709 MODULE_DEVICE_TABLE(pci, pci_ids); 710 711 /* 712 * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't 713 * load firmware, so don't encumber the xhci-pci driver with it. 714 */ 715 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS) 716 MODULE_FIRMWARE("renesas_usb_fw.mem"); 717 #endif 718 719 /* pci driver glue; this is a "new style" PCI driver module */ 720 static struct pci_driver xhci_pci_driver = { 721 .name = hcd_name, 722 .id_table = pci_ids, 723 724 .probe = xhci_pci_probe, 725 .remove = xhci_pci_remove, 726 /* suspend and resume implemented later */ 727 728 .shutdown = usb_hcd_pci_shutdown, 729 .driver = { 730 #ifdef CONFIG_PM 731 .pm = &usb_hcd_pci_pm_ops, 732 #endif 733 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 734 }, 735 }; 736 737 static int __init xhci_pci_init(void) 738 { 739 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 740 #ifdef CONFIG_PM 741 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend; 742 xhci_pci_hc_driver.pci_resume = xhci_pci_resume; 743 xhci_pci_hc_driver.pci_poweroff_late = xhci_pci_poweroff_late; 744 xhci_pci_hc_driver.shutdown = xhci_pci_shutdown; 745 #endif 746 return pci_register_driver(&xhci_pci_driver); 747 } 748 module_init(xhci_pci_init); 749 750 static void __exit xhci_pci_exit(void) 751 { 752 pci_unregister_driver(&xhci_pci_driver); 753 } 754 module_exit(xhci_pci_exit); 755 756 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 757 MODULE_LICENSE("GPL"); 758