1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 #include <linux/reset.h> 16 17 #include "xhci.h" 18 #include "xhci-trace.h" 19 #include "xhci-pci.h" 20 21 #define SSIC_PORT_NUM 2 22 #define SSIC_PORT_CFG2 0x880c 23 #define SSIC_PORT_CFG2_OFFSET 0x30 24 #define PROG_DONE (1 << 30) 25 #define SSIC_PORT_UNUSED (1 << 31) 26 #define SPARSE_DISABLE_BIT 17 27 #define SPARSE_CNTL_ENABLE 0xC12C 28 29 /* Device for a quirk */ 30 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 31 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 32 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 34 35 #define PCI_VENDOR_ID_ETRON 0x1b6f 36 #define PCI_DEVICE_ID_EJ168 0x7023 37 38 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 39 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 40 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 41 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 42 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 43 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 44 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 45 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 46 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 47 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 48 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 49 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 50 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1 51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 53 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 54 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 55 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 56 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 57 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af 58 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13 59 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138 60 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI 0x461e 61 62 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639 63 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 64 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 65 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 66 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 67 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042 68 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 69 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242 70 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142 71 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242 72 73 static const char hcd_name[] = "xhci_hcd"; 74 75 static struct hc_driver __read_mostly xhci_pci_hc_driver; 76 77 static int xhci_pci_setup(struct usb_hcd *hcd); 78 79 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 80 .reset = xhci_pci_setup, 81 }; 82 83 /* called after powerup, by probe or system-pm "wakeup" */ 84 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 85 { 86 /* 87 * TODO: Implement finding debug ports later. 88 * TODO: see if there are any quirks that need to be added to handle 89 * new extended capabilities. 90 */ 91 92 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 93 if (!pci_set_mwi(pdev)) 94 xhci_dbg(xhci, "MWI active\n"); 95 96 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 97 return 0; 98 } 99 100 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 101 { 102 struct pci_dev *pdev = to_pci_dev(dev); 103 struct xhci_driver_data *driver_data; 104 const struct pci_device_id *id; 105 106 id = pci_match_id(pdev->driver->id_table, pdev); 107 108 if (id && id->driver_data) { 109 driver_data = (struct xhci_driver_data *)id->driver_data; 110 xhci->quirks |= driver_data->quirks; 111 } 112 113 /* Look for vendor-specific quirks */ 114 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 115 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 116 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 117 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 118 pdev->revision == 0x0) { 119 xhci->quirks |= XHCI_RESET_EP_QUIRK; 120 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 121 "QUIRK: Fresco Logic xHC needs configure" 122 " endpoint cmd after reset endpoint"); 123 } 124 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 125 pdev->revision == 0x4) { 126 xhci->quirks |= XHCI_SLOW_SUSPEND; 127 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 128 "QUIRK: Fresco Logic xHC revision %u" 129 "must be suspended extra slowly", 130 pdev->revision); 131 } 132 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 133 xhci->quirks |= XHCI_BROKEN_STREAMS; 134 /* Fresco Logic confirms: all revisions of this chip do not 135 * support MSI, even though some of them claim to in their PCI 136 * capabilities. 137 */ 138 xhci->quirks |= XHCI_BROKEN_MSI; 139 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 140 "QUIRK: Fresco Logic revision %u " 141 "has broken MSI implementation", 142 pdev->revision); 143 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 144 } 145 146 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 147 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 148 xhci->quirks |= XHCI_BROKEN_STREAMS; 149 150 if (pdev->vendor == PCI_VENDOR_ID_NEC) 151 xhci->quirks |= XHCI_NEC_HOST; 152 153 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 154 xhci->quirks |= XHCI_AMD_0x96_HOST; 155 156 /* AMD PLL quirk */ 157 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) 158 xhci->quirks |= XHCI_AMD_PLL_FIX; 159 160 if (pdev->vendor == PCI_VENDOR_ID_AMD && 161 (pdev->device == 0x145c || 162 pdev->device == 0x15e0 || 163 pdev->device == 0x15e1 || 164 pdev->device == 0x43bb)) 165 xhci->quirks |= XHCI_SUSPEND_DELAY; 166 167 if (pdev->vendor == PCI_VENDOR_ID_AMD && 168 (pdev->device == 0x15e0 || pdev->device == 0x15e1)) 169 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; 170 171 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) { 172 xhci->quirks |= XHCI_DISABLE_SPARSE; 173 xhci->quirks |= XHCI_RESET_ON_RESUME; 174 } 175 176 if (pdev->vendor == PCI_VENDOR_ID_AMD) 177 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 178 179 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 180 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 181 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 182 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 183 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 184 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 185 186 if (pdev->vendor == PCI_VENDOR_ID_AMD && 187 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) 188 xhci->quirks |= XHCI_BROKEN_D3COLD; 189 190 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 191 xhci->quirks |= XHCI_LPM_SUPPORT; 192 xhci->quirks |= XHCI_INTEL_HOST; 193 xhci->quirks |= XHCI_AVOID_BEI; 194 } 195 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 196 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 197 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 198 xhci->limit_active_eps = 64; 199 xhci->quirks |= XHCI_SW_BW_CHECKING; 200 /* 201 * PPT desktop boards DH77EB and DH77DF will power back on after 202 * a few seconds of being shutdown. The fix for this is to 203 * switch the ports from xHCI to EHCI on shutdown. We can't use 204 * DMI information to find those particular boards (since each 205 * vendor will change the board name), so we have to key off all 206 * PPT chipsets. 207 */ 208 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 209 } 210 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 211 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 212 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 213 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 214 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 215 } 216 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 217 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 218 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 219 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 220 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 221 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 222 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 223 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI || 224 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) { 225 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 226 } 227 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 228 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 229 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 230 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 231 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 232 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 233 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI)) 234 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 235 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 236 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 237 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 238 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 239 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 240 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) 241 xhci->quirks |= XHCI_MISSING_CAS; 242 243 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 244 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 245 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 246 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI || 247 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 248 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 249 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 250 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 251 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || 252 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI || 253 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI || 254 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI || 255 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI)) 256 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 257 258 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 259 pdev->device == PCI_DEVICE_ID_EJ168) { 260 xhci->quirks |= XHCI_RESET_ON_RESUME; 261 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 262 xhci->quirks |= XHCI_BROKEN_STREAMS; 263 } 264 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 265 pdev->device == 0x0014) { 266 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 267 xhci->quirks |= XHCI_ZERO_64B_REGS; 268 } 269 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 270 pdev->device == 0x0015) { 271 xhci->quirks |= XHCI_RESET_ON_RESUME; 272 xhci->quirks |= XHCI_ZERO_64B_REGS; 273 } 274 if (pdev->vendor == PCI_VENDOR_ID_VIA) 275 xhci->quirks |= XHCI_RESET_ON_RESUME; 276 277 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 278 if (pdev->vendor == PCI_VENDOR_ID_VIA && 279 pdev->device == 0x3432) 280 xhci->quirks |= XHCI_BROKEN_STREAMS; 281 282 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) 283 xhci->quirks |= XHCI_LPM_SUPPORT; 284 285 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 286 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) 287 xhci->quirks |= XHCI_BROKEN_STREAMS; 288 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 289 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) { 290 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 291 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 292 } 293 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 294 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI || 295 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI || 296 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI)) 297 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 298 299 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 300 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 301 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 302 303 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 304 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 305 306 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 307 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 308 pdev->device == 0x9026) 309 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 310 311 if (pdev->vendor == PCI_VENDOR_ID_AMD && 312 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 || 313 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4)) 314 xhci->quirks |= XHCI_NO_SOFT_RETRY; 315 316 if (xhci->quirks & XHCI_RESET_ON_RESUME) 317 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 318 "QUIRK: Resetting on resume"); 319 } 320 321 #ifdef CONFIG_ACPI 322 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 323 { 324 static const guid_t intel_dsm_guid = 325 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 326 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 327 union acpi_object *obj; 328 329 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 330 NULL); 331 ACPI_FREE(obj); 332 } 333 #else 334 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 335 #endif /* CONFIG_ACPI */ 336 337 /* called during probe() after chip reset completes */ 338 static int xhci_pci_setup(struct usb_hcd *hcd) 339 { 340 struct xhci_hcd *xhci; 341 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 342 int retval; 343 344 xhci = hcd_to_xhci(hcd); 345 if (!xhci->sbrn) 346 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 347 348 /* imod_interval is the interrupt moderation value in nanoseconds. */ 349 xhci->imod_interval = 40000; 350 351 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 352 if (retval) 353 return retval; 354 355 if (!usb_hcd_is_primary_hcd(hcd)) 356 return 0; 357 358 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 359 xhci_pme_acpi_rtd3_enable(pdev); 360 361 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 362 363 /* Find any debug ports */ 364 return xhci_pci_reinit(xhci, pdev); 365 } 366 367 /* 368 * We need to register our own PCI probe function (instead of the USB core's 369 * function) in order to create a second roothub under xHCI. 370 */ 371 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 372 { 373 int retval; 374 struct xhci_hcd *xhci; 375 struct usb_hcd *hcd; 376 struct xhci_driver_data *driver_data; 377 struct reset_control *reset; 378 379 driver_data = (struct xhci_driver_data *)id->driver_data; 380 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) { 381 retval = renesas_xhci_check_request_fw(dev, id); 382 if (retval) 383 return retval; 384 } 385 386 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 387 if (IS_ERR(reset)) 388 return PTR_ERR(reset); 389 reset_control_reset(reset); 390 391 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 392 pm_runtime_get_noresume(&dev->dev); 393 394 /* Register the USB 2.0 roothub. 395 * FIXME: USB core must know to register the USB 2.0 roothub first. 396 * This is sort of silly, because we could just set the HCD driver flags 397 * to say USB 2.0, but I'm not sure what the implications would be in 398 * the other parts of the HCD code. 399 */ 400 retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver); 401 402 if (retval) 403 goto put_runtime_pm; 404 405 /* USB 2.0 roothub is stored in the PCI device now. */ 406 hcd = dev_get_drvdata(&dev->dev); 407 xhci = hcd_to_xhci(hcd); 408 xhci->reset = reset; 409 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev, 410 pci_name(dev), hcd); 411 if (!xhci->shared_hcd) { 412 retval = -ENOMEM; 413 goto dealloc_usb2_hcd; 414 } 415 416 retval = xhci_ext_cap_init(xhci); 417 if (retval) 418 goto put_usb3_hcd; 419 420 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 421 IRQF_SHARED); 422 if (retval) 423 goto put_usb3_hcd; 424 /* Roothub already marked as USB 3.0 speed */ 425 426 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 427 HCC_MAX_PSA(xhci->hcc_params) >= 4) 428 xhci->shared_hcd->can_do_streams = 1; 429 430 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 431 pm_runtime_put_noidle(&dev->dev); 432 433 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 434 pm_runtime_allow(&dev->dev); 435 436 return 0; 437 438 put_usb3_hcd: 439 usb_put_hcd(xhci->shared_hcd); 440 dealloc_usb2_hcd: 441 usb_hcd_pci_remove(dev); 442 put_runtime_pm: 443 pm_runtime_put_noidle(&dev->dev); 444 return retval; 445 } 446 447 static void xhci_pci_remove(struct pci_dev *dev) 448 { 449 struct xhci_hcd *xhci; 450 451 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 452 453 xhci->xhc_state |= XHCI_STATE_REMOVING; 454 455 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 456 pm_runtime_forbid(&dev->dev); 457 458 if (xhci->shared_hcd) { 459 usb_remove_hcd(xhci->shared_hcd); 460 usb_put_hcd(xhci->shared_hcd); 461 xhci->shared_hcd = NULL; 462 } 463 464 /* Workaround for spurious wakeups at shutdown with HSW */ 465 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 466 pci_set_power_state(dev, PCI_D3hot); 467 468 usb_hcd_pci_remove(dev); 469 } 470 471 #ifdef CONFIG_PM 472 /* 473 * In some Intel xHCI controllers, in order to get D3 working, 474 * through a vendor specific SSIC CONFIG register at offset 0x883c, 475 * SSIC PORT need to be marked as "unused" before putting xHCI 476 * into D3. After D3 exit, the SSIC port need to be marked as "used". 477 * Without this change, xHCI might not enter D3 state. 478 */ 479 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 480 { 481 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 482 u32 val; 483 void __iomem *reg; 484 int i; 485 486 for (i = 0; i < SSIC_PORT_NUM; i++) { 487 reg = (void __iomem *) xhci->cap_regs + 488 SSIC_PORT_CFG2 + 489 i * SSIC_PORT_CFG2_OFFSET; 490 491 /* Notify SSIC that SSIC profile programming is not done. */ 492 val = readl(reg) & ~PROG_DONE; 493 writel(val, reg); 494 495 /* Mark SSIC port as unused(suspend) or used(resume) */ 496 val = readl(reg); 497 if (suspend) 498 val |= SSIC_PORT_UNUSED; 499 else 500 val &= ~SSIC_PORT_UNUSED; 501 writel(val, reg); 502 503 /* Notify SSIC that SSIC profile programming is done */ 504 val = readl(reg) | PROG_DONE; 505 writel(val, reg); 506 readl(reg); 507 } 508 } 509 510 /* 511 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 512 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 513 */ 514 static void xhci_pme_quirk(struct usb_hcd *hcd) 515 { 516 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 517 void __iomem *reg; 518 u32 val; 519 520 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 521 val = readl(reg); 522 writel(val | BIT(28), reg); 523 readl(reg); 524 } 525 526 static void xhci_sparse_control_quirk(struct usb_hcd *hcd) 527 { 528 u32 reg; 529 530 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE); 531 reg &= ~BIT(SPARSE_DISABLE_BIT); 532 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE); 533 } 534 535 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 536 { 537 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 538 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 539 int ret; 540 541 /* 542 * Systems with the TI redriver that loses port status change events 543 * need to have the registers polled during D3, so avoid D3cold. 544 */ 545 if (xhci->quirks & (XHCI_COMP_MODE_QUIRK | XHCI_BROKEN_D3COLD)) 546 pci_d3cold_disable(pdev); 547 548 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 549 xhci_pme_quirk(hcd); 550 551 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 552 xhci_ssic_port_unused_quirk(hcd, true); 553 554 if (xhci->quirks & XHCI_DISABLE_SPARSE) 555 xhci_sparse_control_quirk(hcd); 556 557 ret = xhci_suspend(xhci, do_wakeup); 558 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 559 xhci_ssic_port_unused_quirk(hcd, false); 560 561 return ret; 562 } 563 564 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 565 { 566 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 567 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 568 int retval = 0; 569 570 reset_control_reset(xhci->reset); 571 572 /* The BIOS on systems with the Intel Panther Point chipset may or may 573 * not support xHCI natively. That means that during system resume, it 574 * may switch the ports back to EHCI so that users can use their 575 * keyboard to select a kernel from GRUB after resume from hibernate. 576 * 577 * The BIOS is supposed to remember whether the OS had xHCI ports 578 * enabled before resume, and switch the ports back to xHCI when the 579 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 580 * writers. 581 * 582 * Unconditionally switch the ports back to xHCI after a system resume. 583 * It should not matter whether the EHCI or xHCI controller is 584 * resumed first. It's enough to do the switchover in xHCI because 585 * USB core won't notice anything as the hub driver doesn't start 586 * running again until after all the devices (including both EHCI and 587 * xHCI host controllers) have been resumed. 588 */ 589 590 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 591 usb_enable_intel_xhci_ports(pdev); 592 593 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 594 xhci_ssic_port_unused_quirk(hcd, false); 595 596 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 597 xhci_pme_quirk(hcd); 598 599 retval = xhci_resume(xhci, hibernated); 600 return retval; 601 } 602 603 static void xhci_pci_shutdown(struct usb_hcd *hcd) 604 { 605 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 606 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 607 608 xhci_shutdown(hcd); 609 610 /* Yet another workaround for spurious wakeups at shutdown with HSW */ 611 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 612 pci_set_power_state(pdev, PCI_D3hot); 613 } 614 #endif /* CONFIG_PM */ 615 616 /*-------------------------------------------------------------------------*/ 617 618 static const struct xhci_driver_data reneses_data = { 619 .quirks = XHCI_RENESAS_FW_QUIRK, 620 .firmware = "renesas_usb_fw.mem", 621 }; 622 623 /* PCI driver selection metadata; PCI hotplugging uses this */ 624 static const struct pci_device_id pci_ids[] = { 625 { PCI_DEVICE(0x1912, 0x0014), 626 .driver_data = (unsigned long)&reneses_data, 627 }, 628 { PCI_DEVICE(0x1912, 0x0015), 629 .driver_data = (unsigned long)&reneses_data, 630 }, 631 /* handle any USB 3.0 xHCI controller */ 632 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 633 }, 634 { /* end: all zeroes */ } 635 }; 636 MODULE_DEVICE_TABLE(pci, pci_ids); 637 638 /* 639 * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't 640 * load firmware, so don't encumber the xhci-pci driver with it. 641 */ 642 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS) 643 MODULE_FIRMWARE("renesas_usb_fw.mem"); 644 #endif 645 646 /* pci driver glue; this is a "new style" PCI driver module */ 647 static struct pci_driver xhci_pci_driver = { 648 .name = hcd_name, 649 .id_table = pci_ids, 650 651 .probe = xhci_pci_probe, 652 .remove = xhci_pci_remove, 653 /* suspend and resume implemented later */ 654 655 .shutdown = usb_hcd_pci_shutdown, 656 #ifdef CONFIG_PM 657 .driver = { 658 .pm = &usb_hcd_pci_pm_ops 659 }, 660 #endif 661 }; 662 663 static int __init xhci_pci_init(void) 664 { 665 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 666 #ifdef CONFIG_PM 667 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend; 668 xhci_pci_hc_driver.pci_resume = xhci_pci_resume; 669 xhci_pci_hc_driver.shutdown = xhci_pci_shutdown; 670 #endif 671 return pci_register_driver(&xhci_pci_driver); 672 } 673 module_init(xhci_pci_init); 674 675 static void __exit xhci_pci_exit(void) 676 { 677 pci_unregister_driver(&xhci_pci_driver); 678 } 679 module_exit(xhci_pci_exit); 680 681 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 682 MODULE_LICENSE("GPL"); 683