1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 #include <linux/reset.h> 16 17 #include "xhci.h" 18 #include "xhci-trace.h" 19 #include "xhci-pci.h" 20 21 #define SSIC_PORT_NUM 2 22 #define SSIC_PORT_CFG2 0x880c 23 #define SSIC_PORT_CFG2_OFFSET 0x30 24 #define PROG_DONE (1 << 30) 25 #define SSIC_PORT_UNUSED (1 << 31) 26 #define SPARSE_DISABLE_BIT 17 27 #define SPARSE_CNTL_ENABLE 0xC12C 28 29 /* Device for a quirk */ 30 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 31 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 32 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100 34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 35 36 #define PCI_VENDOR_ID_ETRON 0x1b6f 37 #define PCI_DEVICE_ID_EJ168 0x7023 38 39 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 40 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 41 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 42 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 43 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 44 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 45 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 46 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 47 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 48 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 49 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 50 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1 52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 53 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 54 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 55 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 56 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 57 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 58 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af 59 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13 60 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138 61 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI 0x461e 62 63 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639 64 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 65 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 66 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 67 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 68 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042 69 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 70 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242 71 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142 72 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242 73 74 static const char hcd_name[] = "xhci_hcd"; 75 76 static struct hc_driver __read_mostly xhci_pci_hc_driver; 77 78 static int xhci_pci_setup(struct usb_hcd *hcd); 79 80 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 81 .reset = xhci_pci_setup, 82 }; 83 84 /* called after powerup, by probe or system-pm "wakeup" */ 85 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 86 { 87 /* 88 * TODO: Implement finding debug ports later. 89 * TODO: see if there are any quirks that need to be added to handle 90 * new extended capabilities. 91 */ 92 93 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 94 if (!pci_set_mwi(pdev)) 95 xhci_dbg(xhci, "MWI active\n"); 96 97 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 98 return 0; 99 } 100 101 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 102 { 103 struct pci_dev *pdev = to_pci_dev(dev); 104 struct xhci_driver_data *driver_data; 105 const struct pci_device_id *id; 106 107 id = pci_match_id(pdev->driver->id_table, pdev); 108 109 if (id && id->driver_data) { 110 driver_data = (struct xhci_driver_data *)id->driver_data; 111 xhci->quirks |= driver_data->quirks; 112 } 113 114 /* Look for vendor-specific quirks */ 115 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 116 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 117 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 || 118 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 119 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 120 pdev->revision == 0x0) { 121 xhci->quirks |= XHCI_RESET_EP_QUIRK; 122 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 123 "QUIRK: Fresco Logic xHC needs configure" 124 " endpoint cmd after reset endpoint"); 125 } 126 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 127 pdev->revision == 0x4) { 128 xhci->quirks |= XHCI_SLOW_SUSPEND; 129 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 130 "QUIRK: Fresco Logic xHC revision %u" 131 "must be suspended extra slowly", 132 pdev->revision); 133 } 134 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 135 xhci->quirks |= XHCI_BROKEN_STREAMS; 136 /* Fresco Logic confirms: all revisions of this chip do not 137 * support MSI, even though some of them claim to in their PCI 138 * capabilities. 139 */ 140 xhci->quirks |= XHCI_BROKEN_MSI; 141 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 142 "QUIRK: Fresco Logic revision %u " 143 "has broken MSI implementation", 144 pdev->revision); 145 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 146 } 147 148 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 149 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 150 xhci->quirks |= XHCI_BROKEN_STREAMS; 151 152 if (pdev->vendor == PCI_VENDOR_ID_NEC) 153 xhci->quirks |= XHCI_NEC_HOST; 154 155 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 156 xhci->quirks |= XHCI_AMD_0x96_HOST; 157 158 /* AMD PLL quirk */ 159 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) 160 xhci->quirks |= XHCI_AMD_PLL_FIX; 161 162 if (pdev->vendor == PCI_VENDOR_ID_AMD && 163 (pdev->device == 0x145c || 164 pdev->device == 0x15e0 || 165 pdev->device == 0x15e1 || 166 pdev->device == 0x43bb)) 167 xhci->quirks |= XHCI_SUSPEND_DELAY; 168 169 if (pdev->vendor == PCI_VENDOR_ID_AMD && 170 (pdev->device == 0x15e0 || pdev->device == 0x15e1)) 171 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; 172 173 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) { 174 xhci->quirks |= XHCI_DISABLE_SPARSE; 175 xhci->quirks |= XHCI_RESET_ON_RESUME; 176 } 177 178 if (pdev->vendor == PCI_VENDOR_ID_AMD) 179 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 180 181 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 182 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 183 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 184 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 185 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 186 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 187 188 if (pdev->vendor == PCI_VENDOR_ID_AMD && 189 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) 190 xhci->quirks |= XHCI_BROKEN_D3COLD; 191 192 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 193 xhci->quirks |= XHCI_LPM_SUPPORT; 194 xhci->quirks |= XHCI_INTEL_HOST; 195 xhci->quirks |= XHCI_AVOID_BEI; 196 } 197 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 198 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 199 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 200 xhci->limit_active_eps = 64; 201 xhci->quirks |= XHCI_SW_BW_CHECKING; 202 /* 203 * PPT desktop boards DH77EB and DH77DF will power back on after 204 * a few seconds of being shutdown. The fix for this is to 205 * switch the ports from xHCI to EHCI on shutdown. We can't use 206 * DMI information to find those particular boards (since each 207 * vendor will change the board name), so we have to key off all 208 * PPT chipsets. 209 */ 210 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 211 } 212 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 213 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 214 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 215 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 216 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 217 } 218 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 219 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 220 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 221 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 222 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 223 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 224 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 225 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI || 226 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) { 227 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 228 } 229 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 230 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 231 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 232 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 233 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 234 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 235 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI)) 236 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 237 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 238 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 239 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 240 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 241 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 242 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) 243 xhci->quirks |= XHCI_MISSING_CAS; 244 245 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 246 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 247 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 248 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI || 249 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 250 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 251 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 252 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 253 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || 254 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI || 255 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI || 256 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI || 257 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI)) 258 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 259 260 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 261 pdev->device == PCI_DEVICE_ID_EJ168) { 262 xhci->quirks |= XHCI_RESET_ON_RESUME; 263 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 264 xhci->quirks |= XHCI_BROKEN_STREAMS; 265 } 266 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 267 pdev->device == 0x0014) { 268 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 269 xhci->quirks |= XHCI_ZERO_64B_REGS; 270 } 271 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 272 pdev->device == 0x0015) { 273 xhci->quirks |= XHCI_RESET_ON_RESUME; 274 xhci->quirks |= XHCI_ZERO_64B_REGS; 275 } 276 if (pdev->vendor == PCI_VENDOR_ID_VIA) 277 xhci->quirks |= XHCI_RESET_ON_RESUME; 278 279 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 280 if (pdev->vendor == PCI_VENDOR_ID_VIA && 281 pdev->device == 0x3432) 282 xhci->quirks |= XHCI_BROKEN_STREAMS; 283 284 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) { 285 xhci->quirks |= XHCI_LPM_SUPPORT; 286 xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS; 287 } 288 289 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 290 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) 291 xhci->quirks |= XHCI_BROKEN_STREAMS; 292 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 293 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) { 294 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 295 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 296 } 297 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 298 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI || 299 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI || 300 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI)) 301 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 302 303 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 304 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 305 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 306 307 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 308 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 309 310 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 311 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 312 pdev->device == 0x9026) 313 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 314 315 if (pdev->vendor == PCI_VENDOR_ID_AMD && 316 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 || 317 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4)) 318 xhci->quirks |= XHCI_NO_SOFT_RETRY; 319 320 if (xhci->quirks & XHCI_RESET_ON_RESUME) 321 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 322 "QUIRK: Resetting on resume"); 323 } 324 325 #ifdef CONFIG_ACPI 326 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 327 { 328 static const guid_t intel_dsm_guid = 329 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 330 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 331 union acpi_object *obj; 332 333 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 334 NULL); 335 ACPI_FREE(obj); 336 } 337 #else 338 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 339 #endif /* CONFIG_ACPI */ 340 341 /* called during probe() after chip reset completes */ 342 static int xhci_pci_setup(struct usb_hcd *hcd) 343 { 344 struct xhci_hcd *xhci; 345 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 346 int retval; 347 348 xhci = hcd_to_xhci(hcd); 349 if (!xhci->sbrn) 350 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 351 352 /* imod_interval is the interrupt moderation value in nanoseconds. */ 353 xhci->imod_interval = 40000; 354 355 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 356 if (retval) 357 return retval; 358 359 if (!usb_hcd_is_primary_hcd(hcd)) 360 return 0; 361 362 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 363 xhci_pme_acpi_rtd3_enable(pdev); 364 365 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 366 367 /* Find any debug ports */ 368 return xhci_pci_reinit(xhci, pdev); 369 } 370 371 /* 372 * We need to register our own PCI probe function (instead of the USB core's 373 * function) in order to create a second roothub under xHCI. 374 */ 375 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 376 { 377 int retval; 378 struct xhci_hcd *xhci; 379 struct usb_hcd *hcd; 380 struct xhci_driver_data *driver_data; 381 struct reset_control *reset; 382 383 driver_data = (struct xhci_driver_data *)id->driver_data; 384 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) { 385 retval = renesas_xhci_check_request_fw(dev, id); 386 if (retval) 387 return retval; 388 } 389 390 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 391 if (IS_ERR(reset)) 392 return PTR_ERR(reset); 393 reset_control_reset(reset); 394 395 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 396 pm_runtime_get_noresume(&dev->dev); 397 398 /* Register the USB 2.0 roothub. 399 * FIXME: USB core must know to register the USB 2.0 roothub first. 400 * This is sort of silly, because we could just set the HCD driver flags 401 * to say USB 2.0, but I'm not sure what the implications would be in 402 * the other parts of the HCD code. 403 */ 404 retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver); 405 406 if (retval) 407 goto put_runtime_pm; 408 409 /* USB 2.0 roothub is stored in the PCI device now. */ 410 hcd = dev_get_drvdata(&dev->dev); 411 xhci = hcd_to_xhci(hcd); 412 xhci->reset = reset; 413 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev, 414 pci_name(dev), hcd); 415 if (!xhci->shared_hcd) { 416 retval = -ENOMEM; 417 goto dealloc_usb2_hcd; 418 } 419 420 retval = xhci_ext_cap_init(xhci); 421 if (retval) 422 goto put_usb3_hcd; 423 424 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 425 IRQF_SHARED); 426 if (retval) 427 goto put_usb3_hcd; 428 /* Roothub already marked as USB 3.0 speed */ 429 430 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 431 HCC_MAX_PSA(xhci->hcc_params) >= 4) 432 xhci->shared_hcd->can_do_streams = 1; 433 434 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 435 pm_runtime_put_noidle(&dev->dev); 436 437 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 438 pm_runtime_allow(&dev->dev); 439 440 return 0; 441 442 put_usb3_hcd: 443 usb_put_hcd(xhci->shared_hcd); 444 dealloc_usb2_hcd: 445 usb_hcd_pci_remove(dev); 446 put_runtime_pm: 447 pm_runtime_put_noidle(&dev->dev); 448 return retval; 449 } 450 451 static void xhci_pci_remove(struct pci_dev *dev) 452 { 453 struct xhci_hcd *xhci; 454 455 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 456 457 xhci->xhc_state |= XHCI_STATE_REMOVING; 458 459 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 460 pm_runtime_forbid(&dev->dev); 461 462 if (xhci->shared_hcd) { 463 usb_remove_hcd(xhci->shared_hcd); 464 usb_put_hcd(xhci->shared_hcd); 465 xhci->shared_hcd = NULL; 466 } 467 468 /* Workaround for spurious wakeups at shutdown with HSW */ 469 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 470 pci_set_power_state(dev, PCI_D3hot); 471 472 usb_hcd_pci_remove(dev); 473 } 474 475 #ifdef CONFIG_PM 476 /* 477 * In some Intel xHCI controllers, in order to get D3 working, 478 * through a vendor specific SSIC CONFIG register at offset 0x883c, 479 * SSIC PORT need to be marked as "unused" before putting xHCI 480 * into D3. After D3 exit, the SSIC port need to be marked as "used". 481 * Without this change, xHCI might not enter D3 state. 482 */ 483 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 484 { 485 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 486 u32 val; 487 void __iomem *reg; 488 int i; 489 490 for (i = 0; i < SSIC_PORT_NUM; i++) { 491 reg = (void __iomem *) xhci->cap_regs + 492 SSIC_PORT_CFG2 + 493 i * SSIC_PORT_CFG2_OFFSET; 494 495 /* Notify SSIC that SSIC profile programming is not done. */ 496 val = readl(reg) & ~PROG_DONE; 497 writel(val, reg); 498 499 /* Mark SSIC port as unused(suspend) or used(resume) */ 500 val = readl(reg); 501 if (suspend) 502 val |= SSIC_PORT_UNUSED; 503 else 504 val &= ~SSIC_PORT_UNUSED; 505 writel(val, reg); 506 507 /* Notify SSIC that SSIC profile programming is done */ 508 val = readl(reg) | PROG_DONE; 509 writel(val, reg); 510 readl(reg); 511 } 512 } 513 514 /* 515 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 516 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 517 */ 518 static void xhci_pme_quirk(struct usb_hcd *hcd) 519 { 520 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 521 void __iomem *reg; 522 u32 val; 523 524 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 525 val = readl(reg); 526 writel(val | BIT(28), reg); 527 readl(reg); 528 } 529 530 static void xhci_sparse_control_quirk(struct usb_hcd *hcd) 531 { 532 u32 reg; 533 534 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE); 535 reg &= ~BIT(SPARSE_DISABLE_BIT); 536 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE); 537 } 538 539 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 540 { 541 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 542 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 543 int ret; 544 545 /* 546 * Systems with the TI redriver that loses port status change events 547 * need to have the registers polled during D3, so avoid D3cold. 548 */ 549 if (xhci->quirks & (XHCI_COMP_MODE_QUIRK | XHCI_BROKEN_D3COLD)) 550 pci_d3cold_disable(pdev); 551 552 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 553 xhci_pme_quirk(hcd); 554 555 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 556 xhci_ssic_port_unused_quirk(hcd, true); 557 558 if (xhci->quirks & XHCI_DISABLE_SPARSE) 559 xhci_sparse_control_quirk(hcd); 560 561 ret = xhci_suspend(xhci, do_wakeup); 562 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 563 xhci_ssic_port_unused_quirk(hcd, false); 564 565 return ret; 566 } 567 568 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 569 { 570 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 571 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 572 int retval = 0; 573 574 reset_control_reset(xhci->reset); 575 576 /* The BIOS on systems with the Intel Panther Point chipset may or may 577 * not support xHCI natively. That means that during system resume, it 578 * may switch the ports back to EHCI so that users can use their 579 * keyboard to select a kernel from GRUB after resume from hibernate. 580 * 581 * The BIOS is supposed to remember whether the OS had xHCI ports 582 * enabled before resume, and switch the ports back to xHCI when the 583 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 584 * writers. 585 * 586 * Unconditionally switch the ports back to xHCI after a system resume. 587 * It should not matter whether the EHCI or xHCI controller is 588 * resumed first. It's enough to do the switchover in xHCI because 589 * USB core won't notice anything as the hub driver doesn't start 590 * running again until after all the devices (including both EHCI and 591 * xHCI host controllers) have been resumed. 592 */ 593 594 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 595 usb_enable_intel_xhci_ports(pdev); 596 597 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 598 xhci_ssic_port_unused_quirk(hcd, false); 599 600 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 601 xhci_pme_quirk(hcd); 602 603 retval = xhci_resume(xhci, hibernated); 604 return retval; 605 } 606 607 static void xhci_pci_shutdown(struct usb_hcd *hcd) 608 { 609 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 610 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 611 612 xhci_shutdown(hcd); 613 614 /* Yet another workaround for spurious wakeups at shutdown with HSW */ 615 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 616 pci_set_power_state(pdev, PCI_D3hot); 617 } 618 #endif /* CONFIG_PM */ 619 620 /*-------------------------------------------------------------------------*/ 621 622 static const struct xhci_driver_data reneses_data = { 623 .quirks = XHCI_RENESAS_FW_QUIRK, 624 .firmware = "renesas_usb_fw.mem", 625 }; 626 627 /* PCI driver selection metadata; PCI hotplugging uses this */ 628 static const struct pci_device_id pci_ids[] = { 629 { PCI_DEVICE(0x1912, 0x0014), 630 .driver_data = (unsigned long)&reneses_data, 631 }, 632 { PCI_DEVICE(0x1912, 0x0015), 633 .driver_data = (unsigned long)&reneses_data, 634 }, 635 /* handle any USB 3.0 xHCI controller */ 636 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 637 }, 638 { /* end: all zeroes */ } 639 }; 640 MODULE_DEVICE_TABLE(pci, pci_ids); 641 642 /* 643 * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't 644 * load firmware, so don't encumber the xhci-pci driver with it. 645 */ 646 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS) 647 MODULE_FIRMWARE("renesas_usb_fw.mem"); 648 #endif 649 650 /* pci driver glue; this is a "new style" PCI driver module */ 651 static struct pci_driver xhci_pci_driver = { 652 .name = hcd_name, 653 .id_table = pci_ids, 654 655 .probe = xhci_pci_probe, 656 .remove = xhci_pci_remove, 657 /* suspend and resume implemented later */ 658 659 .shutdown = usb_hcd_pci_shutdown, 660 #ifdef CONFIG_PM 661 .driver = { 662 .pm = &usb_hcd_pci_pm_ops 663 }, 664 #endif 665 }; 666 667 static int __init xhci_pci_init(void) 668 { 669 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 670 #ifdef CONFIG_PM 671 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend; 672 xhci_pci_hc_driver.pci_resume = xhci_pci_resume; 673 xhci_pci_hc_driver.shutdown = xhci_pci_shutdown; 674 #endif 675 return pci_register_driver(&xhci_pci_driver); 676 } 677 module_init(xhci_pci_init); 678 679 static void __exit xhci_pci_exit(void) 680 { 681 pci_unregister_driver(&xhci_pci_driver); 682 } 683 module_exit(xhci_pci_exit); 684 685 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 686 MODULE_LICENSE("GPL"); 687