1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 #include <linux/reset.h> 16 #include <linux/suspend.h> 17 18 #include "xhci.h" 19 #include "xhci-trace.h" 20 #include "xhci-pci.h" 21 22 #define SSIC_PORT_NUM 2 23 #define SSIC_PORT_CFG2 0x880c 24 #define SSIC_PORT_CFG2_OFFSET 0x30 25 #define PROG_DONE (1 << 30) 26 #define SSIC_PORT_UNUSED (1 << 31) 27 #define SPARSE_DISABLE_BIT 17 28 #define SPARSE_CNTL_ENABLE 0xC12C 29 30 /* Device for a quirk */ 31 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 32 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100 35 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 36 37 #define PCI_VENDOR_ID_ETRON 0x1b6f 38 #define PCI_DEVICE_ID_EJ168 0x7023 39 #define PCI_DEVICE_ID_EJ188 0x7052 40 41 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 42 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 43 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 44 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 45 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 46 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 47 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 48 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 49 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 50 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 53 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1 54 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 55 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 56 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 57 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 58 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 59 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 60 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af 61 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13 62 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138 63 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed 64 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI 0x54ed 65 66 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639 67 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 68 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 69 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 70 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 71 72 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042 73 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 74 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242 75 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142 76 #define PCI_DEVICE_ID_ASMEDIA_3042_XHCI 0x3042 77 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242 78 79 #define PCI_DEVICE_ID_CADENCE 0x17CD 80 #define PCI_DEVICE_ID_CADENCE_SSP 0x0200 81 82 static const char hcd_name[] = "xhci_hcd"; 83 84 static struct hc_driver __read_mostly xhci_pci_hc_driver; 85 86 static int xhci_pci_setup(struct usb_hcd *hcd); 87 static int xhci_pci_run(struct usb_hcd *hcd); 88 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 89 struct usb_tt *tt, gfp_t mem_flags); 90 91 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 92 .reset = xhci_pci_setup, 93 .start = xhci_pci_run, 94 .update_hub_device = xhci_pci_update_hub_device, 95 }; 96 97 static void xhci_msix_sync_irqs(struct xhci_hcd *xhci) 98 { 99 struct usb_hcd *hcd = xhci_to_hcd(xhci); 100 101 if (hcd->msix_enabled) { 102 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 103 int i; 104 105 for (i = 0; i < xhci->msix_count; i++) 106 synchronize_irq(pci_irq_vector(pdev, i)); 107 } 108 } 109 110 /* Free any IRQs and disable MSI-X */ 111 static void xhci_cleanup_msix(struct xhci_hcd *xhci) 112 { 113 struct usb_hcd *hcd = xhci_to_hcd(xhci); 114 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 115 116 /* return if using legacy interrupt */ 117 if (hcd->irq > 0) 118 return; 119 120 if (hcd->msix_enabled) { 121 int i; 122 123 for (i = 0; i < xhci->msix_count; i++) 124 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci)); 125 } else { 126 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci)); 127 } 128 129 pci_free_irq_vectors(pdev); 130 hcd->msix_enabled = 0; 131 } 132 133 /* 134 * Set up MSI 135 */ 136 static int xhci_setup_msi(struct xhci_hcd *xhci) 137 { 138 int ret; 139 /* 140 * TODO:Check with MSI Soc for sysdev 141 */ 142 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); 143 144 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 145 if (ret < 0) { 146 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 147 "failed to allocate MSI entry"); 148 return ret; 149 } 150 151 ret = request_irq(pdev->irq, xhci_msi_irq, 152 0, "xhci_hcd", xhci_to_hcd(xhci)); 153 if (ret) { 154 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 155 "disable MSI interrupt"); 156 pci_free_irq_vectors(pdev); 157 } 158 159 return ret; 160 } 161 162 /* 163 * Set up MSI-X 164 */ 165 static int xhci_setup_msix(struct xhci_hcd *xhci) 166 { 167 int i, ret; 168 struct usb_hcd *hcd = xhci_to_hcd(xhci); 169 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 170 171 /* 172 * calculate number of msi-x vectors supported. 173 * - HCS_MAX_INTRS: the max number of interrupts the host can handle, 174 * with max number of interrupters based on the xhci HCSPARAMS1. 175 * - num_online_cpus: maximum msi-x vectors per CPUs core. 176 * Add additional 1 vector to ensure always available interrupt. 177 */ 178 xhci->msix_count = min(num_online_cpus() + 1, 179 HCS_MAX_INTRS(xhci->hcs_params1)); 180 181 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count, 182 PCI_IRQ_MSIX); 183 if (ret < 0) { 184 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 185 "Failed to enable MSI-X"); 186 return ret; 187 } 188 189 for (i = 0; i < xhci->msix_count; i++) { 190 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0, 191 "xhci_hcd", xhci_to_hcd(xhci)); 192 if (ret) 193 goto disable_msix; 194 } 195 196 hcd->msix_enabled = 1; 197 return ret; 198 199 disable_msix: 200 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt"); 201 while (--i >= 0) 202 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci)); 203 pci_free_irq_vectors(pdev); 204 return ret; 205 } 206 207 static int xhci_try_enable_msi(struct usb_hcd *hcd) 208 { 209 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 210 struct pci_dev *pdev; 211 int ret; 212 213 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); 214 /* 215 * Some Fresco Logic host controllers advertise MSI, but fail to 216 * generate interrupts. Don't even try to enable MSI. 217 */ 218 if (xhci->quirks & XHCI_BROKEN_MSI) 219 goto legacy_irq; 220 221 /* unregister the legacy interrupt */ 222 if (hcd->irq) 223 free_irq(hcd->irq, hcd); 224 hcd->irq = 0; 225 226 ret = xhci_setup_msix(xhci); 227 if (ret) 228 /* fall back to msi*/ 229 ret = xhci_setup_msi(xhci); 230 231 if (!ret) { 232 hcd->msi_enabled = 1; 233 return 0; 234 } 235 236 if (!pdev->irq) { 237 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n"); 238 return -EINVAL; 239 } 240 241 legacy_irq: 242 if (!strlen(hcd->irq_descr)) 243 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d", 244 hcd->driver->description, hcd->self.busnum); 245 246 /* fall back to legacy interrupt*/ 247 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, 248 hcd->irq_descr, hcd); 249 if (ret) { 250 xhci_err(xhci, "request interrupt %d failed\n", 251 pdev->irq); 252 return ret; 253 } 254 hcd->irq = pdev->irq; 255 return 0; 256 } 257 258 static int xhci_pci_run(struct usb_hcd *hcd) 259 { 260 int ret; 261 262 if (usb_hcd_is_primary_hcd(hcd)) { 263 ret = xhci_try_enable_msi(hcd); 264 if (ret) 265 return ret; 266 } 267 268 return xhci_run(hcd); 269 } 270 271 static void xhci_pci_stop(struct usb_hcd *hcd) 272 { 273 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 274 275 xhci_stop(hcd); 276 277 if (usb_hcd_is_primary_hcd(hcd)) 278 xhci_cleanup_msix(xhci); 279 } 280 281 /* called after powerup, by probe or system-pm "wakeup" */ 282 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 283 { 284 /* 285 * TODO: Implement finding debug ports later. 286 * TODO: see if there are any quirks that need to be added to handle 287 * new extended capabilities. 288 */ 289 290 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 291 if (!pci_set_mwi(pdev)) 292 xhci_dbg(xhci, "MWI active\n"); 293 294 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 295 return 0; 296 } 297 298 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 299 { 300 struct pci_dev *pdev = to_pci_dev(dev); 301 struct xhci_driver_data *driver_data; 302 const struct pci_device_id *id; 303 304 id = pci_match_id(to_pci_driver(pdev->dev.driver)->id_table, pdev); 305 306 if (id && id->driver_data) { 307 driver_data = (struct xhci_driver_data *)id->driver_data; 308 xhci->quirks |= driver_data->quirks; 309 } 310 311 /* Look for vendor-specific quirks */ 312 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 313 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 314 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 315 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 316 pdev->revision == 0x0) { 317 xhci->quirks |= XHCI_RESET_EP_QUIRK; 318 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 319 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated"); 320 } 321 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 322 pdev->revision == 0x4) { 323 xhci->quirks |= XHCI_SLOW_SUSPEND; 324 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 325 "QUIRK: Fresco Logic xHC revision %u" 326 "must be suspended extra slowly", 327 pdev->revision); 328 } 329 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 330 xhci->quirks |= XHCI_BROKEN_STREAMS; 331 /* Fresco Logic confirms: all revisions of this chip do not 332 * support MSI, even though some of them claim to in their PCI 333 * capabilities. 334 */ 335 xhci->quirks |= XHCI_BROKEN_MSI; 336 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 337 "QUIRK: Fresco Logic revision %u " 338 "has broken MSI implementation", 339 pdev->revision); 340 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 341 } 342 343 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 344 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 345 xhci->quirks |= XHCI_BROKEN_STREAMS; 346 347 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 348 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100) 349 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 350 351 if (pdev->vendor == PCI_VENDOR_ID_NEC) 352 xhci->quirks |= XHCI_NEC_HOST; 353 354 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 355 xhci->quirks |= XHCI_AMD_0x96_HOST; 356 357 /* AMD PLL quirk */ 358 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) 359 xhci->quirks |= XHCI_AMD_PLL_FIX; 360 361 if (pdev->vendor == PCI_VENDOR_ID_AMD && 362 (pdev->device == 0x145c || 363 pdev->device == 0x15e0 || 364 pdev->device == 0x15e1 || 365 pdev->device == 0x43bb)) 366 xhci->quirks |= XHCI_SUSPEND_DELAY; 367 368 if (pdev->vendor == PCI_VENDOR_ID_AMD && 369 (pdev->device == 0x15e0 || pdev->device == 0x15e1)) 370 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; 371 372 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) { 373 xhci->quirks |= XHCI_DISABLE_SPARSE; 374 xhci->quirks |= XHCI_RESET_ON_RESUME; 375 } 376 377 if (pdev->vendor == PCI_VENDOR_ID_AMD) 378 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 379 380 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 381 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 382 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 383 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 384 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 385 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 386 387 if (pdev->vendor == PCI_VENDOR_ID_AMD && 388 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) 389 xhci->quirks |= XHCI_BROKEN_D3COLD_S2I; 390 391 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 392 xhci->quirks |= XHCI_LPM_SUPPORT; 393 xhci->quirks |= XHCI_INTEL_HOST; 394 xhci->quirks |= XHCI_AVOID_BEI; 395 } 396 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 397 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 398 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 399 xhci->limit_active_eps = 64; 400 xhci->quirks |= XHCI_SW_BW_CHECKING; 401 /* 402 * PPT desktop boards DH77EB and DH77DF will power back on after 403 * a few seconds of being shutdown. The fix for this is to 404 * switch the ports from xHCI to EHCI on shutdown. We can't use 405 * DMI information to find those particular boards (since each 406 * vendor will change the board name), so we have to key off all 407 * PPT chipsets. 408 */ 409 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 410 } 411 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 412 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 413 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 414 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 415 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 416 } 417 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 418 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 419 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 420 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 421 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 422 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 423 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 424 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI || 425 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) { 426 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 427 } 428 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 429 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 430 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 431 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 432 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 433 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 434 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI)) 435 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 436 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 437 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 438 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 439 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 440 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 441 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) 442 xhci->quirks |= XHCI_MISSING_CAS; 443 444 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 445 (pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI || 446 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI)) 447 xhci->quirks |= XHCI_RESET_TO_DEFAULT; 448 449 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 450 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 451 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 452 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI || 453 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 454 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 455 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 456 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 457 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || 458 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI || 459 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI || 460 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI)) 461 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 462 463 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 464 pdev->device == PCI_DEVICE_ID_EJ168) { 465 xhci->quirks |= XHCI_RESET_ON_RESUME; 466 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 467 xhci->quirks |= XHCI_BROKEN_STREAMS; 468 } 469 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 470 pdev->device == PCI_DEVICE_ID_EJ188) { 471 xhci->quirks |= XHCI_RESET_ON_RESUME; 472 xhci->quirks |= XHCI_BROKEN_STREAMS; 473 } 474 475 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 476 pdev->device == 0x0014) { 477 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 478 xhci->quirks |= XHCI_ZERO_64B_REGS; 479 } 480 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 481 pdev->device == 0x0015) { 482 xhci->quirks |= XHCI_RESET_ON_RESUME; 483 xhci->quirks |= XHCI_ZERO_64B_REGS; 484 } 485 if (pdev->vendor == PCI_VENDOR_ID_VIA) 486 xhci->quirks |= XHCI_RESET_ON_RESUME; 487 488 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 489 if (pdev->vendor == PCI_VENDOR_ID_VIA && 490 pdev->device == 0x3432) 491 xhci->quirks |= XHCI_BROKEN_STREAMS; 492 493 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) 494 xhci->quirks |= XHCI_LPM_SUPPORT; 495 496 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 497 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) { 498 /* 499 * try to tame the ASMedia 1042 controller which reports 0.96 500 * but appears to behave more like 1.0 501 */ 502 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 503 xhci->quirks |= XHCI_BROKEN_STREAMS; 504 } 505 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 506 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) { 507 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 508 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 509 } 510 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 511 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI || 512 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI || 513 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI)) 514 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 515 516 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 517 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 518 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 519 520 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 521 pdev->device == PCI_DEVICE_ID_ASMEDIA_3042_XHCI) 522 xhci->quirks |= XHCI_RESET_ON_RESUME; 523 524 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 525 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 526 527 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 528 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 529 pdev->device == 0x9026) 530 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 531 532 if (pdev->vendor == PCI_VENDOR_ID_AMD && 533 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 || 534 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4)) 535 xhci->quirks |= XHCI_NO_SOFT_RETRY; 536 537 if (pdev->vendor == PCI_VENDOR_ID_ZHAOXIN) { 538 xhci->quirks |= XHCI_ZHAOXIN_HOST; 539 xhci->quirks |= XHCI_LPM_SUPPORT; 540 541 if (pdev->device == 0x9202) { 542 xhci->quirks |= XHCI_RESET_ON_RESUME; 543 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH; 544 } 545 546 if (pdev->device == 0x9203) 547 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH; 548 } 549 550 if (pdev->vendor == PCI_DEVICE_ID_CADENCE && 551 pdev->device == PCI_DEVICE_ID_CADENCE_SSP) 552 xhci->quirks |= XHCI_CDNS_SCTX_QUIRK; 553 554 /* xHC spec requires PCI devices to support D3hot and D3cold */ 555 if (xhci->hci_version >= 0x120) 556 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 557 558 if (xhci->quirks & XHCI_RESET_ON_RESUME) 559 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 560 "QUIRK: Resetting on resume"); 561 } 562 563 #ifdef CONFIG_ACPI 564 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 565 { 566 static const guid_t intel_dsm_guid = 567 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 568 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 569 union acpi_object *obj; 570 571 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 572 NULL); 573 ACPI_FREE(obj); 574 } 575 576 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) 577 { 578 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 579 struct xhci_hub *rhub = &xhci->usb3_rhub; 580 int ret; 581 int i; 582 583 /* This is not the usb3 roothub we are looking for */ 584 if (hcd != rhub->hcd) 585 return; 586 587 if (hdev->maxchild > rhub->num_ports) { 588 dev_err(&hdev->dev, "USB3 roothub port number mismatch\n"); 589 return; 590 } 591 592 for (i = 0; i < hdev->maxchild; i++) { 593 ret = usb_acpi_port_lpm_incapable(hdev, i); 594 595 dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret); 596 597 if (ret >= 0) { 598 rhub->ports[i]->lpm_incapable = ret; 599 continue; 600 } 601 } 602 } 603 604 #else 605 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 606 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { } 607 #endif /* CONFIG_ACPI */ 608 609 /* called during probe() after chip reset completes */ 610 static int xhci_pci_setup(struct usb_hcd *hcd) 611 { 612 struct xhci_hcd *xhci; 613 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 614 int retval; 615 616 xhci = hcd_to_xhci(hcd); 617 if (!xhci->sbrn) 618 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 619 620 /* imod_interval is the interrupt moderation value in nanoseconds. */ 621 xhci->imod_interval = 40000; 622 623 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 624 if (retval) 625 return retval; 626 627 if (!usb_hcd_is_primary_hcd(hcd)) 628 return 0; 629 630 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 631 xhci_pme_acpi_rtd3_enable(pdev); 632 633 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 634 635 /* Find any debug ports */ 636 return xhci_pci_reinit(xhci, pdev); 637 } 638 639 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 640 struct usb_tt *tt, gfp_t mem_flags) 641 { 642 /* Check if acpi claims some USB3 roothub ports are lpm incapable */ 643 if (!hdev->parent) 644 xhci_find_lpm_incapable_ports(hcd, hdev); 645 646 return xhci_update_hub_device(hcd, hdev, tt, mem_flags); 647 } 648 649 /* 650 * We need to register our own PCI probe function (instead of the USB core's 651 * function) in order to create a second roothub under xHCI. 652 */ 653 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 654 { 655 int retval; 656 struct xhci_hcd *xhci; 657 struct usb_hcd *hcd; 658 struct xhci_driver_data *driver_data; 659 struct reset_control *reset; 660 661 driver_data = (struct xhci_driver_data *)id->driver_data; 662 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) { 663 retval = renesas_xhci_check_request_fw(dev, id); 664 if (retval) 665 return retval; 666 } 667 668 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 669 if (IS_ERR(reset)) 670 return PTR_ERR(reset); 671 reset_control_reset(reset); 672 673 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 674 pm_runtime_get_noresume(&dev->dev); 675 676 /* Register the USB 2.0 roothub. 677 * FIXME: USB core must know to register the USB 2.0 roothub first. 678 * This is sort of silly, because we could just set the HCD driver flags 679 * to say USB 2.0, but I'm not sure what the implications would be in 680 * the other parts of the HCD code. 681 */ 682 retval = usb_hcd_pci_probe(dev, &xhci_pci_hc_driver); 683 684 if (retval) 685 goto put_runtime_pm; 686 687 /* USB 2.0 roothub is stored in the PCI device now. */ 688 hcd = dev_get_drvdata(&dev->dev); 689 xhci = hcd_to_xhci(hcd); 690 xhci->reset = reset; 691 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev, 692 pci_name(dev), hcd); 693 if (!xhci->shared_hcd) { 694 retval = -ENOMEM; 695 goto dealloc_usb2_hcd; 696 } 697 698 retval = xhci_ext_cap_init(xhci); 699 if (retval) 700 goto put_usb3_hcd; 701 702 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 703 IRQF_SHARED); 704 if (retval) 705 goto put_usb3_hcd; 706 /* Roothub already marked as USB 3.0 speed */ 707 708 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 709 HCC_MAX_PSA(xhci->hcc_params) >= 4) 710 xhci->shared_hcd->can_do_streams = 1; 711 712 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 713 pm_runtime_put_noidle(&dev->dev); 714 715 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0) 716 pm_runtime_get(&dev->dev); 717 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 718 pm_runtime_allow(&dev->dev); 719 720 dma_set_max_seg_size(&dev->dev, UINT_MAX); 721 722 return 0; 723 724 put_usb3_hcd: 725 usb_put_hcd(xhci->shared_hcd); 726 dealloc_usb2_hcd: 727 usb_hcd_pci_remove(dev); 728 put_runtime_pm: 729 pm_runtime_put_noidle(&dev->dev); 730 return retval; 731 } 732 733 static void xhci_pci_remove(struct pci_dev *dev) 734 { 735 struct xhci_hcd *xhci; 736 bool set_power_d3; 737 738 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 739 set_power_d3 = xhci->quirks & XHCI_SPURIOUS_WAKEUP; 740 741 xhci->xhc_state |= XHCI_STATE_REMOVING; 742 743 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0) 744 pm_runtime_put(&dev->dev); 745 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 746 pm_runtime_forbid(&dev->dev); 747 748 if (xhci->shared_hcd) { 749 usb_remove_hcd(xhci->shared_hcd); 750 usb_put_hcd(xhci->shared_hcd); 751 xhci->shared_hcd = NULL; 752 } 753 754 usb_hcd_pci_remove(dev); 755 756 /* Workaround for spurious wakeups at shutdown with HSW */ 757 if (set_power_d3) 758 pci_set_power_state(dev, PCI_D3hot); 759 } 760 761 /* 762 * In some Intel xHCI controllers, in order to get D3 working, 763 * through a vendor specific SSIC CONFIG register at offset 0x883c, 764 * SSIC PORT need to be marked as "unused" before putting xHCI 765 * into D3. After D3 exit, the SSIC port need to be marked as "used". 766 * Without this change, xHCI might not enter D3 state. 767 */ 768 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 769 { 770 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 771 u32 val; 772 void __iomem *reg; 773 int i; 774 775 for (i = 0; i < SSIC_PORT_NUM; i++) { 776 reg = (void __iomem *) xhci->cap_regs + 777 SSIC_PORT_CFG2 + 778 i * SSIC_PORT_CFG2_OFFSET; 779 780 /* Notify SSIC that SSIC profile programming is not done. */ 781 val = readl(reg) & ~PROG_DONE; 782 writel(val, reg); 783 784 /* Mark SSIC port as unused(suspend) or used(resume) */ 785 val = readl(reg); 786 if (suspend) 787 val |= SSIC_PORT_UNUSED; 788 else 789 val &= ~SSIC_PORT_UNUSED; 790 writel(val, reg); 791 792 /* Notify SSIC that SSIC profile programming is done */ 793 val = readl(reg) | PROG_DONE; 794 writel(val, reg); 795 readl(reg); 796 } 797 } 798 799 /* 800 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 801 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 802 */ 803 static void xhci_pme_quirk(struct usb_hcd *hcd) 804 { 805 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 806 void __iomem *reg; 807 u32 val; 808 809 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 810 val = readl(reg); 811 writel(val | BIT(28), reg); 812 readl(reg); 813 } 814 815 static void xhci_sparse_control_quirk(struct usb_hcd *hcd) 816 { 817 u32 reg; 818 819 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE); 820 reg &= ~BIT(SPARSE_DISABLE_BIT); 821 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE); 822 } 823 824 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 825 { 826 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 827 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 828 int ret; 829 830 /* 831 * Systems with the TI redriver that loses port status change events 832 * need to have the registers polled during D3, so avoid D3cold. 833 */ 834 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 835 pci_d3cold_disable(pdev); 836 837 #ifdef CONFIG_SUSPEND 838 /* d3cold is broken, but only when s2idle is used */ 839 if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE && 840 xhci->quirks & (XHCI_BROKEN_D3COLD_S2I)) 841 pci_d3cold_disable(pdev); 842 #endif 843 844 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 845 xhci_pme_quirk(hcd); 846 847 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 848 xhci_ssic_port_unused_quirk(hcd, true); 849 850 if (xhci->quirks & XHCI_DISABLE_SPARSE) 851 xhci_sparse_control_quirk(hcd); 852 853 ret = xhci_suspend(xhci, do_wakeup); 854 855 /* synchronize irq when using MSI-X */ 856 xhci_msix_sync_irqs(xhci); 857 858 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 859 xhci_ssic_port_unused_quirk(hcd, false); 860 861 return ret; 862 } 863 864 static int xhci_pci_resume(struct usb_hcd *hcd, pm_message_t msg) 865 { 866 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 867 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 868 int retval = 0; 869 870 reset_control_reset(xhci->reset); 871 872 /* The BIOS on systems with the Intel Panther Point chipset may or may 873 * not support xHCI natively. That means that during system resume, it 874 * may switch the ports back to EHCI so that users can use their 875 * keyboard to select a kernel from GRUB after resume from hibernate. 876 * 877 * The BIOS is supposed to remember whether the OS had xHCI ports 878 * enabled before resume, and switch the ports back to xHCI when the 879 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 880 * writers. 881 * 882 * Unconditionally switch the ports back to xHCI after a system resume. 883 * It should not matter whether the EHCI or xHCI controller is 884 * resumed first. It's enough to do the switchover in xHCI because 885 * USB core won't notice anything as the hub driver doesn't start 886 * running again until after all the devices (including both EHCI and 887 * xHCI host controllers) have been resumed. 888 */ 889 890 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 891 usb_enable_intel_xhci_ports(pdev); 892 893 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 894 xhci_ssic_port_unused_quirk(hcd, false); 895 896 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 897 xhci_pme_quirk(hcd); 898 899 retval = xhci_resume(xhci, msg); 900 return retval; 901 } 902 903 static int xhci_pci_poweroff_late(struct usb_hcd *hcd, bool do_wakeup) 904 { 905 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 906 struct xhci_port *port; 907 struct usb_device *udev; 908 unsigned int slot_id; 909 u32 portsc; 910 int i; 911 912 /* 913 * Systems with XHCI_RESET_TO_DEFAULT quirk have boot firmware that 914 * cause significant boot delay if usb ports are in suspended U3 state 915 * during boot. Some USB devices survive in U3 state over S4 hibernate 916 * 917 * Disable ports that are in U3 if remote wake is not enabled for either 918 * host controller or connected device 919 */ 920 921 if (!(xhci->quirks & XHCI_RESET_TO_DEFAULT)) 922 return 0; 923 924 for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) { 925 port = &xhci->hw_ports[i]; 926 portsc = readl(port->addr); 927 928 if ((portsc & PORT_PLS_MASK) != XDEV_U3) 929 continue; 930 931 slot_id = xhci_find_slot_id_by_port(port->rhub->hcd, xhci, 932 port->hcd_portnum + 1); 933 if (!slot_id || !xhci->devs[slot_id]) { 934 xhci_err(xhci, "No dev for slot_id %d for port %d-%d in U3\n", 935 slot_id, port->rhub->hcd->self.busnum, port->hcd_portnum + 1); 936 continue; 937 } 938 939 udev = xhci->devs[slot_id]->udev; 940 941 /* if wakeup is enabled then don't disable the port */ 942 if (udev->do_remote_wakeup && do_wakeup) 943 continue; 944 945 xhci_dbg(xhci, "port %d-%d in U3 without wakeup, disable it\n", 946 port->rhub->hcd->self.busnum, port->hcd_portnum + 1); 947 portsc = xhci_port_state_to_neutral(portsc); 948 writel(portsc | PORT_PE, port->addr); 949 } 950 951 return 0; 952 } 953 954 static void xhci_pci_shutdown(struct usb_hcd *hcd) 955 { 956 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 957 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 958 959 xhci_shutdown(hcd); 960 xhci_cleanup_msix(xhci); 961 962 /* Yet another workaround for spurious wakeups at shutdown with HSW */ 963 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 964 pci_set_power_state(pdev, PCI_D3hot); 965 } 966 967 /*-------------------------------------------------------------------------*/ 968 969 static const struct xhci_driver_data reneses_data = { 970 .quirks = XHCI_RENESAS_FW_QUIRK, 971 .firmware = "renesas_usb_fw.mem", 972 }; 973 974 /* PCI driver selection metadata; PCI hotplugging uses this */ 975 static const struct pci_device_id pci_ids[] = { 976 { PCI_DEVICE(0x1912, 0x0014), 977 .driver_data = (unsigned long)&reneses_data, 978 }, 979 { PCI_DEVICE(0x1912, 0x0015), 980 .driver_data = (unsigned long)&reneses_data, 981 }, 982 /* handle any USB 3.0 xHCI controller */ 983 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 984 }, 985 { /* end: all zeroes */ } 986 }; 987 MODULE_DEVICE_TABLE(pci, pci_ids); 988 989 /* 990 * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't 991 * load firmware, so don't encumber the xhci-pci driver with it. 992 */ 993 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS) 994 MODULE_FIRMWARE("renesas_usb_fw.mem"); 995 #endif 996 997 /* pci driver glue; this is a "new style" PCI driver module */ 998 static struct pci_driver xhci_pci_driver = { 999 .name = hcd_name, 1000 .id_table = pci_ids, 1001 1002 .probe = xhci_pci_probe, 1003 .remove = xhci_pci_remove, 1004 /* suspend and resume implemented later */ 1005 1006 .shutdown = usb_hcd_pci_shutdown, 1007 .driver = { 1008 .pm = pm_ptr(&usb_hcd_pci_pm_ops), 1009 }, 1010 }; 1011 1012 static int __init xhci_pci_init(void) 1013 { 1014 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 1015 xhci_pci_hc_driver.pci_suspend = pm_ptr(xhci_pci_suspend); 1016 xhci_pci_hc_driver.pci_resume = pm_ptr(xhci_pci_resume); 1017 xhci_pci_hc_driver.pci_poweroff_late = pm_ptr(xhci_pci_poweroff_late); 1018 xhci_pci_hc_driver.shutdown = pm_ptr(xhci_pci_shutdown); 1019 xhci_pci_hc_driver.stop = xhci_pci_stop; 1020 return pci_register_driver(&xhci_pci_driver); 1021 } 1022 module_init(xhci_pci_init); 1023 1024 static void __exit xhci_pci_exit(void) 1025 { 1026 pci_unregister_driver(&xhci_pci_driver); 1027 } 1028 module_exit(xhci_pci_exit); 1029 1030 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 1031 MODULE_LICENSE("GPL"); 1032