1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * xHCI host controller driver PCI Bus Glue.
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11 #include <linux/pci.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/acpi.h>
15 #include <linux/reset.h>
16 #include <linux/suspend.h>
17
18 #include "xhci.h"
19 #include "xhci-trace.h"
20 #include "xhci-pci.h"
21
22 #define SSIC_PORT_NUM 2
23 #define SSIC_PORT_CFG2 0x880c
24 #define SSIC_PORT_CFG2_OFFSET 0x30
25 #define PROG_DONE (1 << 30)
26 #define SSIC_PORT_UNUSED (1 << 31)
27 #define SPARSE_DISABLE_BIT 17
28 #define SPARSE_CNTL_ENABLE 0xC12C
29
30 /* Device for a quirk */
31 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
32 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100
35 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
36
37 #define PCI_VENDOR_ID_ETRON 0x1b6f
38 #define PCI_DEVICE_ID_EJ168 0x7023
39 #define PCI_DEVICE_ID_EJ188 0x7052
40
41 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
42 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
43 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
44 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
45 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
46 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
47 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
48 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
49 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
50 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5
52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6
53 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1
54 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db
55 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4
56 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9
57 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec
58 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0
59 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13
60 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af
61 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13
62 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138
63 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed
64 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI 0x54ed
65
66 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639
67 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
68 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
69 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
70 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
71
72 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042
73 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
74 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242
75 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142
76 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242
77
78 static const char hcd_name[] = "xhci_hcd";
79
80 static struct hc_driver __read_mostly xhci_pci_hc_driver;
81
82 static int xhci_pci_setup(struct usb_hcd *hcd);
83 static int xhci_pci_run(struct usb_hcd *hcd);
84 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
85 struct usb_tt *tt, gfp_t mem_flags);
86
87 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
88 .reset = xhci_pci_setup,
89 .start = xhci_pci_run,
90 .update_hub_device = xhci_pci_update_hub_device,
91 };
92
xhci_msix_sync_irqs(struct xhci_hcd * xhci)93 static void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
94 {
95 struct usb_hcd *hcd = xhci_to_hcd(xhci);
96
97 if (hcd->msix_enabled) {
98 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
99 int i;
100
101 for (i = 0; i < xhci->msix_count; i++)
102 synchronize_irq(pci_irq_vector(pdev, i));
103 }
104 }
105
106 /* Free any IRQs and disable MSI-X */
xhci_cleanup_msix(struct xhci_hcd * xhci)107 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
108 {
109 struct usb_hcd *hcd = xhci_to_hcd(xhci);
110 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
111
112 /* return if using legacy interrupt */
113 if (hcd->irq > 0)
114 return;
115
116 if (hcd->msix_enabled) {
117 int i;
118
119 for (i = 0; i < xhci->msix_count; i++)
120 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
121 } else {
122 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
123 }
124
125 pci_free_irq_vectors(pdev);
126 hcd->msix_enabled = 0;
127 }
128
129 /*
130 * Set up MSI
131 */
xhci_setup_msi(struct xhci_hcd * xhci)132 static int xhci_setup_msi(struct xhci_hcd *xhci)
133 {
134 int ret;
135 /*
136 * TODO:Check with MSI Soc for sysdev
137 */
138 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
139
140 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
141 if (ret < 0) {
142 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
143 "failed to allocate MSI entry");
144 return ret;
145 }
146
147 ret = request_irq(pdev->irq, xhci_msi_irq,
148 0, "xhci_hcd", xhci_to_hcd(xhci));
149 if (ret) {
150 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
151 "disable MSI interrupt");
152 pci_free_irq_vectors(pdev);
153 }
154
155 return ret;
156 }
157
158 /*
159 * Set up MSI-X
160 */
xhci_setup_msix(struct xhci_hcd * xhci)161 static int xhci_setup_msix(struct xhci_hcd *xhci)
162 {
163 int i, ret;
164 struct usb_hcd *hcd = xhci_to_hcd(xhci);
165 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
166
167 /*
168 * calculate number of msi-x vectors supported.
169 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
170 * with max number of interrupters based on the xhci HCSPARAMS1.
171 * - num_online_cpus: maximum msi-x vectors per CPUs core.
172 * Add additional 1 vector to ensure always available interrupt.
173 */
174 xhci->msix_count = min(num_online_cpus() + 1,
175 HCS_MAX_INTRS(xhci->hcs_params1));
176
177 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
178 PCI_IRQ_MSIX);
179 if (ret < 0) {
180 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
181 "Failed to enable MSI-X");
182 return ret;
183 }
184
185 for (i = 0; i < xhci->msix_count; i++) {
186 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
187 "xhci_hcd", xhci_to_hcd(xhci));
188 if (ret)
189 goto disable_msix;
190 }
191
192 hcd->msix_enabled = 1;
193 return ret;
194
195 disable_msix:
196 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
197 while (--i >= 0)
198 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
199 pci_free_irq_vectors(pdev);
200 return ret;
201 }
202
xhci_try_enable_msi(struct usb_hcd * hcd)203 static int xhci_try_enable_msi(struct usb_hcd *hcd)
204 {
205 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
206 struct pci_dev *pdev;
207 int ret;
208
209 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
210 /*
211 * Some Fresco Logic host controllers advertise MSI, but fail to
212 * generate interrupts. Don't even try to enable MSI.
213 */
214 if (xhci->quirks & XHCI_BROKEN_MSI)
215 goto legacy_irq;
216
217 /* unregister the legacy interrupt */
218 if (hcd->irq)
219 free_irq(hcd->irq, hcd);
220 hcd->irq = 0;
221
222 ret = xhci_setup_msix(xhci);
223 if (ret)
224 /* fall back to msi*/
225 ret = xhci_setup_msi(xhci);
226
227 if (!ret) {
228 hcd->msi_enabled = 1;
229 return 0;
230 }
231
232 if (!pdev->irq) {
233 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
234 return -EINVAL;
235 }
236
237 legacy_irq:
238 if (!strlen(hcd->irq_descr))
239 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
240 hcd->driver->description, hcd->self.busnum);
241
242 /* fall back to legacy interrupt*/
243 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
244 hcd->irq_descr, hcd);
245 if (ret) {
246 xhci_err(xhci, "request interrupt %d failed\n",
247 pdev->irq);
248 return ret;
249 }
250 hcd->irq = pdev->irq;
251 return 0;
252 }
253
xhci_pci_run(struct usb_hcd * hcd)254 static int xhci_pci_run(struct usb_hcd *hcd)
255 {
256 int ret;
257
258 if (usb_hcd_is_primary_hcd(hcd)) {
259 ret = xhci_try_enable_msi(hcd);
260 if (ret)
261 return ret;
262 }
263
264 return xhci_run(hcd);
265 }
266
xhci_pci_stop(struct usb_hcd * hcd)267 static void xhci_pci_stop(struct usb_hcd *hcd)
268 {
269 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
270
271 xhci_stop(hcd);
272
273 if (usb_hcd_is_primary_hcd(hcd))
274 xhci_cleanup_msix(xhci);
275 }
276
277 /* called after powerup, by probe or system-pm "wakeup" */
xhci_pci_reinit(struct xhci_hcd * xhci,struct pci_dev * pdev)278 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
279 {
280 /*
281 * TODO: Implement finding debug ports later.
282 * TODO: see if there are any quirks that need to be added to handle
283 * new extended capabilities.
284 */
285
286 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
287 if (!pci_set_mwi(pdev))
288 xhci_dbg(xhci, "MWI active\n");
289
290 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
291 return 0;
292 }
293
xhci_pci_quirks(struct device * dev,struct xhci_hcd * xhci)294 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
295 {
296 struct pci_dev *pdev = to_pci_dev(dev);
297 struct xhci_driver_data *driver_data;
298 const struct pci_device_id *id;
299
300 id = pci_match_id(to_pci_driver(pdev->dev.driver)->id_table, pdev);
301
302 if (id && id->driver_data) {
303 driver_data = (struct xhci_driver_data *)id->driver_data;
304 xhci->quirks |= driver_data->quirks;
305 }
306
307 /* Look for vendor-specific quirks */
308 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
309 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
310 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
311 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
312 pdev->revision == 0x0) {
313 xhci->quirks |= XHCI_RESET_EP_QUIRK;
314 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
315 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated");
316 }
317 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
318 pdev->revision == 0x4) {
319 xhci->quirks |= XHCI_SLOW_SUSPEND;
320 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
321 "QUIRK: Fresco Logic xHC revision %u"
322 "must be suspended extra slowly",
323 pdev->revision);
324 }
325 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
326 xhci->quirks |= XHCI_BROKEN_STREAMS;
327 /* Fresco Logic confirms: all revisions of this chip do not
328 * support MSI, even though some of them claim to in their PCI
329 * capabilities.
330 */
331 xhci->quirks |= XHCI_BROKEN_MSI;
332 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
333 "QUIRK: Fresco Logic revision %u "
334 "has broken MSI implementation",
335 pdev->revision);
336 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
337 }
338
339 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
340 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
341 xhci->quirks |= XHCI_BROKEN_STREAMS;
342
343 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
344 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100)
345 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
346
347 if (pdev->vendor == PCI_VENDOR_ID_NEC)
348 xhci->quirks |= XHCI_NEC_HOST;
349
350 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
351 xhci->quirks |= XHCI_AMD_0x96_HOST;
352
353 /* AMD PLL quirk */
354 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
355 xhci->quirks |= XHCI_AMD_PLL_FIX;
356
357 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
358 (pdev->device == 0x145c ||
359 pdev->device == 0x15e0 ||
360 pdev->device == 0x15e1 ||
361 pdev->device == 0x43bb))
362 xhci->quirks |= XHCI_SUSPEND_DELAY;
363
364 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
365 (pdev->device == 0x15e0 || pdev->device == 0x15e1))
366 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
367
368 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
369 xhci->quirks |= XHCI_DISABLE_SPARSE;
370 xhci->quirks |= XHCI_RESET_ON_RESUME;
371 }
372
373 if (pdev->vendor == PCI_VENDOR_ID_AMD)
374 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
375
376 if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
377 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
378 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
379 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
380 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
381 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
382
383 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
384 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI)
385 xhci->quirks |= XHCI_BROKEN_D3COLD_S2I;
386
387 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
388 xhci->quirks |= XHCI_LPM_SUPPORT;
389 xhci->quirks |= XHCI_INTEL_HOST;
390 xhci->quirks |= XHCI_AVOID_BEI;
391 }
392 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
393 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
394 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
395 xhci->limit_active_eps = 64;
396 xhci->quirks |= XHCI_SW_BW_CHECKING;
397 /*
398 * PPT desktop boards DH77EB and DH77DF will power back on after
399 * a few seconds of being shutdown. The fix for this is to
400 * switch the ports from xHCI to EHCI on shutdown. We can't use
401 * DMI information to find those particular boards (since each
402 * vendor will change the board name), so we have to key off all
403 * PPT chipsets.
404 */
405 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
406 }
407 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
408 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
409 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
410 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
411 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
412 }
413 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
414 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
415 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
416 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
417 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
418 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
419 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
420 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
421 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
422 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
423 }
424 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
425 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
426 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
427 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
428 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
429 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
430 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
431 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
432 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
433 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
434 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
435 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
436 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
437 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
438 xhci->quirks |= XHCI_MISSING_CAS;
439
440 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
441 (pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI ||
442 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI))
443 xhci->quirks |= XHCI_RESET_TO_DEFAULT;
444
445 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
446 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
447 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
448 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
449 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
450 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
451 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
452 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
453 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
454 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
455 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
456 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI))
457 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
458
459 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
460 pdev->device == PCI_DEVICE_ID_EJ168) {
461 xhci->quirks |= XHCI_RESET_ON_RESUME;
462 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
463 xhci->quirks |= XHCI_BROKEN_STREAMS;
464 }
465 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
466 pdev->device == PCI_DEVICE_ID_EJ188) {
467 xhci->quirks |= XHCI_RESET_ON_RESUME;
468 xhci->quirks |= XHCI_BROKEN_STREAMS;
469 }
470
471 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
472 pdev->device == 0x0014) {
473 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
474 xhci->quirks |= XHCI_ZERO_64B_REGS;
475 }
476 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
477 pdev->device == 0x0015) {
478 xhci->quirks |= XHCI_RESET_ON_RESUME;
479 xhci->quirks |= XHCI_ZERO_64B_REGS;
480 }
481 if (pdev->vendor == PCI_VENDOR_ID_VIA)
482 xhci->quirks |= XHCI_RESET_ON_RESUME;
483
484 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
485 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
486 pdev->device == 0x3432)
487 xhci->quirks |= XHCI_BROKEN_STREAMS;
488
489 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483)
490 xhci->quirks |= XHCI_LPM_SUPPORT;
491
492 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
493 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) {
494 /*
495 * try to tame the ASMedia 1042 controller which reports 0.96
496 * but appears to behave more like 1.0
497 */
498 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
499 xhci->quirks |= XHCI_BROKEN_STREAMS;
500 }
501 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
502 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
503 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
504 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
505 }
506 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
507 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
508 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
509 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
510 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
511
512 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
513 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
514 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
515
516 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
517 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
518
519 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
520 pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
521 pdev->device == 0x9026)
522 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
523
524 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
525 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
526 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
527 xhci->quirks |= XHCI_NO_SOFT_RETRY;
528
529 if (pdev->vendor == PCI_VENDOR_ID_ZHAOXIN) {
530 xhci->quirks |= XHCI_ZHAOXIN_HOST;
531 xhci->quirks |= XHCI_LPM_SUPPORT;
532
533 if (pdev->device == 0x9202) {
534 xhci->quirks |= XHCI_RESET_ON_RESUME;
535 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH;
536 }
537
538 if (pdev->device == 0x9203)
539 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH;
540 }
541
542 /* xHC spec requires PCI devices to support D3hot and D3cold */
543 if (xhci->hci_version >= 0x120)
544 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
545
546 if (xhci->quirks & XHCI_RESET_ON_RESUME)
547 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
548 "QUIRK: Resetting on resume");
549 }
550
551 #ifdef CONFIG_ACPI
xhci_pme_acpi_rtd3_enable(struct pci_dev * dev)552 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
553 {
554 static const guid_t intel_dsm_guid =
555 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
556 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
557 union acpi_object *obj;
558
559 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
560 NULL);
561 ACPI_FREE(obj);
562 }
563
xhci_find_lpm_incapable_ports(struct usb_hcd * hcd,struct usb_device * hdev)564 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev)
565 {
566 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
567 struct xhci_hub *rhub = &xhci->usb3_rhub;
568 int ret;
569 int i;
570
571 /* This is not the usb3 roothub we are looking for */
572 if (hcd != rhub->hcd)
573 return;
574
575 if (hdev->maxchild > rhub->num_ports) {
576 dev_err(&hdev->dev, "USB3 roothub port number mismatch\n");
577 return;
578 }
579
580 for (i = 0; i < hdev->maxchild; i++) {
581 ret = usb_acpi_port_lpm_incapable(hdev, i);
582
583 dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret);
584
585 if (ret >= 0) {
586 rhub->ports[i]->lpm_incapable = ret;
587 continue;
588 }
589 }
590 }
591
592 #else
xhci_pme_acpi_rtd3_enable(struct pci_dev * dev)593 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
xhci_find_lpm_incapable_ports(struct usb_hcd * hcd,struct usb_device * hdev)594 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { }
595 #endif /* CONFIG_ACPI */
596
597 /* called during probe() after chip reset completes */
xhci_pci_setup(struct usb_hcd * hcd)598 static int xhci_pci_setup(struct usb_hcd *hcd)
599 {
600 struct xhci_hcd *xhci;
601 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
602 int retval;
603
604 xhci = hcd_to_xhci(hcd);
605 if (!xhci->sbrn)
606 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
607
608 /* imod_interval is the interrupt moderation value in nanoseconds. */
609 xhci->imod_interval = 40000;
610
611 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
612 if (retval)
613 return retval;
614
615 if (!usb_hcd_is_primary_hcd(hcd))
616 return 0;
617
618 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
619 xhci_pme_acpi_rtd3_enable(pdev);
620
621 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
622
623 /* Find any debug ports */
624 return xhci_pci_reinit(xhci, pdev);
625 }
626
xhci_pci_update_hub_device(struct usb_hcd * hcd,struct usb_device * hdev,struct usb_tt * tt,gfp_t mem_flags)627 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
628 struct usb_tt *tt, gfp_t mem_flags)
629 {
630 /* Check if acpi claims some USB3 roothub ports are lpm incapable */
631 if (!hdev->parent)
632 xhci_find_lpm_incapable_ports(hcd, hdev);
633
634 return xhci_update_hub_device(hcd, hdev, tt, mem_flags);
635 }
636
637 /*
638 * We need to register our own PCI probe function (instead of the USB core's
639 * function) in order to create a second roothub under xHCI.
640 */
xhci_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)641 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
642 {
643 int retval;
644 struct xhci_hcd *xhci;
645 struct usb_hcd *hcd;
646 struct xhci_driver_data *driver_data;
647 struct reset_control *reset;
648
649 driver_data = (struct xhci_driver_data *)id->driver_data;
650 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
651 retval = renesas_xhci_check_request_fw(dev, id);
652 if (retval)
653 return retval;
654 }
655
656 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
657 if (IS_ERR(reset))
658 return PTR_ERR(reset);
659 reset_control_reset(reset);
660
661 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
662 pm_runtime_get_noresume(&dev->dev);
663
664 /* Register the USB 2.0 roothub.
665 * FIXME: USB core must know to register the USB 2.0 roothub first.
666 * This is sort of silly, because we could just set the HCD driver flags
667 * to say USB 2.0, but I'm not sure what the implications would be in
668 * the other parts of the HCD code.
669 */
670 retval = usb_hcd_pci_probe(dev, &xhci_pci_hc_driver);
671
672 if (retval)
673 goto put_runtime_pm;
674
675 /* USB 2.0 roothub is stored in the PCI device now. */
676 hcd = dev_get_drvdata(&dev->dev);
677 xhci = hcd_to_xhci(hcd);
678 xhci->reset = reset;
679 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
680 pci_name(dev), hcd);
681 if (!xhci->shared_hcd) {
682 retval = -ENOMEM;
683 goto dealloc_usb2_hcd;
684 }
685
686 retval = xhci_ext_cap_init(xhci);
687 if (retval)
688 goto put_usb3_hcd;
689
690 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
691 IRQF_SHARED);
692 if (retval)
693 goto put_usb3_hcd;
694 /* Roothub already marked as USB 3.0 speed */
695
696 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
697 HCC_MAX_PSA(xhci->hcc_params) >= 4)
698 xhci->shared_hcd->can_do_streams = 1;
699
700 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
701 pm_runtime_put_noidle(&dev->dev);
702
703 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0)
704 pm_runtime_forbid(&dev->dev);
705 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
706 pm_runtime_allow(&dev->dev);
707
708 dma_set_max_seg_size(&dev->dev, UINT_MAX);
709
710 return 0;
711
712 put_usb3_hcd:
713 usb_put_hcd(xhci->shared_hcd);
714 dealloc_usb2_hcd:
715 usb_hcd_pci_remove(dev);
716 put_runtime_pm:
717 pm_runtime_put_noidle(&dev->dev);
718 return retval;
719 }
720
xhci_pci_remove(struct pci_dev * dev)721 static void xhci_pci_remove(struct pci_dev *dev)
722 {
723 struct xhci_hcd *xhci;
724
725 xhci = hcd_to_xhci(pci_get_drvdata(dev));
726
727 xhci->xhc_state |= XHCI_STATE_REMOVING;
728
729 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
730 pm_runtime_forbid(&dev->dev);
731
732 if (xhci->shared_hcd) {
733 usb_remove_hcd(xhci->shared_hcd);
734 usb_put_hcd(xhci->shared_hcd);
735 xhci->shared_hcd = NULL;
736 }
737
738 /* Workaround for spurious wakeups at shutdown with HSW */
739 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
740 pci_set_power_state(dev, PCI_D3hot);
741
742 usb_hcd_pci_remove(dev);
743 }
744
745 /*
746 * In some Intel xHCI controllers, in order to get D3 working,
747 * through a vendor specific SSIC CONFIG register at offset 0x883c,
748 * SSIC PORT need to be marked as "unused" before putting xHCI
749 * into D3. After D3 exit, the SSIC port need to be marked as "used".
750 * Without this change, xHCI might not enter D3 state.
751 */
xhci_ssic_port_unused_quirk(struct usb_hcd * hcd,bool suspend)752 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
753 {
754 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
755 u32 val;
756 void __iomem *reg;
757 int i;
758
759 for (i = 0; i < SSIC_PORT_NUM; i++) {
760 reg = (void __iomem *) xhci->cap_regs +
761 SSIC_PORT_CFG2 +
762 i * SSIC_PORT_CFG2_OFFSET;
763
764 /* Notify SSIC that SSIC profile programming is not done. */
765 val = readl(reg) & ~PROG_DONE;
766 writel(val, reg);
767
768 /* Mark SSIC port as unused(suspend) or used(resume) */
769 val = readl(reg);
770 if (suspend)
771 val |= SSIC_PORT_UNUSED;
772 else
773 val &= ~SSIC_PORT_UNUSED;
774 writel(val, reg);
775
776 /* Notify SSIC that SSIC profile programming is done */
777 val = readl(reg) | PROG_DONE;
778 writel(val, reg);
779 readl(reg);
780 }
781 }
782
783 /*
784 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
785 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
786 */
xhci_pme_quirk(struct usb_hcd * hcd)787 static void xhci_pme_quirk(struct usb_hcd *hcd)
788 {
789 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
790 void __iomem *reg;
791 u32 val;
792
793 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
794 val = readl(reg);
795 writel(val | BIT(28), reg);
796 readl(reg);
797 }
798
xhci_sparse_control_quirk(struct usb_hcd * hcd)799 static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
800 {
801 u32 reg;
802
803 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
804 reg &= ~BIT(SPARSE_DISABLE_BIT);
805 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
806 }
807
xhci_pci_suspend(struct usb_hcd * hcd,bool do_wakeup)808 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
809 {
810 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
811 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
812 int ret;
813
814 /*
815 * Systems with the TI redriver that loses port status change events
816 * need to have the registers polled during D3, so avoid D3cold.
817 */
818 if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
819 pci_d3cold_disable(pdev);
820
821 #ifdef CONFIG_SUSPEND
822 /* d3cold is broken, but only when s2idle is used */
823 if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE &&
824 xhci->quirks & (XHCI_BROKEN_D3COLD_S2I))
825 pci_d3cold_disable(pdev);
826 #endif
827
828 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
829 xhci_pme_quirk(hcd);
830
831 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
832 xhci_ssic_port_unused_quirk(hcd, true);
833
834 if (xhci->quirks & XHCI_DISABLE_SPARSE)
835 xhci_sparse_control_quirk(hcd);
836
837 ret = xhci_suspend(xhci, do_wakeup);
838
839 /* synchronize irq when using MSI-X */
840 xhci_msix_sync_irqs(xhci);
841
842 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
843 xhci_ssic_port_unused_quirk(hcd, false);
844
845 return ret;
846 }
847
xhci_pci_resume(struct usb_hcd * hcd,pm_message_t msg)848 static int xhci_pci_resume(struct usb_hcd *hcd, pm_message_t msg)
849 {
850 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
851 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
852 int retval = 0;
853
854 reset_control_reset(xhci->reset);
855
856 /* The BIOS on systems with the Intel Panther Point chipset may or may
857 * not support xHCI natively. That means that during system resume, it
858 * may switch the ports back to EHCI so that users can use their
859 * keyboard to select a kernel from GRUB after resume from hibernate.
860 *
861 * The BIOS is supposed to remember whether the OS had xHCI ports
862 * enabled before resume, and switch the ports back to xHCI when the
863 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
864 * writers.
865 *
866 * Unconditionally switch the ports back to xHCI after a system resume.
867 * It should not matter whether the EHCI or xHCI controller is
868 * resumed first. It's enough to do the switchover in xHCI because
869 * USB core won't notice anything as the hub driver doesn't start
870 * running again until after all the devices (including both EHCI and
871 * xHCI host controllers) have been resumed.
872 */
873
874 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
875 usb_enable_intel_xhci_ports(pdev);
876
877 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
878 xhci_ssic_port_unused_quirk(hcd, false);
879
880 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
881 xhci_pme_quirk(hcd);
882
883 retval = xhci_resume(xhci, msg);
884 return retval;
885 }
886
xhci_pci_poweroff_late(struct usb_hcd * hcd,bool do_wakeup)887 static int xhci_pci_poweroff_late(struct usb_hcd *hcd, bool do_wakeup)
888 {
889 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
890 struct xhci_port *port;
891 struct usb_device *udev;
892 unsigned int slot_id;
893 u32 portsc;
894 int i;
895
896 /*
897 * Systems with XHCI_RESET_TO_DEFAULT quirk have boot firmware that
898 * cause significant boot delay if usb ports are in suspended U3 state
899 * during boot. Some USB devices survive in U3 state over S4 hibernate
900 *
901 * Disable ports that are in U3 if remote wake is not enabled for either
902 * host controller or connected device
903 */
904
905 if (!(xhci->quirks & XHCI_RESET_TO_DEFAULT))
906 return 0;
907
908 for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
909 port = &xhci->hw_ports[i];
910 portsc = readl(port->addr);
911
912 if ((portsc & PORT_PLS_MASK) != XDEV_U3)
913 continue;
914
915 slot_id = xhci_find_slot_id_by_port(port->rhub->hcd, xhci,
916 port->hcd_portnum + 1);
917 if (!slot_id || !xhci->devs[slot_id]) {
918 xhci_err(xhci, "No dev for slot_id %d for port %d-%d in U3\n",
919 slot_id, port->rhub->hcd->self.busnum, port->hcd_portnum + 1);
920 continue;
921 }
922
923 udev = xhci->devs[slot_id]->udev;
924
925 /* if wakeup is enabled then don't disable the port */
926 if (udev->do_remote_wakeup && do_wakeup)
927 continue;
928
929 xhci_dbg(xhci, "port %d-%d in U3 without wakeup, disable it\n",
930 port->rhub->hcd->self.busnum, port->hcd_portnum + 1);
931 portsc = xhci_port_state_to_neutral(portsc);
932 writel(portsc | PORT_PE, port->addr);
933 }
934
935 return 0;
936 }
937
xhci_pci_shutdown(struct usb_hcd * hcd)938 static void xhci_pci_shutdown(struct usb_hcd *hcd)
939 {
940 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
941 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
942
943 xhci_shutdown(hcd);
944 xhci_cleanup_msix(xhci);
945
946 /* Yet another workaround for spurious wakeups at shutdown with HSW */
947 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
948 pci_set_power_state(pdev, PCI_D3hot);
949 }
950
951 /*-------------------------------------------------------------------------*/
952
953 static const struct xhci_driver_data reneses_data = {
954 .quirks = XHCI_RENESAS_FW_QUIRK,
955 .firmware = "renesas_usb_fw.mem",
956 };
957
958 /* PCI driver selection metadata; PCI hotplugging uses this */
959 static const struct pci_device_id pci_ids[] = {
960 { PCI_DEVICE(0x1912, 0x0014),
961 .driver_data = (unsigned long)&reneses_data,
962 },
963 { PCI_DEVICE(0x1912, 0x0015),
964 .driver_data = (unsigned long)&reneses_data,
965 },
966 /* handle any USB 3.0 xHCI controller */
967 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
968 },
969 { /* end: all zeroes */ }
970 };
971 MODULE_DEVICE_TABLE(pci, pci_ids);
972
973 /*
974 * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't
975 * load firmware, so don't encumber the xhci-pci driver with it.
976 */
977 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS)
978 MODULE_FIRMWARE("renesas_usb_fw.mem");
979 #endif
980
981 /* pci driver glue; this is a "new style" PCI driver module */
982 static struct pci_driver xhci_pci_driver = {
983 .name = hcd_name,
984 .id_table = pci_ids,
985
986 .probe = xhci_pci_probe,
987 .remove = xhci_pci_remove,
988 /* suspend and resume implemented later */
989
990 .shutdown = usb_hcd_pci_shutdown,
991 .driver = {
992 .pm = pm_ptr(&usb_hcd_pci_pm_ops),
993 },
994 };
995
xhci_pci_init(void)996 static int __init xhci_pci_init(void)
997 {
998 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
999 xhci_pci_hc_driver.pci_suspend = pm_ptr(xhci_pci_suspend);
1000 xhci_pci_hc_driver.pci_resume = pm_ptr(xhci_pci_resume);
1001 xhci_pci_hc_driver.pci_poweroff_late = pm_ptr(xhci_pci_poweroff_late);
1002 xhci_pci_hc_driver.shutdown = pm_ptr(xhci_pci_shutdown);
1003 xhci_pci_hc_driver.stop = xhci_pci_stop;
1004 return pci_register_driver(&xhci_pci_driver);
1005 }
1006 module_init(xhci_pci_init);
1007
xhci_pci_exit(void)1008 static void __exit xhci_pci_exit(void)
1009 {
1010 pci_unregister_driver(&xhci_pci_driver);
1011 }
1012 module_exit(xhci_pci_exit);
1013
1014 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
1015 MODULE_LICENSE("GPL");
1016