1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: 5 * Zhigang.Wei <zhigang.wei@mediatek.com> 6 * Chunfeng.Yun <chunfeng.yun@mediatek.com> 7 */ 8 9 #ifndef _XHCI_MTK_H_ 10 #define _XHCI_MTK_H_ 11 12 #include <linux/clk.h> 13 14 #include "xhci.h" 15 16 #define BULK_CLKS_NUM 5 17 18 /** 19 * To simplify scheduler algorithm, set a upper limit for ESIT, 20 * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT, 21 * round down to the limit value, that means allocating more 22 * bandwidth to it. 23 */ 24 #define XHCI_MTK_MAX_ESIT 64 25 26 /** 27 * @fs_bus_bw: array to keep track of bandwidth already used for FS 28 * @ep_list: Endpoints using this TT 29 */ 30 struct mu3h_sch_tt { 31 u32 fs_bus_bw[XHCI_MTK_MAX_ESIT]; 32 struct list_head ep_list; 33 }; 34 35 /** 36 * struct mu3h_sch_bw_info: schedule information for bandwidth domain 37 * 38 * @bus_bw: array to keep track of bandwidth already used at each uframes 39 * @bw_ep_list: eps in the bandwidth domain 40 * 41 * treat a HS root port as a bandwidth domain, but treat a SS root port as 42 * two bandwidth domains, one for IN eps and another for OUT eps. 43 */ 44 struct mu3h_sch_bw_info { 45 u32 bus_bw[XHCI_MTK_MAX_ESIT]; 46 struct list_head bw_ep_list; 47 }; 48 49 /** 50 * struct mu3h_sch_ep_info: schedule information for endpoint 51 * 52 * @esit: unit is 125us, equal to 2 << Interval field in ep-context 53 * @num_budget_microframes: number of continuous uframes 54 * (@repeat==1) scheduled within the interval 55 * @bw_cost_per_microframe: bandwidth cost per microframe 56 * @endpoint: linked into bandwidth domain which it belongs to 57 * @tt_endpoint: linked into mu3h_sch_tt's list which it belongs to 58 * @sch_tt: mu3h_sch_tt linked into 59 * @ep_type: endpoint type 60 * @maxpkt: max packet size of endpoint 61 * @ep: address of usb_host_endpoint struct 62 * @allocated: the bandwidth is aready allocated from bus_bw 63 * @offset: which uframe of the interval that transfer should be 64 * scheduled first time within the interval 65 * @repeat: the time gap between two uframes that transfers are 66 * scheduled within a interval. in the simple algorithm, only 67 * assign 0 or 1 to it; 0 means using only one uframe in a 68 * interval, and 1 means using @num_budget_microframes 69 * continuous uframes 70 * @pkts: number of packets to be transferred in the scheduled uframes 71 * @cs_count: number of CS that host will trigger 72 * @burst_mode: burst mode for scheduling. 0: normal burst mode, 73 * distribute the bMaxBurst+1 packets for a single burst 74 * according to @pkts and @repeat, repeate the burst multiple 75 * times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets 76 * according to @pkts and @repeat. normal mode is used by 77 * default 78 * @bw_budget_table: table to record bandwidth budget per microframe 79 */ 80 struct mu3h_sch_ep_info { 81 u32 esit; 82 u32 num_budget_microframes; 83 u32 bw_cost_per_microframe; 84 struct list_head endpoint; 85 struct list_head tt_endpoint; 86 struct mu3h_sch_tt *sch_tt; 87 u32 ep_type; 88 u32 maxpkt; 89 struct usb_host_endpoint *ep; 90 enum usb_device_speed speed; 91 bool allocated; 92 /* 93 * mtk xHCI scheduling information put into reserved DWs 94 * in ep context 95 */ 96 u32 offset; 97 u32 repeat; 98 u32 pkts; 99 u32 cs_count; 100 u32 burst_mode; 101 u32 bw_budget_table[]; 102 }; 103 104 #define MU3C_U3_PORT_MAX 4 105 #define MU3C_U2_PORT_MAX 5 106 107 /** 108 * struct mu3c_ippc_regs: MTK ssusb ip port control registers 109 * @ip_pw_ctr0~3: ip power and clock control registers 110 * @ip_pw_sts1~2: ip power and clock status registers 111 * @ip_xhci_cap: ip xHCI capability register 112 * @u3_ctrl_p[x]: ip usb3 port x control register, only low 4bytes are used 113 * @u2_ctrl_p[x]: ip usb2 port x control register, only low 4bytes are used 114 * @u2_phy_pll: usb2 phy pll control register 115 */ 116 struct mu3c_ippc_regs { 117 __le32 ip_pw_ctr0; 118 __le32 ip_pw_ctr1; 119 __le32 ip_pw_ctr2; 120 __le32 ip_pw_ctr3; 121 __le32 ip_pw_sts1; 122 __le32 ip_pw_sts2; 123 __le32 reserved0[3]; 124 __le32 ip_xhci_cap; 125 __le32 reserved1[2]; 126 __le64 u3_ctrl_p[MU3C_U3_PORT_MAX]; 127 __le64 u2_ctrl_p[MU3C_U2_PORT_MAX]; 128 __le32 reserved2; 129 __le32 u2_phy_pll; 130 __le32 reserved3[33]; /* 0x80 ~ 0xff */ 131 }; 132 133 struct xhci_hcd_mtk { 134 struct device *dev; 135 struct usb_hcd *hcd; 136 struct mu3h_sch_bw_info *sch_array; 137 struct list_head bw_ep_chk_list; 138 struct mu3c_ippc_regs __iomem *ippc_regs; 139 int num_u2_ports; 140 int num_u3_ports; 141 int u3p_dis_msk; 142 struct regulator *vusb33; 143 struct regulator *vbus; 144 struct clk_bulk_data clks[BULK_CLKS_NUM]; 145 unsigned int has_ippc:1; 146 unsigned int lpm_support:1; 147 unsigned int u2_lpm_disable:1; 148 /* usb remote wakeup */ 149 unsigned int uwk_en:1; 150 struct regmap *uwk; 151 u32 uwk_reg_base; 152 u32 uwk_vers; 153 }; 154 155 static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd) 156 { 157 return dev_get_drvdata(hcd->self.controller); 158 } 159 160 int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk); 161 void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk); 162 int xhci_mtk_add_ep(struct usb_hcd *hcd, struct usb_device *udev, 163 struct usb_host_endpoint *ep); 164 int xhci_mtk_drop_ep(struct usb_hcd *hcd, struct usb_device *udev, 165 struct usb_host_endpoint *ep); 166 int xhci_mtk_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 167 void xhci_mtk_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 168 169 #endif /* _XHCI_MTK_H_ */ 170