1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: 5 * Zhigang.Wei <zhigang.wei@mediatek.com> 6 * Chunfeng.Yun <chunfeng.yun@mediatek.com> 7 */ 8 9 #ifndef _XHCI_MTK_H_ 10 #define _XHCI_MTK_H_ 11 12 #include <linux/clk.h> 13 14 #include "xhci.h" 15 16 #define BULK_CLKS_NUM 5 17 18 /** 19 * To simplify scheduler algorithm, set a upper limit for ESIT, 20 * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT, 21 * round down to the limit value, that means allocating more 22 * bandwidth to it. 23 */ 24 #define XHCI_MTK_MAX_ESIT 64 25 26 /** 27 * @ss_bit_map: used to avoid start split microframes overlay 28 * @fs_bus_bw: array to keep track of bandwidth already used for FS 29 * @ep_list: Endpoints using this TT 30 */ 31 struct mu3h_sch_tt { 32 DECLARE_BITMAP(ss_bit_map, XHCI_MTK_MAX_ESIT); 33 u32 fs_bus_bw[XHCI_MTK_MAX_ESIT]; 34 struct list_head ep_list; 35 }; 36 37 /** 38 * struct mu3h_sch_bw_info: schedule information for bandwidth domain 39 * 40 * @bus_bw: array to keep track of bandwidth already used at each uframes 41 * @bw_ep_list: eps in the bandwidth domain 42 * 43 * treat a HS root port as a bandwidth domain, but treat a SS root port as 44 * two bandwidth domains, one for IN eps and another for OUT eps. 45 */ 46 struct mu3h_sch_bw_info { 47 u32 bus_bw[XHCI_MTK_MAX_ESIT]; 48 struct list_head bw_ep_list; 49 }; 50 51 /** 52 * struct mu3h_sch_ep_info: schedule information for endpoint 53 * 54 * @esit: unit is 125us, equal to 2 << Interval field in ep-context 55 * @num_budget_microframes: number of continuous uframes 56 * (@repeat==1) scheduled within the interval 57 * @bw_cost_per_microframe: bandwidth cost per microframe 58 * @endpoint: linked into bandwidth domain which it belongs to 59 * @tt_endpoint: linked into mu3h_sch_tt's list which it belongs to 60 * @sch_tt: mu3h_sch_tt linked into 61 * @ep_type: endpoint type 62 * @maxpkt: max packet size of endpoint 63 * @ep: address of usb_host_endpoint struct 64 * @allocated: the bandwidth is aready allocated from bus_bw 65 * @offset: which uframe of the interval that transfer should be 66 * scheduled first time within the interval 67 * @repeat: the time gap between two uframes that transfers are 68 * scheduled within a interval. in the simple algorithm, only 69 * assign 0 or 1 to it; 0 means using only one uframe in a 70 * interval, and 1 means using @num_budget_microframes 71 * continuous uframes 72 * @pkts: number of packets to be transferred in the scheduled uframes 73 * @cs_count: number of CS that host will trigger 74 * @burst_mode: burst mode for scheduling. 0: normal burst mode, 75 * distribute the bMaxBurst+1 packets for a single burst 76 * according to @pkts and @repeat, repeate the burst multiple 77 * times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets 78 * according to @pkts and @repeat. normal mode is used by 79 * default 80 * @bw_budget_table: table to record bandwidth budget per microframe 81 */ 82 struct mu3h_sch_ep_info { 83 u32 esit; 84 u32 num_budget_microframes; 85 u32 bw_cost_per_microframe; 86 struct list_head endpoint; 87 struct list_head tt_endpoint; 88 struct mu3h_sch_tt *sch_tt; 89 u32 ep_type; 90 u32 maxpkt; 91 struct usb_host_endpoint *ep; 92 enum usb_device_speed speed; 93 bool allocated; 94 /* 95 * mtk xHCI scheduling information put into reserved DWs 96 * in ep context 97 */ 98 u32 offset; 99 u32 repeat; 100 u32 pkts; 101 u32 cs_count; 102 u32 burst_mode; 103 u32 bw_budget_table[]; 104 }; 105 106 #define MU3C_U3_PORT_MAX 4 107 #define MU3C_U2_PORT_MAX 5 108 109 /** 110 * struct mu3c_ippc_regs: MTK ssusb ip port control registers 111 * @ip_pw_ctr0~3: ip power and clock control registers 112 * @ip_pw_sts1~2: ip power and clock status registers 113 * @ip_xhci_cap: ip xHCI capability register 114 * @u3_ctrl_p[x]: ip usb3 port x control register, only low 4bytes are used 115 * @u2_ctrl_p[x]: ip usb2 port x control register, only low 4bytes are used 116 * @u2_phy_pll: usb2 phy pll control register 117 */ 118 struct mu3c_ippc_regs { 119 __le32 ip_pw_ctr0; 120 __le32 ip_pw_ctr1; 121 __le32 ip_pw_ctr2; 122 __le32 ip_pw_ctr3; 123 __le32 ip_pw_sts1; 124 __le32 ip_pw_sts2; 125 __le32 reserved0[3]; 126 __le32 ip_xhci_cap; 127 __le32 reserved1[2]; 128 __le64 u3_ctrl_p[MU3C_U3_PORT_MAX]; 129 __le64 u2_ctrl_p[MU3C_U2_PORT_MAX]; 130 __le32 reserved2; 131 __le32 u2_phy_pll; 132 __le32 reserved3[33]; /* 0x80 ~ 0xff */ 133 }; 134 135 struct xhci_hcd_mtk { 136 struct device *dev; 137 struct usb_hcd *hcd; 138 struct mu3h_sch_bw_info *sch_array; 139 struct list_head bw_ep_chk_list; 140 struct mu3c_ippc_regs __iomem *ippc_regs; 141 bool has_ippc; 142 int num_u2_ports; 143 int num_u3_ports; 144 int u3p_dis_msk; 145 struct regulator *vusb33; 146 struct regulator *vbus; 147 struct clk_bulk_data clks[BULK_CLKS_NUM]; 148 bool lpm_support; 149 bool u2_lpm_disable; 150 /* usb remote wakeup */ 151 bool uwk_en; 152 struct regmap *uwk; 153 u32 uwk_reg_base; 154 u32 uwk_vers; 155 }; 156 157 static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd) 158 { 159 return dev_get_drvdata(hcd->self.controller); 160 } 161 162 int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk); 163 void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk); 164 int xhci_mtk_add_ep(struct usb_hcd *hcd, struct usb_device *udev, 165 struct usb_host_endpoint *ep); 166 int xhci_mtk_drop_ep(struct usb_hcd *hcd, struct usb_device *udev, 167 struct usb_host_endpoint *ep); 168 int xhci_mtk_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 169 void xhci_mtk_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 170 171 #endif /* _XHCI_MTK_H_ */ 172