15fd54aceSGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0 20cbd4b34SChunfeng Yun /* 30cbd4b34SChunfeng Yun * Copyright (c) 2015 MediaTek Inc. 40cbd4b34SChunfeng Yun * Author: 50cbd4b34SChunfeng Yun * Zhigang.Wei <zhigang.wei@mediatek.com> 60cbd4b34SChunfeng Yun * Chunfeng.Yun <chunfeng.yun@mediatek.com> 70cbd4b34SChunfeng Yun * 80cbd4b34SChunfeng Yun * This software is licensed under the terms of the GNU General Public 90cbd4b34SChunfeng Yun * License version 2, as published by the Free Software Foundation, and 100cbd4b34SChunfeng Yun * may be copied, distributed, and modified under those terms. 110cbd4b34SChunfeng Yun * 120cbd4b34SChunfeng Yun * This program is distributed in the hope that it will be useful, 130cbd4b34SChunfeng Yun * but WITHOUT ANY WARRANTY; without even the implied warranty of 140cbd4b34SChunfeng Yun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 150cbd4b34SChunfeng Yun * GNU General Public License for more details. 160cbd4b34SChunfeng Yun * 170cbd4b34SChunfeng Yun */ 180cbd4b34SChunfeng Yun 190cbd4b34SChunfeng Yun #ifndef _XHCI_MTK_H_ 200cbd4b34SChunfeng Yun #define _XHCI_MTK_H_ 210cbd4b34SChunfeng Yun 220cbd4b34SChunfeng Yun #include "xhci.h" 230cbd4b34SChunfeng Yun 240cbd4b34SChunfeng Yun /** 250cbd4b34SChunfeng Yun * To simplify scheduler algorithm, set a upper limit for ESIT, 260cbd4b34SChunfeng Yun * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT, 270cbd4b34SChunfeng Yun * round down to the limit value, that means allocating more 280cbd4b34SChunfeng Yun * bandwidth to it. 290cbd4b34SChunfeng Yun */ 300cbd4b34SChunfeng Yun #define XHCI_MTK_MAX_ESIT 64 310cbd4b34SChunfeng Yun 320cbd4b34SChunfeng Yun /** 330cbd4b34SChunfeng Yun * struct mu3h_sch_bw_info: schedule information for bandwidth domain 340cbd4b34SChunfeng Yun * 350cbd4b34SChunfeng Yun * @bus_bw: array to keep track of bandwidth already used at each uframes 360cbd4b34SChunfeng Yun * @bw_ep_list: eps in the bandwidth domain 370cbd4b34SChunfeng Yun * 380cbd4b34SChunfeng Yun * treat a HS root port as a bandwidth domain, but treat a SS root port as 390cbd4b34SChunfeng Yun * two bandwidth domains, one for IN eps and another for OUT eps. 400cbd4b34SChunfeng Yun */ 410cbd4b34SChunfeng Yun struct mu3h_sch_bw_info { 420cbd4b34SChunfeng Yun u32 bus_bw[XHCI_MTK_MAX_ESIT]; 430cbd4b34SChunfeng Yun struct list_head bw_ep_list; 440cbd4b34SChunfeng Yun }; 450cbd4b34SChunfeng Yun 460cbd4b34SChunfeng Yun /** 470cbd4b34SChunfeng Yun * struct mu3h_sch_ep_info: schedule information for endpoint 480cbd4b34SChunfeng Yun * 490cbd4b34SChunfeng Yun * @esit: unit is 125us, equal to 2 << Interval field in ep-context 500cbd4b34SChunfeng Yun * @num_budget_microframes: number of continuous uframes 510cbd4b34SChunfeng Yun * (@repeat==1) scheduled within the interval 520cbd4b34SChunfeng Yun * @bw_cost_per_microframe: bandwidth cost per microframe 530cbd4b34SChunfeng Yun * @endpoint: linked into bandwidth domain which it belongs to 540cbd4b34SChunfeng Yun * @ep: address of usb_host_endpoint struct 550cbd4b34SChunfeng Yun * @offset: which uframe of the interval that transfer should be 560cbd4b34SChunfeng Yun * scheduled first time within the interval 570cbd4b34SChunfeng Yun * @repeat: the time gap between two uframes that transfers are 580cbd4b34SChunfeng Yun * scheduled within a interval. in the simple algorithm, only 590cbd4b34SChunfeng Yun * assign 0 or 1 to it; 0 means using only one uframe in a 600cbd4b34SChunfeng Yun * interval, and 1 means using @num_budget_microframes 610cbd4b34SChunfeng Yun * continuous uframes 620cbd4b34SChunfeng Yun * @pkts: number of packets to be transferred in the scheduled uframes 630cbd4b34SChunfeng Yun * @cs_count: number of CS that host will trigger 640cbd4b34SChunfeng Yun * @burst_mode: burst mode for scheduling. 0: normal burst mode, 650cbd4b34SChunfeng Yun * distribute the bMaxBurst+1 packets for a single burst 660cbd4b34SChunfeng Yun * according to @pkts and @repeat, repeate the burst multiple 670cbd4b34SChunfeng Yun * times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets 680cbd4b34SChunfeng Yun * according to @pkts and @repeat. normal mode is used by 690cbd4b34SChunfeng Yun * default 700cbd4b34SChunfeng Yun */ 710cbd4b34SChunfeng Yun struct mu3h_sch_ep_info { 720cbd4b34SChunfeng Yun u32 esit; 730cbd4b34SChunfeng Yun u32 num_budget_microframes; 740cbd4b34SChunfeng Yun u32 bw_cost_per_microframe; 750cbd4b34SChunfeng Yun struct list_head endpoint; 760cbd4b34SChunfeng Yun void *ep; 770cbd4b34SChunfeng Yun /* 780cbd4b34SChunfeng Yun * mtk xHCI scheduling information put into reserved DWs 790cbd4b34SChunfeng Yun * in ep context 800cbd4b34SChunfeng Yun */ 810cbd4b34SChunfeng Yun u32 offset; 820cbd4b34SChunfeng Yun u32 repeat; 830cbd4b34SChunfeng Yun u32 pkts; 840cbd4b34SChunfeng Yun u32 cs_count; 850cbd4b34SChunfeng Yun u32 burst_mode; 860cbd4b34SChunfeng Yun }; 870cbd4b34SChunfeng Yun 880cbd4b34SChunfeng Yun #define MU3C_U3_PORT_MAX 4 890cbd4b34SChunfeng Yun #define MU3C_U2_PORT_MAX 5 900cbd4b34SChunfeng Yun 910cbd4b34SChunfeng Yun /** 920cbd4b34SChunfeng Yun * struct mu3c_ippc_regs: MTK ssusb ip port control registers 930cbd4b34SChunfeng Yun * @ip_pw_ctr0~3: ip power and clock control registers 940cbd4b34SChunfeng Yun * @ip_pw_sts1~2: ip power and clock status registers 950cbd4b34SChunfeng Yun * @ip_xhci_cap: ip xHCI capability register 960cbd4b34SChunfeng Yun * @u3_ctrl_p[x]: ip usb3 port x control register, only low 4bytes are used 970cbd4b34SChunfeng Yun * @u2_ctrl_p[x]: ip usb2 port x control register, only low 4bytes are used 980cbd4b34SChunfeng Yun * @u2_phy_pll: usb2 phy pll control register 990cbd4b34SChunfeng Yun */ 1000cbd4b34SChunfeng Yun struct mu3c_ippc_regs { 1010cbd4b34SChunfeng Yun __le32 ip_pw_ctr0; 1020cbd4b34SChunfeng Yun __le32 ip_pw_ctr1; 1030cbd4b34SChunfeng Yun __le32 ip_pw_ctr2; 1040cbd4b34SChunfeng Yun __le32 ip_pw_ctr3; 1050cbd4b34SChunfeng Yun __le32 ip_pw_sts1; 1060cbd4b34SChunfeng Yun __le32 ip_pw_sts2; 1070cbd4b34SChunfeng Yun __le32 reserved0[3]; 1080cbd4b34SChunfeng Yun __le32 ip_xhci_cap; 1090cbd4b34SChunfeng Yun __le32 reserved1[2]; 1100cbd4b34SChunfeng Yun __le64 u3_ctrl_p[MU3C_U3_PORT_MAX]; 1110cbd4b34SChunfeng Yun __le64 u2_ctrl_p[MU3C_U2_PORT_MAX]; 1120cbd4b34SChunfeng Yun __le32 reserved2; 1130cbd4b34SChunfeng Yun __le32 u2_phy_pll; 1140cbd4b34SChunfeng Yun __le32 reserved3[33]; /* 0x80 ~ 0xff */ 1150cbd4b34SChunfeng Yun }; 1160cbd4b34SChunfeng Yun 1170cbd4b34SChunfeng Yun struct xhci_hcd_mtk { 1180cbd4b34SChunfeng Yun struct device *dev; 1190cbd4b34SChunfeng Yun struct usb_hcd *hcd; 1200cbd4b34SChunfeng Yun struct mu3h_sch_bw_info *sch_array; 1210cbd4b34SChunfeng Yun struct mu3c_ippc_regs __iomem *ippc_regs; 122065d48cfSChunfeng Yun bool has_ippc; 1230cbd4b34SChunfeng Yun int num_u2_ports; 1240cbd4b34SChunfeng Yun int num_u3_ports; 12555ba6e9eSChunfeng Yun int u3p_dis_msk; 1260cbd4b34SChunfeng Yun struct regulator *vusb33; 1270cbd4b34SChunfeng Yun struct regulator *vbus; 1280cbd4b34SChunfeng Yun struct clk *sys_clk; /* sys and mac clock */ 1299c4afd42SChunfeng Yun struct clk *ref_clk; 130b6bb72cfSChunfeng Yun struct clk *mcu_clk; 131b6bb72cfSChunfeng Yun struct clk *dma_clk; 1320cbd4b34SChunfeng Yun struct regmap *pericfg; 1330cbd4b34SChunfeng Yun struct phy **phys; 1340cbd4b34SChunfeng Yun int num_phys; 1350cbd4b34SChunfeng Yun int wakeup_src; 1360cbd4b34SChunfeng Yun bool lpm_support; 1370cbd4b34SChunfeng Yun }; 1380cbd4b34SChunfeng Yun 1390cbd4b34SChunfeng Yun static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd) 1400cbd4b34SChunfeng Yun { 1410cbd4b34SChunfeng Yun return dev_get_drvdata(hcd->self.controller); 1420cbd4b34SChunfeng Yun } 1430cbd4b34SChunfeng Yun 1440cbd4b34SChunfeng Yun #if IS_ENABLED(CONFIG_USB_XHCI_MTK) 1450cbd4b34SChunfeng Yun int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk); 1460cbd4b34SChunfeng Yun void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk); 1470cbd4b34SChunfeng Yun int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev, 1480cbd4b34SChunfeng Yun struct usb_host_endpoint *ep); 1490cbd4b34SChunfeng Yun void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev, 1500cbd4b34SChunfeng Yun struct usb_host_endpoint *ep); 1510cbd4b34SChunfeng Yun 1520cbd4b34SChunfeng Yun #else 1530cbd4b34SChunfeng Yun static inline int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, 1540cbd4b34SChunfeng Yun struct usb_device *udev, struct usb_host_endpoint *ep) 1550cbd4b34SChunfeng Yun { 1560cbd4b34SChunfeng Yun return 0; 1570cbd4b34SChunfeng Yun } 1580cbd4b34SChunfeng Yun 1590cbd4b34SChunfeng Yun static inline void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, 1600cbd4b34SChunfeng Yun struct usb_device *udev, struct usb_host_endpoint *ep) 1610cbd4b34SChunfeng Yun { 1620cbd4b34SChunfeng Yun } 1630cbd4b34SChunfeng Yun 1640cbd4b34SChunfeng Yun #endif 1650cbd4b34SChunfeng Yun 1660cbd4b34SChunfeng Yun #endif /* _XHCI_MTK_H_ */ 167