13e45ed3cSNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */
20cbd4b34SChunfeng Yun /*
30cbd4b34SChunfeng Yun * Copyright (c) 2015 MediaTek Inc.
40cbd4b34SChunfeng Yun * Author:
50cbd4b34SChunfeng Yun * Zhigang.Wei <zhigang.wei@mediatek.com>
60cbd4b34SChunfeng Yun * Chunfeng.Yun <chunfeng.yun@mediatek.com>
70cbd4b34SChunfeng Yun */
80cbd4b34SChunfeng Yun
90cbd4b34SChunfeng Yun #ifndef _XHCI_MTK_H_
100cbd4b34SChunfeng Yun #define _XHCI_MTK_H_
110cbd4b34SChunfeng Yun
127fed6368SChunfeng Yun #include <linux/clk.h>
134ce18666SChunfeng Yun #include <linux/hashtable.h>
145f508d79SAngeloGioacchino Del Regno #include <linux/regulator/consumer.h>
157fed6368SChunfeng Yun
160cbd4b34SChunfeng Yun #include "xhci.h"
170cbd4b34SChunfeng Yun
186a14ffc0SChunfeng Yun #define BULK_CLKS_NUM 6
195f508d79SAngeloGioacchino Del Regno #define BULK_VREGS_NUM 2
207fed6368SChunfeng Yun
214ce18666SChunfeng Yun /* support at most 64 ep, use 32 size hash table */
224ce18666SChunfeng Yun #define SCH_EP_HASH_BITS 5
234ce18666SChunfeng Yun
240cbd4b34SChunfeng Yun /**
250cbd4b34SChunfeng Yun * To simplify scheduler algorithm, set a upper limit for ESIT,
260cbd4b34SChunfeng Yun * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT,
270cbd4b34SChunfeng Yun * round down to the limit value, that means allocating more
280cbd4b34SChunfeng Yun * bandwidth to it.
290cbd4b34SChunfeng Yun */
30b7d509a9SChunfeng Yun #define XHCI_MTK_MAX_ESIT (1 << 6)
31b7d509a9SChunfeng Yun #define XHCI_MTK_BW_INDEX(x) ((x) & (XHCI_MTK_MAX_ESIT - 1))
320cbd4b34SChunfeng Yun
330cbd4b34SChunfeng Yun /**
34e19ee44aSChunfeng Yun * @fs_bus_bw: array to keep track of bandwidth already used for FS
35f2a9797bSChunfeng Yun * @ep_list: Endpoints using this TT
3608e469deSChunfeng Yun */
3708e469deSChunfeng Yun struct mu3h_sch_tt {
38e19ee44aSChunfeng Yun u32 fs_bus_bw[XHCI_MTK_MAX_ESIT];
39f2a9797bSChunfeng Yun struct list_head ep_list;
4008e469deSChunfeng Yun };
4108e469deSChunfeng Yun
4208e469deSChunfeng Yun /**
430cbd4b34SChunfeng Yun * struct mu3h_sch_bw_info: schedule information for bandwidth domain
440cbd4b34SChunfeng Yun *
450cbd4b34SChunfeng Yun * @bus_bw: array to keep track of bandwidth already used at each uframes
460cbd4b34SChunfeng Yun *
470cbd4b34SChunfeng Yun * treat a HS root port as a bandwidth domain, but treat a SS root port as
480cbd4b34SChunfeng Yun * two bandwidth domains, one for IN eps and another for OUT eps.
490cbd4b34SChunfeng Yun */
500cbd4b34SChunfeng Yun struct mu3h_sch_bw_info {
510cbd4b34SChunfeng Yun u32 bus_bw[XHCI_MTK_MAX_ESIT];
520cbd4b34SChunfeng Yun };
530cbd4b34SChunfeng Yun
540cbd4b34SChunfeng Yun /**
550cbd4b34SChunfeng Yun * struct mu3h_sch_ep_info: schedule information for endpoint
560cbd4b34SChunfeng Yun *
570cbd4b34SChunfeng Yun * @esit: unit is 125us, equal to 2 << Interval field in ep-context
5882799c80SChunfeng Yun * @num_esit: number of @esit in a period
590cbd4b34SChunfeng Yun * @num_budget_microframes: number of continuous uframes
600cbd4b34SChunfeng Yun * (@repeat==1) scheduled within the interval
610cbd4b34SChunfeng Yun * @bw_cost_per_microframe: bandwidth cost per microframe
624ce18666SChunfeng Yun * @hentry: hash table entry
63f2a9797bSChunfeng Yun * @endpoint: linked into bandwidth domain which it belongs to
64f2a9797bSChunfeng Yun * @tt_endpoint: linked into mu3h_sch_tt's list which it belongs to
654ce18666SChunfeng Yun * @bw_info: bandwidth domain which this endpoint belongs
6608e469deSChunfeng Yun * @sch_tt: mu3h_sch_tt linked into
6708e469deSChunfeng Yun * @ep_type: endpoint type
6808e469deSChunfeng Yun * @maxpkt: max packet size of endpoint
690cbd4b34SChunfeng Yun * @ep: address of usb_host_endpoint struct
7054f6a8afSChunfeng Yun * @allocated: the bandwidth is aready allocated from bus_bw
710cbd4b34SChunfeng Yun * @offset: which uframe of the interval that transfer should be
720cbd4b34SChunfeng Yun * scheduled first time within the interval
730cbd4b34SChunfeng Yun * @repeat: the time gap between two uframes that transfers are
740cbd4b34SChunfeng Yun * scheduled within a interval. in the simple algorithm, only
750cbd4b34SChunfeng Yun * assign 0 or 1 to it; 0 means using only one uframe in a
760cbd4b34SChunfeng Yun * interval, and 1 means using @num_budget_microframes
770cbd4b34SChunfeng Yun * continuous uframes
780cbd4b34SChunfeng Yun * @pkts: number of packets to be transferred in the scheduled uframes
790cbd4b34SChunfeng Yun * @cs_count: number of CS that host will trigger
800cbd4b34SChunfeng Yun * @burst_mode: burst mode for scheduling. 0: normal burst mode,
810cbd4b34SChunfeng Yun * distribute the bMaxBurst+1 packets for a single burst
820cbd4b34SChunfeng Yun * according to @pkts and @repeat, repeate the burst multiple
830cbd4b34SChunfeng Yun * times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets
840cbd4b34SChunfeng Yun * according to @pkts and @repeat. normal mode is used by
850cbd4b34SChunfeng Yun * default
860cbd4b34SChunfeng Yun */
870cbd4b34SChunfeng Yun struct mu3h_sch_ep_info {
880cbd4b34SChunfeng Yun u32 esit;
8982799c80SChunfeng Yun u32 num_esit;
900cbd4b34SChunfeng Yun u32 num_budget_microframes;
910cbd4b34SChunfeng Yun u32 bw_cost_per_microframe;
920cbd4b34SChunfeng Yun struct list_head endpoint;
934ce18666SChunfeng Yun struct hlist_node hentry;
94f2a9797bSChunfeng Yun struct list_head tt_endpoint;
954ce18666SChunfeng Yun struct mu3h_sch_bw_info *bw_info;
9608e469deSChunfeng Yun struct mu3h_sch_tt *sch_tt;
9708e469deSChunfeng Yun u32 ep_type;
9808e469deSChunfeng Yun u32 maxpkt;
999132799dSChunfeng Yun struct usb_host_endpoint *ep;
1006009bea0SChunfeng Yun enum usb_device_speed speed;
10154f6a8afSChunfeng Yun bool allocated;
1020cbd4b34SChunfeng Yun /*
1030cbd4b34SChunfeng Yun * mtk xHCI scheduling information put into reserved DWs
1040cbd4b34SChunfeng Yun * in ep context
1050cbd4b34SChunfeng Yun */
1060cbd4b34SChunfeng Yun u32 offset;
1070cbd4b34SChunfeng Yun u32 repeat;
1080cbd4b34SChunfeng Yun u32 pkts;
1090cbd4b34SChunfeng Yun u32 cs_count;
1100cbd4b34SChunfeng Yun u32 burst_mode;
1110cbd4b34SChunfeng Yun };
1120cbd4b34SChunfeng Yun
1130cbd4b34SChunfeng Yun #define MU3C_U3_PORT_MAX 4
1140cbd4b34SChunfeng Yun #define MU3C_U2_PORT_MAX 5
1150cbd4b34SChunfeng Yun
1160cbd4b34SChunfeng Yun /**
1170cbd4b34SChunfeng Yun * struct mu3c_ippc_regs: MTK ssusb ip port control registers
1180cbd4b34SChunfeng Yun * @ip_pw_ctr0~3: ip power and clock control registers
1190cbd4b34SChunfeng Yun * @ip_pw_sts1~2: ip power and clock status registers
1200cbd4b34SChunfeng Yun * @ip_xhci_cap: ip xHCI capability register
1210cbd4b34SChunfeng Yun * @u3_ctrl_p[x]: ip usb3 port x control register, only low 4bytes are used
1220cbd4b34SChunfeng Yun * @u2_ctrl_p[x]: ip usb2 port x control register, only low 4bytes are used
1230cbd4b34SChunfeng Yun * @u2_phy_pll: usb2 phy pll control register
1240cbd4b34SChunfeng Yun */
1250cbd4b34SChunfeng Yun struct mu3c_ippc_regs {
1260cbd4b34SChunfeng Yun __le32 ip_pw_ctr0;
1270cbd4b34SChunfeng Yun __le32 ip_pw_ctr1;
1280cbd4b34SChunfeng Yun __le32 ip_pw_ctr2;
1290cbd4b34SChunfeng Yun __le32 ip_pw_ctr3;
1300cbd4b34SChunfeng Yun __le32 ip_pw_sts1;
1310cbd4b34SChunfeng Yun __le32 ip_pw_sts2;
1320cbd4b34SChunfeng Yun __le32 reserved0[3];
1330cbd4b34SChunfeng Yun __le32 ip_xhci_cap;
1340cbd4b34SChunfeng Yun __le32 reserved1[2];
1350cbd4b34SChunfeng Yun __le64 u3_ctrl_p[MU3C_U3_PORT_MAX];
1360cbd4b34SChunfeng Yun __le64 u2_ctrl_p[MU3C_U2_PORT_MAX];
1370cbd4b34SChunfeng Yun __le32 reserved2;
1380cbd4b34SChunfeng Yun __le32 u2_phy_pll;
1390cbd4b34SChunfeng Yun __le32 reserved3[33]; /* 0x80 ~ 0xff */
1400cbd4b34SChunfeng Yun };
1410cbd4b34SChunfeng Yun
1420cbd4b34SChunfeng Yun struct xhci_hcd_mtk {
1430cbd4b34SChunfeng Yun struct device *dev;
1440cbd4b34SChunfeng Yun struct usb_hcd *hcd;
1450cbd4b34SChunfeng Yun struct mu3h_sch_bw_info *sch_array;
14654f6a8afSChunfeng Yun struct list_head bw_ep_chk_list;
1474ce18666SChunfeng Yun DECLARE_HASHTABLE(sch_ep_hash, SCH_EP_HASH_BITS);
1480cbd4b34SChunfeng Yun struct mu3c_ippc_regs __iomem *ippc_regs;
1490cbd4b34SChunfeng Yun int num_u2_ports;
1500cbd4b34SChunfeng Yun int num_u3_ports;
1517465d7b6SChunfeng Yun int u2p_dis_msk;
15255ba6e9eSChunfeng Yun int u3p_dis_msk;
1537fed6368SChunfeng Yun struct clk_bulk_data clks[BULK_CLKS_NUM];
1545f508d79SAngeloGioacchino Del Regno struct regulator_bulk_data supplies[BULK_VREGS_NUM];
15540ddb76bSChunfeng Yun unsigned int has_ippc:1;
15640ddb76bSChunfeng Yun unsigned int lpm_support:1;
15740ddb76bSChunfeng Yun unsigned int u2_lpm_disable:1;
158a2ecc4dfSChunfeng Yun /* usb remote wakeup */
15940ddb76bSChunfeng Yun unsigned int uwk_en:1;
160a2ecc4dfSChunfeng Yun struct regmap *uwk;
161a2ecc4dfSChunfeng Yun u32 uwk_reg_base;
162a2ecc4dfSChunfeng Yun u32 uwk_vers;
163*821ad008SChunfeng Yun /* quirk */
164*821ad008SChunfeng Yun u32 rxfifo_depth;
1650cbd4b34SChunfeng Yun };
1660cbd4b34SChunfeng Yun
hcd_to_mtk(struct usb_hcd * hcd)1670cbd4b34SChunfeng Yun static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd)
1680cbd4b34SChunfeng Yun {
1690cbd4b34SChunfeng Yun return dev_get_drvdata(hcd->self.controller);
1700cbd4b34SChunfeng Yun }
1710cbd4b34SChunfeng Yun
1720cbd4b34SChunfeng Yun int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk);
1730cbd4b34SChunfeng Yun void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk);
17414295a15SChunfeng Yun int xhci_mtk_add_ep(struct usb_hcd *hcd, struct usb_device *udev,
1750cbd4b34SChunfeng Yun struct usb_host_endpoint *ep);
17614295a15SChunfeng Yun int xhci_mtk_drop_ep(struct usb_hcd *hcd, struct usb_device *udev,
1770cbd4b34SChunfeng Yun struct usb_host_endpoint *ep);
1781d69f9d9SIkjoon Jang int xhci_mtk_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1791d69f9d9SIkjoon Jang void xhci_mtk_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1800cbd4b34SChunfeng Yun
1810cbd4b34SChunfeng Yun #endif /* _XHCI_MTK_H_ */
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