1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek xHCI Host Controller Driver 4 * 5 * Copyright (c) 2015 MediaTek Inc. 6 * Author: 7 * Chunfeng Yun <chunfeng.yun@mediatek.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/iopoll.h> 13 #include <linux/kernel.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/regmap.h> 20 #include <linux/regulator/consumer.h> 21 22 #include "xhci.h" 23 #include "xhci-mtk.h" 24 25 /* ip_pw_ctrl0 register */ 26 #define CTRL0_IP_SW_RST BIT(0) 27 28 /* ip_pw_ctrl1 register */ 29 #define CTRL1_IP_HOST_PDN BIT(0) 30 31 /* ip_pw_ctrl2 register */ 32 #define CTRL2_IP_DEV_PDN BIT(0) 33 34 /* ip_pw_sts1 register */ 35 #define STS1_IP_SLEEP_STS BIT(30) 36 #define STS1_U3_MAC_RST BIT(16) 37 #define STS1_XHCI_RST BIT(11) 38 #define STS1_SYS125_RST BIT(10) 39 #define STS1_REF_RST BIT(8) 40 #define STS1_SYSPLL_STABLE BIT(0) 41 42 /* ip_xhci_cap register */ 43 #define CAP_U3_PORT_NUM(p) ((p) & 0xff) 44 #define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff) 45 46 /* u3_ctrl_p register */ 47 #define CTRL_U3_PORT_HOST_SEL BIT(2) 48 #define CTRL_U3_PORT_PDN BIT(1) 49 #define CTRL_U3_PORT_DIS BIT(0) 50 51 /* u2_ctrl_p register */ 52 #define CTRL_U2_PORT_HOST_SEL BIT(2) 53 #define CTRL_U2_PORT_PDN BIT(1) 54 #define CTRL_U2_PORT_DIS BIT(0) 55 56 /* u2_phy_pll register */ 57 #define CTRL_U2_FORCE_PLL_STB BIT(28) 58 59 /* usb remote wakeup registers in syscon */ 60 /* mt8173 etc */ 61 #define PERI_WK_CTRL1 0x4 62 #define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */ 63 #define WC1_IS_EN BIT(25) 64 #define WC1_IS_P BIT(6) /* polarity for ip sleep */ 65 66 /* mt2712 etc */ 67 #define PERI_SSUSB_SPM_CTRL 0x0 68 #define SSC_IP_SLEEP_EN BIT(4) 69 #define SSC_SPM_INT_EN BIT(1) 70 71 enum ssusb_uwk_vers { 72 SSUSB_UWK_V1 = 1, 73 SSUSB_UWK_V2, 74 }; 75 76 static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk) 77 { 78 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; 79 u32 value, check_val; 80 int u3_ports_disabed = 0; 81 int ret; 82 int i; 83 84 if (!mtk->has_ippc) 85 return 0; 86 87 /* power on host ip */ 88 value = readl(&ippc->ip_pw_ctr1); 89 value &= ~CTRL1_IP_HOST_PDN; 90 writel(value, &ippc->ip_pw_ctr1); 91 92 /* power on and enable u3 ports except skipped ones */ 93 for (i = 0; i < mtk->num_u3_ports; i++) { 94 if ((0x1 << i) & mtk->u3p_dis_msk) { 95 u3_ports_disabed++; 96 continue; 97 } 98 99 value = readl(&ippc->u3_ctrl_p[i]); 100 value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS); 101 value |= CTRL_U3_PORT_HOST_SEL; 102 writel(value, &ippc->u3_ctrl_p[i]); 103 } 104 105 /* power on and enable all u2 ports */ 106 for (i = 0; i < mtk->num_u2_ports; i++) { 107 value = readl(&ippc->u2_ctrl_p[i]); 108 value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS); 109 value |= CTRL_U2_PORT_HOST_SEL; 110 writel(value, &ippc->u2_ctrl_p[i]); 111 } 112 113 /* 114 * wait for clocks to be stable, and clock domains reset to 115 * be inactive after power on and enable ports 116 */ 117 check_val = STS1_SYSPLL_STABLE | STS1_REF_RST | 118 STS1_SYS125_RST | STS1_XHCI_RST; 119 120 if (mtk->num_u3_ports > u3_ports_disabed) 121 check_val |= STS1_U3_MAC_RST; 122 123 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value, 124 (check_val == (value & check_val)), 100, 20000); 125 if (ret) { 126 dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value); 127 return ret; 128 } 129 130 return 0; 131 } 132 133 static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk) 134 { 135 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; 136 u32 value; 137 int ret; 138 int i; 139 140 if (!mtk->has_ippc) 141 return 0; 142 143 /* power down u3 ports except skipped ones */ 144 for (i = 0; i < mtk->num_u3_ports; i++) { 145 if ((0x1 << i) & mtk->u3p_dis_msk) 146 continue; 147 148 value = readl(&ippc->u3_ctrl_p[i]); 149 value |= CTRL_U3_PORT_PDN; 150 writel(value, &ippc->u3_ctrl_p[i]); 151 } 152 153 /* power down all u2 ports */ 154 for (i = 0; i < mtk->num_u2_ports; i++) { 155 value = readl(&ippc->u2_ctrl_p[i]); 156 value |= CTRL_U2_PORT_PDN; 157 writel(value, &ippc->u2_ctrl_p[i]); 158 } 159 160 /* power down host ip */ 161 value = readl(&ippc->ip_pw_ctr1); 162 value |= CTRL1_IP_HOST_PDN; 163 writel(value, &ippc->ip_pw_ctr1); 164 165 /* wait for host ip to sleep */ 166 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value, 167 (value & STS1_IP_SLEEP_STS), 100, 100000); 168 if (ret) { 169 dev_err(mtk->dev, "ip sleep failed!!!\n"); 170 return ret; 171 } 172 return 0; 173 } 174 175 static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk) 176 { 177 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; 178 u32 value; 179 180 if (!mtk->has_ippc) 181 return 0; 182 183 /* reset whole ip */ 184 value = readl(&ippc->ip_pw_ctr0); 185 value |= CTRL0_IP_SW_RST; 186 writel(value, &ippc->ip_pw_ctr0); 187 udelay(1); 188 value = readl(&ippc->ip_pw_ctr0); 189 value &= ~CTRL0_IP_SW_RST; 190 writel(value, &ippc->ip_pw_ctr0); 191 192 /* 193 * device ip is default power-on in fact 194 * power down device ip, otherwise ip-sleep will fail 195 */ 196 value = readl(&ippc->ip_pw_ctr2); 197 value |= CTRL2_IP_DEV_PDN; 198 writel(value, &ippc->ip_pw_ctr2); 199 200 value = readl(&ippc->ip_xhci_cap); 201 mtk->num_u3_ports = CAP_U3_PORT_NUM(value); 202 mtk->num_u2_ports = CAP_U2_PORT_NUM(value); 203 dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__, 204 mtk->num_u2_ports, mtk->num_u3_ports); 205 206 return xhci_mtk_host_enable(mtk); 207 } 208 209 static int xhci_mtk_clks_get(struct xhci_hcd_mtk *mtk) 210 { 211 struct device *dev = mtk->dev; 212 213 mtk->sys_clk = devm_clk_get(dev, "sys_ck"); 214 if (IS_ERR(mtk->sys_clk)) { 215 dev_err(dev, "fail to get sys_ck\n"); 216 return PTR_ERR(mtk->sys_clk); 217 } 218 219 mtk->ref_clk = devm_clk_get_optional(dev, "ref_ck"); 220 if (IS_ERR(mtk->ref_clk)) 221 return PTR_ERR(mtk->ref_clk); 222 223 mtk->mcu_clk = devm_clk_get_optional(dev, "mcu_ck"); 224 if (IS_ERR(mtk->mcu_clk)) 225 return PTR_ERR(mtk->mcu_clk); 226 227 mtk->dma_clk = devm_clk_get_optional(dev, "dma_ck"); 228 return PTR_ERR_OR_ZERO(mtk->dma_clk); 229 } 230 231 static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk) 232 { 233 int ret; 234 235 ret = clk_prepare_enable(mtk->ref_clk); 236 if (ret) { 237 dev_err(mtk->dev, "failed to enable ref_clk\n"); 238 goto ref_clk_err; 239 } 240 241 ret = clk_prepare_enable(mtk->sys_clk); 242 if (ret) { 243 dev_err(mtk->dev, "failed to enable sys_clk\n"); 244 goto sys_clk_err; 245 } 246 247 ret = clk_prepare_enable(mtk->mcu_clk); 248 if (ret) { 249 dev_err(mtk->dev, "failed to enable mcu_clk\n"); 250 goto mcu_clk_err; 251 } 252 253 ret = clk_prepare_enable(mtk->dma_clk); 254 if (ret) { 255 dev_err(mtk->dev, "failed to enable dma_clk\n"); 256 goto dma_clk_err; 257 } 258 259 return 0; 260 261 dma_clk_err: 262 clk_disable_unprepare(mtk->mcu_clk); 263 mcu_clk_err: 264 clk_disable_unprepare(mtk->sys_clk); 265 sys_clk_err: 266 clk_disable_unprepare(mtk->ref_clk); 267 ref_clk_err: 268 return ret; 269 } 270 271 static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk) 272 { 273 clk_disable_unprepare(mtk->dma_clk); 274 clk_disable_unprepare(mtk->mcu_clk); 275 clk_disable_unprepare(mtk->sys_clk); 276 clk_disable_unprepare(mtk->ref_clk); 277 } 278 279 /* only clocks can be turn off for ip-sleep wakeup mode */ 280 static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable) 281 { 282 u32 reg, msk, val; 283 284 switch (mtk->uwk_vers) { 285 case SSUSB_UWK_V1: 286 reg = mtk->uwk_reg_base + PERI_WK_CTRL1; 287 msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P; 288 val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0; 289 break; 290 case SSUSB_UWK_V2: 291 reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL; 292 msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN; 293 val = enable ? msk : 0; 294 break; 295 default: 296 return; 297 } 298 regmap_update_bits(mtk->uwk, reg, msk, val); 299 } 300 301 static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk, 302 struct device_node *dn) 303 { 304 struct of_phandle_args args; 305 int ret; 306 307 /* Wakeup function is optional */ 308 mtk->uwk_en = of_property_read_bool(dn, "wakeup-source"); 309 if (!mtk->uwk_en) 310 return 0; 311 312 ret = of_parse_phandle_with_fixed_args(dn, 313 "mediatek,syscon-wakeup", 2, 0, &args); 314 if (ret) 315 return ret; 316 317 mtk->uwk_reg_base = args.args[0]; 318 mtk->uwk_vers = args.args[1]; 319 mtk->uwk = syscon_node_to_regmap(args.np); 320 of_node_put(args.np); 321 dev_info(mtk->dev, "uwk - reg:0x%x, version:%d\n", 322 mtk->uwk_reg_base, mtk->uwk_vers); 323 324 return PTR_ERR_OR_ZERO(mtk->uwk); 325 326 } 327 328 static void usb_wakeup_set(struct xhci_hcd_mtk *mtk, bool enable) 329 { 330 if (mtk->uwk_en) 331 usb_wakeup_ip_sleep_set(mtk, enable); 332 } 333 334 static int xhci_mtk_setup(struct usb_hcd *hcd); 335 static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = { 336 .reset = xhci_mtk_setup, 337 }; 338 339 static struct hc_driver __read_mostly xhci_mtk_hc_driver; 340 341 static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk) 342 { 343 int ret; 344 345 ret = regulator_enable(mtk->vbus); 346 if (ret) { 347 dev_err(mtk->dev, "failed to enable vbus\n"); 348 return ret; 349 } 350 351 ret = regulator_enable(mtk->vusb33); 352 if (ret) { 353 dev_err(mtk->dev, "failed to enable vusb33\n"); 354 regulator_disable(mtk->vbus); 355 return ret; 356 } 357 return 0; 358 } 359 360 static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk) 361 { 362 regulator_disable(mtk->vbus); 363 regulator_disable(mtk->vusb33); 364 } 365 366 static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci) 367 { 368 struct usb_hcd *hcd = xhci_to_hcd(xhci); 369 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd); 370 371 /* 372 * As of now platform drivers don't provide MSI support so we ensure 373 * here that the generic code does not try to make a pci_dev from our 374 * dev struct in order to setup MSI 375 */ 376 xhci->quirks |= XHCI_PLAT; 377 xhci->quirks |= XHCI_MTK_HOST; 378 /* 379 * MTK host controller gives a spurious successful event after a 380 * short transfer. Ignore it. 381 */ 382 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 383 if (mtk->lpm_support) 384 xhci->quirks |= XHCI_LPM_SUPPORT; 385 } 386 387 /* called during probe() after chip reset completes */ 388 static int xhci_mtk_setup(struct usb_hcd *hcd) 389 { 390 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd); 391 int ret; 392 393 if (usb_hcd_is_primary_hcd(hcd)) { 394 ret = xhci_mtk_ssusb_config(mtk); 395 if (ret) 396 return ret; 397 } 398 399 ret = xhci_gen_setup(hcd, xhci_mtk_quirks); 400 if (ret) 401 return ret; 402 403 if (usb_hcd_is_primary_hcd(hcd)) { 404 ret = xhci_mtk_sch_init(mtk); 405 if (ret) 406 return ret; 407 } 408 409 return ret; 410 } 411 412 static int xhci_mtk_probe(struct platform_device *pdev) 413 { 414 struct device *dev = &pdev->dev; 415 struct device_node *node = dev->of_node; 416 struct xhci_hcd_mtk *mtk; 417 const struct hc_driver *driver; 418 struct xhci_hcd *xhci; 419 struct resource *res; 420 struct usb_hcd *hcd; 421 int ret = -ENODEV; 422 int irq; 423 424 if (usb_disabled()) 425 return -ENODEV; 426 427 driver = &xhci_mtk_hc_driver; 428 mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL); 429 if (!mtk) 430 return -ENOMEM; 431 432 mtk->dev = dev; 433 mtk->vbus = devm_regulator_get(dev, "vbus"); 434 if (IS_ERR(mtk->vbus)) { 435 dev_err(dev, "fail to get vbus\n"); 436 return PTR_ERR(mtk->vbus); 437 } 438 439 mtk->vusb33 = devm_regulator_get(dev, "vusb33"); 440 if (IS_ERR(mtk->vusb33)) { 441 dev_err(dev, "fail to get vusb33\n"); 442 return PTR_ERR(mtk->vusb33); 443 } 444 445 ret = xhci_mtk_clks_get(mtk); 446 if (ret) 447 return ret; 448 449 mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable"); 450 /* optional property, ignore the error if it does not exist */ 451 of_property_read_u32(node, "mediatek,u3p-dis-msk", 452 &mtk->u3p_dis_msk); 453 454 ret = usb_wakeup_of_property_parse(mtk, node); 455 if (ret) { 456 dev_err(dev, "failed to parse uwk property\n"); 457 return ret; 458 } 459 460 pm_runtime_enable(dev); 461 pm_runtime_get_sync(dev); 462 device_enable_async_suspend(dev); 463 464 ret = xhci_mtk_ldos_enable(mtk); 465 if (ret) 466 goto disable_pm; 467 468 ret = xhci_mtk_clks_enable(mtk); 469 if (ret) 470 goto disable_ldos; 471 472 irq = platform_get_irq(pdev, 0); 473 if (irq < 0) { 474 ret = irq; 475 goto disable_clk; 476 } 477 478 /* Initialize dma_mask and coherent_dma_mask to 32-bits */ 479 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 480 if (ret) 481 goto disable_clk; 482 483 hcd = usb_create_hcd(driver, dev, dev_name(dev)); 484 if (!hcd) { 485 ret = -ENOMEM; 486 goto disable_clk; 487 } 488 489 /* 490 * USB 2.0 roothub is stored in the platform_device. 491 * Swap it with mtk HCD. 492 */ 493 mtk->hcd = platform_get_drvdata(pdev); 494 platform_set_drvdata(pdev, mtk); 495 496 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac"); 497 hcd->regs = devm_ioremap_resource(dev, res); 498 if (IS_ERR(hcd->regs)) { 499 ret = PTR_ERR(hcd->regs); 500 goto put_usb2_hcd; 501 } 502 hcd->rsrc_start = res->start; 503 hcd->rsrc_len = resource_size(res); 504 505 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc"); 506 if (res) { /* ippc register is optional */ 507 mtk->ippc_regs = devm_ioremap_resource(dev, res); 508 if (IS_ERR(mtk->ippc_regs)) { 509 ret = PTR_ERR(mtk->ippc_regs); 510 goto put_usb2_hcd; 511 } 512 mtk->has_ippc = true; 513 } else { 514 mtk->has_ippc = false; 515 } 516 517 device_init_wakeup(dev, true); 518 519 xhci = hcd_to_xhci(hcd); 520 xhci->main_hcd = hcd; 521 522 /* 523 * imod_interval is the interrupt moderation value in nanoseconds. 524 * The increment interval is 8 times as much as that defined in 525 * the xHCI spec on MTK's controller. 526 */ 527 xhci->imod_interval = 5000; 528 device_property_read_u32(dev, "imod-interval-ns", &xhci->imod_interval); 529 530 xhci->shared_hcd = usb_create_shared_hcd(driver, dev, 531 dev_name(dev), hcd); 532 if (!xhci->shared_hcd) { 533 ret = -ENOMEM; 534 goto disable_device_wakeup; 535 } 536 537 ret = usb_add_hcd(hcd, irq, IRQF_SHARED); 538 if (ret) 539 goto put_usb3_hcd; 540 541 if (HCC_MAX_PSA(xhci->hcc_params) >= 4) 542 xhci->shared_hcd->can_do_streams = 1; 543 544 ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED); 545 if (ret) 546 goto dealloc_usb2_hcd; 547 548 return 0; 549 550 dealloc_usb2_hcd: 551 usb_remove_hcd(hcd); 552 553 put_usb3_hcd: 554 xhci_mtk_sch_exit(mtk); 555 usb_put_hcd(xhci->shared_hcd); 556 557 disable_device_wakeup: 558 device_init_wakeup(dev, false); 559 560 put_usb2_hcd: 561 usb_put_hcd(hcd); 562 563 disable_clk: 564 xhci_mtk_clks_disable(mtk); 565 566 disable_ldos: 567 xhci_mtk_ldos_disable(mtk); 568 569 disable_pm: 570 pm_runtime_put_sync(dev); 571 pm_runtime_disable(dev); 572 return ret; 573 } 574 575 static int xhci_mtk_remove(struct platform_device *dev) 576 { 577 struct xhci_hcd_mtk *mtk = platform_get_drvdata(dev); 578 struct usb_hcd *hcd = mtk->hcd; 579 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 580 struct usb_hcd *shared_hcd = xhci->shared_hcd; 581 582 usb_remove_hcd(shared_hcd); 583 xhci->shared_hcd = NULL; 584 device_init_wakeup(&dev->dev, false); 585 586 usb_remove_hcd(hcd); 587 usb_put_hcd(shared_hcd); 588 usb_put_hcd(hcd); 589 xhci_mtk_sch_exit(mtk); 590 xhci_mtk_clks_disable(mtk); 591 xhci_mtk_ldos_disable(mtk); 592 pm_runtime_put_sync(&dev->dev); 593 pm_runtime_disable(&dev->dev); 594 595 return 0; 596 } 597 598 /* 599 * if ip sleep fails, and all clocks are disabled, access register will hang 600 * AHB bus, so stop polling roothubs to avoid regs access on bus suspend. 601 * and no need to check whether ip sleep failed or not; this will cause SPM 602 * to wake up system immediately after system suspend complete if ip sleep 603 * fails, it is what we wanted. 604 */ 605 static int __maybe_unused xhci_mtk_suspend(struct device *dev) 606 { 607 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); 608 struct usb_hcd *hcd = mtk->hcd; 609 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 610 611 xhci_dbg(xhci, "%s: stop port polling\n", __func__); 612 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); 613 del_timer_sync(&hcd->rh_timer); 614 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); 615 del_timer_sync(&xhci->shared_hcd->rh_timer); 616 617 xhci_mtk_host_disable(mtk); 618 xhci_mtk_clks_disable(mtk); 619 usb_wakeup_set(mtk, true); 620 return 0; 621 } 622 623 static int __maybe_unused xhci_mtk_resume(struct device *dev) 624 { 625 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); 626 struct usb_hcd *hcd = mtk->hcd; 627 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 628 629 usb_wakeup_set(mtk, false); 630 xhci_mtk_clks_enable(mtk); 631 xhci_mtk_host_enable(mtk); 632 633 xhci_dbg(xhci, "%s: restart port polling\n", __func__); 634 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); 635 usb_hcd_poll_rh_status(xhci->shared_hcd); 636 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 637 usb_hcd_poll_rh_status(hcd); 638 return 0; 639 } 640 641 static const struct dev_pm_ops xhci_mtk_pm_ops = { 642 SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume) 643 }; 644 #define DEV_PM_OPS IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL 645 646 #ifdef CONFIG_OF 647 static const struct of_device_id mtk_xhci_of_match[] = { 648 { .compatible = "mediatek,mt8173-xhci"}, 649 { .compatible = "mediatek,mtk-xhci"}, 650 { }, 651 }; 652 MODULE_DEVICE_TABLE(of, mtk_xhci_of_match); 653 #endif 654 655 static struct platform_driver mtk_xhci_driver = { 656 .probe = xhci_mtk_probe, 657 .remove = xhci_mtk_remove, 658 .driver = { 659 .name = "xhci-mtk", 660 .pm = DEV_PM_OPS, 661 .of_match_table = of_match_ptr(mtk_xhci_of_match), 662 }, 663 }; 664 MODULE_ALIAS("platform:xhci-mtk"); 665 666 static int __init xhci_mtk_init(void) 667 { 668 xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides); 669 return platform_driver_register(&mtk_xhci_driver); 670 } 671 module_init(xhci_mtk_init); 672 673 static void __exit xhci_mtk_exit(void) 674 { 675 platform_driver_unregister(&mtk_xhci_driver); 676 } 677 module_exit(xhci_mtk_exit); 678 679 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>"); 680 MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver"); 681 MODULE_LICENSE("GPL v2"); 682