1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek xHCI Host Controller Driver 4 * 5 * Copyright (c) 2015 MediaTek Inc. 6 * Author: 7 * Chunfeng Yun <chunfeng.yun@mediatek.com> 8 */ 9 10 #include <linux/dma-mapping.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/pm_wakeirq.h> 19 #include <linux/regmap.h> 20 #include <linux/regulator/consumer.h> 21 22 #include "xhci.h" 23 #include "xhci-mtk.h" 24 25 /* ip_pw_ctrl0 register */ 26 #define CTRL0_IP_SW_RST BIT(0) 27 28 /* ip_pw_ctrl1 register */ 29 #define CTRL1_IP_HOST_PDN BIT(0) 30 31 /* ip_pw_ctrl2 register */ 32 #define CTRL2_IP_DEV_PDN BIT(0) 33 34 /* ip_pw_sts1 register */ 35 #define STS1_IP_SLEEP_STS BIT(30) 36 #define STS1_U3_MAC_RST BIT(16) 37 #define STS1_XHCI_RST BIT(11) 38 #define STS1_SYS125_RST BIT(10) 39 #define STS1_REF_RST BIT(8) 40 #define STS1_SYSPLL_STABLE BIT(0) 41 42 /* ip_xhci_cap register */ 43 #define CAP_U3_PORT_NUM(p) ((p) & 0xff) 44 #define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff) 45 46 /* u3_ctrl_p register */ 47 #define CTRL_U3_PORT_HOST_SEL BIT(2) 48 #define CTRL_U3_PORT_PDN BIT(1) 49 #define CTRL_U3_PORT_DIS BIT(0) 50 51 /* u2_ctrl_p register */ 52 #define CTRL_U2_PORT_HOST_SEL BIT(2) 53 #define CTRL_U2_PORT_PDN BIT(1) 54 #define CTRL_U2_PORT_DIS BIT(0) 55 56 /* u2_phy_pll register */ 57 #define CTRL_U2_FORCE_PLL_STB BIT(28) 58 59 /* xHCI CSR */ 60 #define LS_EOF_CFG 0x930 61 #define LSEOF_OFFSET 0x89 62 63 #define FS_EOF_CFG 0x934 64 #define FSEOF_OFFSET 0x2e 65 66 #define SS_GEN1_EOF_CFG 0x93c 67 #define SSG1EOF_OFFSET 0x78 68 69 #define HFCNTR_CFG 0x944 70 #define ITP_DELTA_CLK (0xa << 1) 71 #define ITP_DELTA_CLK_MASK GENMASK(5, 1) 72 #define FRMCNT_LEV1_RANG (0x12b << 8) 73 #define FRMCNT_LEV1_RANG_MASK GENMASK(19, 8) 74 75 #define SS_GEN2_EOF_CFG 0x990 76 #define SSG2EOF_OFFSET 0x3c 77 78 #define XSEOF_OFFSET_MASK GENMASK(11, 0) 79 80 /* usb remote wakeup registers in syscon */ 81 82 /* mt8173 etc */ 83 #define PERI_WK_CTRL1 0x4 84 #define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */ 85 #define WC1_IS_EN BIT(25) 86 #define WC1_IS_P BIT(6) /* polarity for ip sleep */ 87 88 /* mt8183 */ 89 #define PERI_WK_CTRL0 0x0 90 #define WC0_IS_C(x) ((u32)(((x) & 0xf) << 28)) /* cycle debounce */ 91 #define WC0_IS_P BIT(12) /* polarity */ 92 #define WC0_IS_EN BIT(6) 93 94 /* mt8192 */ 95 #define WC0_SSUSB0_CDEN BIT(6) 96 #define WC0_IS_SPM_EN BIT(1) 97 98 /* mt8195 */ 99 #define PERI_WK_CTRL0_8195 0x04 100 #define WC0_IS_P_95 BIT(30) /* polarity */ 101 #define WC0_IS_C_95(x) ((u32)(((x) & 0x7) << 27)) 102 #define WC0_IS_EN_P3_95 BIT(26) 103 #define WC0_IS_EN_P2_95 BIT(25) 104 #define WC0_IS_EN_P1_95 BIT(24) 105 106 #define PERI_WK_CTRL1_8195 0x20 107 #define WC1_IS_C_95(x) ((u32)(((x) & 0xf) << 28)) 108 #define WC1_IS_P_95 BIT(12) 109 #define WC1_IS_EN_P0_95 BIT(6) 110 111 /* mt2712 etc */ 112 #define PERI_SSUSB_SPM_CTRL 0x0 113 #define SSC_IP_SLEEP_EN BIT(4) 114 #define SSC_SPM_INT_EN BIT(1) 115 116 enum ssusb_uwk_vers { 117 SSUSB_UWK_V1 = 1, 118 SSUSB_UWK_V2, 119 SSUSB_UWK_V1_1 = 101, /* specific revision 1.01 */ 120 SSUSB_UWK_V1_2, /* specific revision 1.2 */ 121 SSUSB_UWK_V1_3, /* mt8195 IP0 */ 122 SSUSB_UWK_V1_4, /* mt8195 IP1 */ 123 SSUSB_UWK_V1_5, /* mt8195 IP2 */ 124 SSUSB_UWK_V1_6, /* mt8195 IP3 */ 125 }; 126 127 /* 128 * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval 129 * is calculated from the frame counter clock 24M, but in fact, the clock 130 * is 48M, add workaround for it. 131 */ 132 static void xhci_mtk_set_frame_interval(struct xhci_hcd_mtk *mtk) 133 { 134 struct device *dev = mtk->dev; 135 struct usb_hcd *hcd = mtk->hcd; 136 u32 value; 137 138 if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci")) 139 return; 140 141 value = readl(hcd->regs + HFCNTR_CFG); 142 value &= ~(ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK); 143 value |= (ITP_DELTA_CLK | FRMCNT_LEV1_RANG); 144 writel(value, hcd->regs + HFCNTR_CFG); 145 146 value = readl(hcd->regs + LS_EOF_CFG); 147 value &= ~XSEOF_OFFSET_MASK; 148 value |= LSEOF_OFFSET; 149 writel(value, hcd->regs + LS_EOF_CFG); 150 151 value = readl(hcd->regs + FS_EOF_CFG); 152 value &= ~XSEOF_OFFSET_MASK; 153 value |= FSEOF_OFFSET; 154 writel(value, hcd->regs + FS_EOF_CFG); 155 156 value = readl(hcd->regs + SS_GEN1_EOF_CFG); 157 value &= ~XSEOF_OFFSET_MASK; 158 value |= SSG1EOF_OFFSET; 159 writel(value, hcd->regs + SS_GEN1_EOF_CFG); 160 161 value = readl(hcd->regs + SS_GEN2_EOF_CFG); 162 value &= ~XSEOF_OFFSET_MASK; 163 value |= SSG2EOF_OFFSET; 164 writel(value, hcd->regs + SS_GEN2_EOF_CFG); 165 } 166 167 static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk) 168 { 169 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; 170 u32 value, check_val; 171 int u3_ports_disabled = 0; 172 int ret; 173 int i; 174 175 if (!mtk->has_ippc) 176 return 0; 177 178 /* power on host ip */ 179 value = readl(&ippc->ip_pw_ctr1); 180 value &= ~CTRL1_IP_HOST_PDN; 181 writel(value, &ippc->ip_pw_ctr1); 182 183 /* power on and enable u3 ports except skipped ones */ 184 for (i = 0; i < mtk->num_u3_ports; i++) { 185 if ((0x1 << i) & mtk->u3p_dis_msk) { 186 u3_ports_disabled++; 187 continue; 188 } 189 190 value = readl(&ippc->u3_ctrl_p[i]); 191 value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS); 192 value |= CTRL_U3_PORT_HOST_SEL; 193 writel(value, &ippc->u3_ctrl_p[i]); 194 } 195 196 /* power on and enable all u2 ports except skipped ones */ 197 for (i = 0; i < mtk->num_u2_ports; i++) { 198 if (BIT(i) & mtk->u2p_dis_msk) 199 continue; 200 201 value = readl(&ippc->u2_ctrl_p[i]); 202 value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS); 203 value |= CTRL_U2_PORT_HOST_SEL; 204 writel(value, &ippc->u2_ctrl_p[i]); 205 } 206 207 /* 208 * wait for clocks to be stable, and clock domains reset to 209 * be inactive after power on and enable ports 210 */ 211 check_val = STS1_SYSPLL_STABLE | STS1_REF_RST | 212 STS1_SYS125_RST | STS1_XHCI_RST; 213 214 if (mtk->num_u3_ports > u3_ports_disabled) 215 check_val |= STS1_U3_MAC_RST; 216 217 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value, 218 (check_val == (value & check_val)), 100, 20000); 219 if (ret) { 220 dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value); 221 return ret; 222 } 223 224 return 0; 225 } 226 227 static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk) 228 { 229 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; 230 u32 value; 231 int ret; 232 int i; 233 234 if (!mtk->has_ippc) 235 return 0; 236 237 /* power down u3 ports except skipped ones */ 238 for (i = 0; i < mtk->num_u3_ports; i++) { 239 if ((0x1 << i) & mtk->u3p_dis_msk) 240 continue; 241 242 value = readl(&ippc->u3_ctrl_p[i]); 243 value |= CTRL_U3_PORT_PDN; 244 writel(value, &ippc->u3_ctrl_p[i]); 245 } 246 247 /* power down all u2 ports except skipped ones */ 248 for (i = 0; i < mtk->num_u2_ports; i++) { 249 if (BIT(i) & mtk->u2p_dis_msk) 250 continue; 251 252 value = readl(&ippc->u2_ctrl_p[i]); 253 value |= CTRL_U2_PORT_PDN; 254 writel(value, &ippc->u2_ctrl_p[i]); 255 } 256 257 /* power down host ip */ 258 value = readl(&ippc->ip_pw_ctr1); 259 value |= CTRL1_IP_HOST_PDN; 260 writel(value, &ippc->ip_pw_ctr1); 261 262 /* wait for host ip to sleep */ 263 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value, 264 (value & STS1_IP_SLEEP_STS), 100, 100000); 265 if (ret) 266 dev_err(mtk->dev, "ip sleep failed!!!\n"); 267 else /* workaound for platforms using low level latch */ 268 usleep_range(100, 200); 269 270 return ret; 271 } 272 273 static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk) 274 { 275 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; 276 u32 value; 277 278 if (!mtk->has_ippc) 279 return 0; 280 281 /* reset whole ip */ 282 value = readl(&ippc->ip_pw_ctr0); 283 value |= CTRL0_IP_SW_RST; 284 writel(value, &ippc->ip_pw_ctr0); 285 udelay(1); 286 value = readl(&ippc->ip_pw_ctr0); 287 value &= ~CTRL0_IP_SW_RST; 288 writel(value, &ippc->ip_pw_ctr0); 289 290 /* 291 * device ip is default power-on in fact 292 * power down device ip, otherwise ip-sleep will fail 293 */ 294 value = readl(&ippc->ip_pw_ctr2); 295 value |= CTRL2_IP_DEV_PDN; 296 writel(value, &ippc->ip_pw_ctr2); 297 298 value = readl(&ippc->ip_xhci_cap); 299 mtk->num_u3_ports = CAP_U3_PORT_NUM(value); 300 mtk->num_u2_ports = CAP_U2_PORT_NUM(value); 301 dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__, 302 mtk->num_u2_ports, mtk->num_u3_ports); 303 304 return xhci_mtk_host_enable(mtk); 305 } 306 307 /* only clocks can be turn off for ip-sleep wakeup mode */ 308 static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable) 309 { 310 u32 reg, msk, val; 311 312 switch (mtk->uwk_vers) { 313 case SSUSB_UWK_V1: 314 reg = mtk->uwk_reg_base + PERI_WK_CTRL1; 315 msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P; 316 val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0; 317 break; 318 case SSUSB_UWK_V1_1: 319 reg = mtk->uwk_reg_base + PERI_WK_CTRL0; 320 msk = WC0_IS_EN | WC0_IS_C(0xf) | WC0_IS_P; 321 val = enable ? (WC0_IS_EN | WC0_IS_C(0x1)) : 0; 322 break; 323 case SSUSB_UWK_V1_2: 324 reg = mtk->uwk_reg_base + PERI_WK_CTRL0; 325 msk = WC0_SSUSB0_CDEN | WC0_IS_SPM_EN; 326 val = enable ? msk : 0; 327 break; 328 case SSUSB_UWK_V1_3: 329 reg = mtk->uwk_reg_base + PERI_WK_CTRL1_8195; 330 msk = WC1_IS_EN_P0_95 | WC1_IS_C_95(0xf) | WC1_IS_P_95; 331 val = enable ? (WC1_IS_EN_P0_95 | WC1_IS_C_95(0x1)) : 0; 332 break; 333 case SSUSB_UWK_V1_4: 334 reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195; 335 msk = WC0_IS_EN_P1_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95; 336 val = enable ? (WC0_IS_EN_P1_95 | WC0_IS_C_95(0x1)) : 0; 337 break; 338 case SSUSB_UWK_V1_5: 339 reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195; 340 msk = WC0_IS_EN_P2_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95; 341 val = enable ? (WC0_IS_EN_P2_95 | WC0_IS_C_95(0x1)) : 0; 342 break; 343 case SSUSB_UWK_V1_6: 344 reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195; 345 msk = WC0_IS_EN_P3_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95; 346 val = enable ? (WC0_IS_EN_P3_95 | WC0_IS_C_95(0x1)) : 0; 347 break; 348 case SSUSB_UWK_V2: 349 reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL; 350 msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN; 351 val = enable ? msk : 0; 352 break; 353 default: 354 return; 355 } 356 regmap_update_bits(mtk->uwk, reg, msk, val); 357 } 358 359 static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk, 360 struct device_node *dn) 361 { 362 struct of_phandle_args args; 363 int ret; 364 365 /* Wakeup function is optional */ 366 mtk->uwk_en = of_property_read_bool(dn, "wakeup-source"); 367 if (!mtk->uwk_en) 368 return 0; 369 370 ret = of_parse_phandle_with_fixed_args(dn, 371 "mediatek,syscon-wakeup", 2, 0, &args); 372 if (ret) 373 return ret; 374 375 mtk->uwk_reg_base = args.args[0]; 376 mtk->uwk_vers = args.args[1]; 377 mtk->uwk = syscon_node_to_regmap(args.np); 378 of_node_put(args.np); 379 dev_info(mtk->dev, "uwk - reg:0x%x, version:%d\n", 380 mtk->uwk_reg_base, mtk->uwk_vers); 381 382 return PTR_ERR_OR_ZERO(mtk->uwk); 383 } 384 385 static void usb_wakeup_set(struct xhci_hcd_mtk *mtk, bool enable) 386 { 387 if (mtk->uwk_en) 388 usb_wakeup_ip_sleep_set(mtk, enable); 389 } 390 391 static int xhci_mtk_clks_get(struct xhci_hcd_mtk *mtk) 392 { 393 struct clk_bulk_data *clks = mtk->clks; 394 395 clks[0].id = "sys_ck"; 396 clks[1].id = "xhci_ck"; 397 clks[2].id = "ref_ck"; 398 clks[3].id = "mcu_ck"; 399 clks[4].id = "dma_ck"; 400 401 return devm_clk_bulk_get_optional(mtk->dev, BULK_CLKS_NUM, clks); 402 } 403 404 static int xhci_mtk_vregs_get(struct xhci_hcd_mtk *mtk) 405 { 406 struct regulator_bulk_data *supplies = mtk->supplies; 407 408 supplies[0].supply = "vbus"; 409 supplies[1].supply = "vusb33"; 410 411 return devm_regulator_bulk_get(mtk->dev, BULK_VREGS_NUM, supplies); 412 } 413 414 static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci) 415 { 416 struct usb_hcd *hcd = xhci_to_hcd(xhci); 417 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd); 418 419 /* 420 * As of now platform drivers don't provide MSI support so we ensure 421 * here that the generic code does not try to make a pci_dev from our 422 * dev struct in order to setup MSI 423 */ 424 xhci->quirks |= XHCI_PLAT; 425 xhci->quirks |= XHCI_MTK_HOST; 426 /* 427 * MTK host controller gives a spurious successful event after a 428 * short transfer. Ignore it. 429 */ 430 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 431 if (mtk->lpm_support) 432 xhci->quirks |= XHCI_LPM_SUPPORT; 433 if (mtk->u2_lpm_disable) 434 xhci->quirks |= XHCI_HW_LPM_DISABLE; 435 436 /* 437 * MTK xHCI 0.96: PSA is 1 by default even if doesn't support stream, 438 * and it's 3 when support it. 439 */ 440 if (xhci->hci_version < 0x100 && HCC_MAX_PSA(xhci->hcc_params) == 4) 441 xhci->quirks |= XHCI_BROKEN_STREAMS; 442 } 443 444 /* called during probe() after chip reset completes */ 445 static int xhci_mtk_setup(struct usb_hcd *hcd) 446 { 447 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd); 448 int ret; 449 450 if (usb_hcd_is_primary_hcd(hcd)) { 451 ret = xhci_mtk_ssusb_config(mtk); 452 if (ret) 453 return ret; 454 455 /* workaround only for mt8195 */ 456 xhci_mtk_set_frame_interval(mtk); 457 } 458 459 ret = xhci_gen_setup(hcd, xhci_mtk_quirks); 460 if (ret) 461 return ret; 462 463 if (usb_hcd_is_primary_hcd(hcd)) 464 ret = xhci_mtk_sch_init(mtk); 465 466 return ret; 467 } 468 469 static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = { 470 .reset = xhci_mtk_setup, 471 .add_endpoint = xhci_mtk_add_ep, 472 .drop_endpoint = xhci_mtk_drop_ep, 473 .check_bandwidth = xhci_mtk_check_bandwidth, 474 .reset_bandwidth = xhci_mtk_reset_bandwidth, 475 }; 476 477 static struct hc_driver __read_mostly xhci_mtk_hc_driver; 478 479 static int xhci_mtk_probe(struct platform_device *pdev) 480 { 481 struct device *dev = &pdev->dev; 482 struct device_node *node = dev->of_node; 483 struct xhci_hcd_mtk *mtk; 484 const struct hc_driver *driver; 485 struct xhci_hcd *xhci; 486 struct resource *res; 487 struct usb_hcd *hcd; 488 int ret = -ENODEV; 489 int wakeup_irq; 490 int irq; 491 492 if (usb_disabled()) 493 return -ENODEV; 494 495 driver = &xhci_mtk_hc_driver; 496 mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL); 497 if (!mtk) 498 return -ENOMEM; 499 500 mtk->dev = dev; 501 502 ret = xhci_mtk_vregs_get(mtk); 503 if (ret) 504 return dev_err_probe(dev, ret, "Failed to get regulators\n"); 505 506 ret = xhci_mtk_clks_get(mtk); 507 if (ret) 508 return ret; 509 510 irq = platform_get_irq_byname_optional(pdev, "host"); 511 if (irq < 0) { 512 if (irq == -EPROBE_DEFER) 513 return irq; 514 515 /* for backward compatibility */ 516 irq = platform_get_irq(pdev, 0); 517 if (irq < 0) 518 return irq; 519 } 520 521 wakeup_irq = platform_get_irq_byname_optional(pdev, "wakeup"); 522 if (wakeup_irq == -EPROBE_DEFER) 523 return wakeup_irq; 524 525 mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable"); 526 mtk->u2_lpm_disable = of_property_read_bool(node, "usb2-lpm-disable"); 527 /* optional property, ignore the error if it does not exist */ 528 of_property_read_u32(node, "mediatek,u3p-dis-msk", 529 &mtk->u3p_dis_msk); 530 of_property_read_u32(node, "mediatek,u2p-dis-msk", 531 &mtk->u2p_dis_msk); 532 533 ret = usb_wakeup_of_property_parse(mtk, node); 534 if (ret) { 535 dev_err(dev, "failed to parse uwk property\n"); 536 return ret; 537 } 538 539 pm_runtime_set_active(dev); 540 pm_runtime_use_autosuspend(dev); 541 pm_runtime_set_autosuspend_delay(dev, 4000); 542 pm_runtime_enable(dev); 543 pm_runtime_get_sync(dev); 544 545 ret = regulator_bulk_enable(BULK_VREGS_NUM, mtk->supplies); 546 if (ret) 547 goto disable_pm; 548 549 ret = clk_bulk_prepare_enable(BULK_CLKS_NUM, mtk->clks); 550 if (ret) 551 goto disable_ldos; 552 553 hcd = usb_create_hcd(driver, dev, dev_name(dev)); 554 if (!hcd) { 555 ret = -ENOMEM; 556 goto disable_clk; 557 } 558 559 /* 560 * USB 2.0 roothub is stored in the platform_device. 561 * Swap it with mtk HCD. 562 */ 563 mtk->hcd = platform_get_drvdata(pdev); 564 platform_set_drvdata(pdev, mtk); 565 566 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac"); 567 hcd->regs = devm_ioremap_resource(dev, res); 568 if (IS_ERR(hcd->regs)) { 569 ret = PTR_ERR(hcd->regs); 570 goto put_usb2_hcd; 571 } 572 hcd->rsrc_start = res->start; 573 hcd->rsrc_len = resource_size(res); 574 575 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc"); 576 if (res) { /* ippc register is optional */ 577 mtk->ippc_regs = devm_ioremap_resource(dev, res); 578 if (IS_ERR(mtk->ippc_regs)) { 579 ret = PTR_ERR(mtk->ippc_regs); 580 goto put_usb2_hcd; 581 } 582 mtk->has_ippc = true; 583 } 584 585 device_init_wakeup(dev, true); 586 587 xhci = hcd_to_xhci(hcd); 588 xhci->main_hcd = hcd; 589 590 /* 591 * imod_interval is the interrupt moderation value in nanoseconds. 592 * The increment interval is 8 times as much as that defined in 593 * the xHCI spec on MTK's controller. 594 */ 595 xhci->imod_interval = 5000; 596 device_property_read_u32(dev, "imod-interval-ns", &xhci->imod_interval); 597 598 xhci->shared_hcd = usb_create_shared_hcd(driver, dev, 599 dev_name(dev), hcd); 600 if (!xhci->shared_hcd) { 601 ret = -ENOMEM; 602 goto disable_device_wakeup; 603 } 604 605 ret = usb_add_hcd(hcd, irq, IRQF_SHARED); 606 if (ret) 607 goto put_usb3_hcd; 608 609 if (HCC_MAX_PSA(xhci->hcc_params) >= 4 && 610 !(xhci->quirks & XHCI_BROKEN_STREAMS)) 611 xhci->shared_hcd->can_do_streams = 1; 612 613 ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED); 614 if (ret) 615 goto dealloc_usb2_hcd; 616 617 if (wakeup_irq > 0) { 618 ret = dev_pm_set_dedicated_wake_irq_reverse(dev, wakeup_irq); 619 if (ret) { 620 dev_err(dev, "set wakeup irq %d failed\n", wakeup_irq); 621 goto dealloc_usb3_hcd; 622 } 623 dev_info(dev, "wakeup irq %d\n", wakeup_irq); 624 } 625 626 device_enable_async_suspend(dev); 627 pm_runtime_mark_last_busy(dev); 628 pm_runtime_put_autosuspend(dev); 629 pm_runtime_forbid(dev); 630 631 return 0; 632 633 dealloc_usb3_hcd: 634 usb_remove_hcd(xhci->shared_hcd); 635 xhci->shared_hcd = NULL; 636 637 dealloc_usb2_hcd: 638 usb_remove_hcd(hcd); 639 640 put_usb3_hcd: 641 xhci_mtk_sch_exit(mtk); 642 usb_put_hcd(xhci->shared_hcd); 643 644 disable_device_wakeup: 645 device_init_wakeup(dev, false); 646 647 put_usb2_hcd: 648 usb_put_hcd(hcd); 649 650 disable_clk: 651 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks); 652 653 disable_ldos: 654 regulator_bulk_disable(BULK_VREGS_NUM, mtk->supplies); 655 656 disable_pm: 657 pm_runtime_put_noidle(dev); 658 pm_runtime_disable(dev); 659 return ret; 660 } 661 662 static int xhci_mtk_remove(struct platform_device *pdev) 663 { 664 struct xhci_hcd_mtk *mtk = platform_get_drvdata(pdev); 665 struct usb_hcd *hcd = mtk->hcd; 666 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 667 struct usb_hcd *shared_hcd = xhci->shared_hcd; 668 struct device *dev = &pdev->dev; 669 670 pm_runtime_get_sync(dev); 671 xhci->xhc_state |= XHCI_STATE_REMOVING; 672 dev_pm_clear_wake_irq(dev); 673 device_init_wakeup(dev, false); 674 675 usb_remove_hcd(shared_hcd); 676 xhci->shared_hcd = NULL; 677 usb_remove_hcd(hcd); 678 usb_put_hcd(shared_hcd); 679 usb_put_hcd(hcd); 680 xhci_mtk_sch_exit(mtk); 681 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks); 682 regulator_bulk_disable(BULK_VREGS_NUM, mtk->supplies); 683 684 pm_runtime_disable(dev); 685 pm_runtime_put_noidle(dev); 686 pm_runtime_set_suspended(dev); 687 688 return 0; 689 } 690 691 static int __maybe_unused xhci_mtk_suspend(struct device *dev) 692 { 693 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); 694 struct usb_hcd *hcd = mtk->hcd; 695 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 696 int ret; 697 698 xhci_dbg(xhci, "%s: stop port polling\n", __func__); 699 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); 700 del_timer_sync(&hcd->rh_timer); 701 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); 702 del_timer_sync(&xhci->shared_hcd->rh_timer); 703 704 ret = xhci_mtk_host_disable(mtk); 705 if (ret) 706 goto restart_poll_rh; 707 708 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks); 709 usb_wakeup_set(mtk, true); 710 return 0; 711 712 restart_poll_rh: 713 xhci_dbg(xhci, "%s: restart port polling\n", __func__); 714 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); 715 usb_hcd_poll_rh_status(xhci->shared_hcd); 716 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 717 usb_hcd_poll_rh_status(hcd); 718 return ret; 719 } 720 721 static int __maybe_unused xhci_mtk_resume(struct device *dev) 722 { 723 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); 724 struct usb_hcd *hcd = mtk->hcd; 725 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 726 int ret; 727 728 usb_wakeup_set(mtk, false); 729 ret = clk_bulk_prepare_enable(BULK_CLKS_NUM, mtk->clks); 730 if (ret) 731 goto enable_wakeup; 732 733 ret = xhci_mtk_host_enable(mtk); 734 if (ret) 735 goto disable_clks; 736 737 xhci_dbg(xhci, "%s: restart port polling\n", __func__); 738 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); 739 usb_hcd_poll_rh_status(xhci->shared_hcd); 740 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 741 usb_hcd_poll_rh_status(hcd); 742 return 0; 743 744 disable_clks: 745 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks); 746 enable_wakeup: 747 usb_wakeup_set(mtk, true); 748 return ret; 749 } 750 751 static int __maybe_unused xhci_mtk_runtime_suspend(struct device *dev) 752 { 753 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); 754 struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd); 755 int ret = 0; 756 757 if (xhci->xhc_state) 758 return -ESHUTDOWN; 759 760 if (device_may_wakeup(dev)) 761 ret = xhci_mtk_suspend(dev); 762 763 /* -EBUSY: let PM automatically reschedule another autosuspend */ 764 return ret ? -EBUSY : 0; 765 } 766 767 static int __maybe_unused xhci_mtk_runtime_resume(struct device *dev) 768 { 769 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); 770 struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd); 771 int ret = 0; 772 773 if (xhci->xhc_state) 774 return -ESHUTDOWN; 775 776 if (device_may_wakeup(dev)) 777 ret = xhci_mtk_resume(dev); 778 779 return ret; 780 } 781 782 static const struct dev_pm_ops xhci_mtk_pm_ops = { 783 SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume) 784 SET_RUNTIME_PM_OPS(xhci_mtk_runtime_suspend, 785 xhci_mtk_runtime_resume, NULL) 786 }; 787 788 #define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL) 789 790 static const struct of_device_id mtk_xhci_of_match[] = { 791 { .compatible = "mediatek,mt8173-xhci"}, 792 { .compatible = "mediatek,mt8195-xhci"}, 793 { .compatible = "mediatek,mtk-xhci"}, 794 { }, 795 }; 796 MODULE_DEVICE_TABLE(of, mtk_xhci_of_match); 797 798 static struct platform_driver mtk_xhci_driver = { 799 .probe = xhci_mtk_probe, 800 .remove = xhci_mtk_remove, 801 .driver = { 802 .name = "xhci-mtk", 803 .pm = DEV_PM_OPS, 804 .of_match_table = mtk_xhci_of_match, 805 }, 806 }; 807 808 static int __init xhci_mtk_init(void) 809 { 810 xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides); 811 return platform_driver_register(&mtk_xhci_driver); 812 } 813 module_init(xhci_mtk_init); 814 815 static void __exit xhci_mtk_exit(void) 816 { 817 platform_driver_unregister(&mtk_xhci_driver); 818 } 819 module_exit(xhci_mtk_exit); 820 821 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>"); 822 MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver"); 823 MODULE_LICENSE("GPL v2"); 824