1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek xHCI Host Controller Driver 4 * 5 * Copyright (c) 2015 MediaTek Inc. 6 * Author: 7 * Chunfeng Yun <chunfeng.yun@mediatek.com> 8 */ 9 10 #include <linux/dma-mapping.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/pm_wakeirq.h> 19 #include <linux/regmap.h> 20 #include <linux/regulator/consumer.h> 21 22 #include "xhci.h" 23 #include "xhci-mtk.h" 24 25 /* ip_pw_ctrl0 register */ 26 #define CTRL0_IP_SW_RST BIT(0) 27 28 /* ip_pw_ctrl1 register */ 29 #define CTRL1_IP_HOST_PDN BIT(0) 30 31 /* ip_pw_ctrl2 register */ 32 #define CTRL2_IP_DEV_PDN BIT(0) 33 34 /* ip_pw_sts1 register */ 35 #define STS1_IP_SLEEP_STS BIT(30) 36 #define STS1_U3_MAC_RST BIT(16) 37 #define STS1_XHCI_RST BIT(11) 38 #define STS1_SYS125_RST BIT(10) 39 #define STS1_REF_RST BIT(8) 40 #define STS1_SYSPLL_STABLE BIT(0) 41 42 /* ip_xhci_cap register */ 43 #define CAP_U3_PORT_NUM(p) ((p) & 0xff) 44 #define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff) 45 46 /* u3_ctrl_p register */ 47 #define CTRL_U3_PORT_HOST_SEL BIT(2) 48 #define CTRL_U3_PORT_PDN BIT(1) 49 #define CTRL_U3_PORT_DIS BIT(0) 50 51 /* u2_ctrl_p register */ 52 #define CTRL_U2_PORT_HOST_SEL BIT(2) 53 #define CTRL_U2_PORT_PDN BIT(1) 54 #define CTRL_U2_PORT_DIS BIT(0) 55 56 /* u2_phy_pll register */ 57 #define CTRL_U2_FORCE_PLL_STB BIT(28) 58 59 /* xHCI CSR */ 60 #define LS_EOF_CFG 0x930 61 #define LSEOF_OFFSET 0x89 62 63 #define FS_EOF_CFG 0x934 64 #define FSEOF_OFFSET 0x2e 65 66 #define SS_GEN1_EOF_CFG 0x93c 67 #define SSG1EOF_OFFSET 0x78 68 69 #define HFCNTR_CFG 0x944 70 #define ITP_DELTA_CLK (0xa << 1) 71 #define ITP_DELTA_CLK_MASK GENMASK(5, 1) 72 #define FRMCNT_LEV1_RANG (0x12b << 8) 73 #define FRMCNT_LEV1_RANG_MASK GENMASK(19, 8) 74 75 #define SS_GEN2_EOF_CFG 0x990 76 #define SSG2EOF_OFFSET 0x3c 77 78 #define XSEOF_OFFSET_MASK GENMASK(11, 0) 79 80 /* usb remote wakeup registers in syscon */ 81 82 /* mt8173 etc */ 83 #define PERI_WK_CTRL1 0x4 84 #define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */ 85 #define WC1_IS_EN BIT(25) 86 #define WC1_IS_P BIT(6) /* polarity for ip sleep */ 87 88 /* mt8183 */ 89 #define PERI_WK_CTRL0 0x0 90 #define WC0_IS_C(x) ((u32)(((x) & 0xf) << 28)) /* cycle debounce */ 91 #define WC0_IS_P BIT(12) /* polarity */ 92 #define WC0_IS_EN BIT(6) 93 94 /* mt8192 */ 95 #define WC0_SSUSB0_CDEN BIT(6) 96 #define WC0_IS_SPM_EN BIT(1) 97 98 /* mt2712 etc */ 99 #define PERI_SSUSB_SPM_CTRL 0x0 100 #define SSC_IP_SLEEP_EN BIT(4) 101 #define SSC_SPM_INT_EN BIT(1) 102 103 enum ssusb_uwk_vers { 104 SSUSB_UWK_V1 = 1, 105 SSUSB_UWK_V2, 106 SSUSB_UWK_V1_1 = 101, /* specific revision 1.01 */ 107 SSUSB_UWK_V1_2, /* specific revision 1.2 */ 108 }; 109 110 /* 111 * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval 112 * is calculated from the frame counter clock 24M, but in fact, the clock 113 * is 48M, add workaround for it. 114 */ 115 static void xhci_mtk_set_frame_interval(struct xhci_hcd_mtk *mtk) 116 { 117 struct device *dev = mtk->dev; 118 struct usb_hcd *hcd = mtk->hcd; 119 u32 value; 120 121 if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci")) 122 return; 123 124 value = readl(hcd->regs + HFCNTR_CFG); 125 value &= ~(ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK); 126 value |= (ITP_DELTA_CLK | FRMCNT_LEV1_RANG); 127 writel(value, hcd->regs + HFCNTR_CFG); 128 129 value = readl(hcd->regs + LS_EOF_CFG); 130 value &= ~XSEOF_OFFSET_MASK; 131 value |= LSEOF_OFFSET; 132 writel(value, hcd->regs + LS_EOF_CFG); 133 134 value = readl(hcd->regs + FS_EOF_CFG); 135 value &= ~XSEOF_OFFSET_MASK; 136 value |= FSEOF_OFFSET; 137 writel(value, hcd->regs + FS_EOF_CFG); 138 139 value = readl(hcd->regs + SS_GEN1_EOF_CFG); 140 value &= ~XSEOF_OFFSET_MASK; 141 value |= SSG1EOF_OFFSET; 142 writel(value, hcd->regs + SS_GEN1_EOF_CFG); 143 144 value = readl(hcd->regs + SS_GEN2_EOF_CFG); 145 value &= ~XSEOF_OFFSET_MASK; 146 value |= SSG2EOF_OFFSET; 147 writel(value, hcd->regs + SS_GEN2_EOF_CFG); 148 } 149 150 static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk) 151 { 152 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; 153 u32 value, check_val; 154 int u3_ports_disabled = 0; 155 int ret; 156 int i; 157 158 if (!mtk->has_ippc) 159 return 0; 160 161 /* power on host ip */ 162 value = readl(&ippc->ip_pw_ctr1); 163 value &= ~CTRL1_IP_HOST_PDN; 164 writel(value, &ippc->ip_pw_ctr1); 165 166 /* power on and enable u3 ports except skipped ones */ 167 for (i = 0; i < mtk->num_u3_ports; i++) { 168 if ((0x1 << i) & mtk->u3p_dis_msk) { 169 u3_ports_disabled++; 170 continue; 171 } 172 173 value = readl(&ippc->u3_ctrl_p[i]); 174 value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS); 175 value |= CTRL_U3_PORT_HOST_SEL; 176 writel(value, &ippc->u3_ctrl_p[i]); 177 } 178 179 /* power on and enable all u2 ports except skipped ones */ 180 for (i = 0; i < mtk->num_u2_ports; i++) { 181 if (BIT(i) & mtk->u2p_dis_msk) 182 continue; 183 184 value = readl(&ippc->u2_ctrl_p[i]); 185 value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS); 186 value |= CTRL_U2_PORT_HOST_SEL; 187 writel(value, &ippc->u2_ctrl_p[i]); 188 } 189 190 /* 191 * wait for clocks to be stable, and clock domains reset to 192 * be inactive after power on and enable ports 193 */ 194 check_val = STS1_SYSPLL_STABLE | STS1_REF_RST | 195 STS1_SYS125_RST | STS1_XHCI_RST; 196 197 if (mtk->num_u3_ports > u3_ports_disabled) 198 check_val |= STS1_U3_MAC_RST; 199 200 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value, 201 (check_val == (value & check_val)), 100, 20000); 202 if (ret) { 203 dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value); 204 return ret; 205 } 206 207 return 0; 208 } 209 210 static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk) 211 { 212 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; 213 u32 value; 214 int ret; 215 int i; 216 217 if (!mtk->has_ippc) 218 return 0; 219 220 /* power down u3 ports except skipped ones */ 221 for (i = 0; i < mtk->num_u3_ports; i++) { 222 if ((0x1 << i) & mtk->u3p_dis_msk) 223 continue; 224 225 value = readl(&ippc->u3_ctrl_p[i]); 226 value |= CTRL_U3_PORT_PDN; 227 writel(value, &ippc->u3_ctrl_p[i]); 228 } 229 230 /* power down all u2 ports except skipped ones */ 231 for (i = 0; i < mtk->num_u2_ports; i++) { 232 if (BIT(i) & mtk->u2p_dis_msk) 233 continue; 234 235 value = readl(&ippc->u2_ctrl_p[i]); 236 value |= CTRL_U2_PORT_PDN; 237 writel(value, &ippc->u2_ctrl_p[i]); 238 } 239 240 /* power down host ip */ 241 value = readl(&ippc->ip_pw_ctr1); 242 value |= CTRL1_IP_HOST_PDN; 243 writel(value, &ippc->ip_pw_ctr1); 244 245 /* wait for host ip to sleep */ 246 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value, 247 (value & STS1_IP_SLEEP_STS), 100, 100000); 248 if (ret) { 249 dev_err(mtk->dev, "ip sleep failed!!!\n"); 250 return ret; 251 } 252 return 0; 253 } 254 255 static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk) 256 { 257 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; 258 u32 value; 259 260 if (!mtk->has_ippc) 261 return 0; 262 263 /* reset whole ip */ 264 value = readl(&ippc->ip_pw_ctr0); 265 value |= CTRL0_IP_SW_RST; 266 writel(value, &ippc->ip_pw_ctr0); 267 udelay(1); 268 value = readl(&ippc->ip_pw_ctr0); 269 value &= ~CTRL0_IP_SW_RST; 270 writel(value, &ippc->ip_pw_ctr0); 271 272 /* 273 * device ip is default power-on in fact 274 * power down device ip, otherwise ip-sleep will fail 275 */ 276 value = readl(&ippc->ip_pw_ctr2); 277 value |= CTRL2_IP_DEV_PDN; 278 writel(value, &ippc->ip_pw_ctr2); 279 280 value = readl(&ippc->ip_xhci_cap); 281 mtk->num_u3_ports = CAP_U3_PORT_NUM(value); 282 mtk->num_u2_ports = CAP_U2_PORT_NUM(value); 283 dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__, 284 mtk->num_u2_ports, mtk->num_u3_ports); 285 286 return xhci_mtk_host_enable(mtk); 287 } 288 289 /* only clocks can be turn off for ip-sleep wakeup mode */ 290 static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable) 291 { 292 u32 reg, msk, val; 293 294 switch (mtk->uwk_vers) { 295 case SSUSB_UWK_V1: 296 reg = mtk->uwk_reg_base + PERI_WK_CTRL1; 297 msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P; 298 val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0; 299 break; 300 case SSUSB_UWK_V1_1: 301 reg = mtk->uwk_reg_base + PERI_WK_CTRL0; 302 msk = WC0_IS_EN | WC0_IS_C(0xf) | WC0_IS_P; 303 val = enable ? (WC0_IS_EN | WC0_IS_C(0x8)) : 0; 304 break; 305 case SSUSB_UWK_V1_2: 306 reg = mtk->uwk_reg_base + PERI_WK_CTRL0; 307 msk = WC0_SSUSB0_CDEN | WC0_IS_SPM_EN; 308 val = enable ? msk : 0; 309 break; 310 case SSUSB_UWK_V2: 311 reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL; 312 msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN; 313 val = enable ? msk : 0; 314 break; 315 default: 316 return; 317 } 318 regmap_update_bits(mtk->uwk, reg, msk, val); 319 } 320 321 static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk, 322 struct device_node *dn) 323 { 324 struct of_phandle_args args; 325 int ret; 326 327 /* Wakeup function is optional */ 328 mtk->uwk_en = of_property_read_bool(dn, "wakeup-source"); 329 if (!mtk->uwk_en) 330 return 0; 331 332 ret = of_parse_phandle_with_fixed_args(dn, 333 "mediatek,syscon-wakeup", 2, 0, &args); 334 if (ret) 335 return ret; 336 337 mtk->uwk_reg_base = args.args[0]; 338 mtk->uwk_vers = args.args[1]; 339 mtk->uwk = syscon_node_to_regmap(args.np); 340 of_node_put(args.np); 341 dev_info(mtk->dev, "uwk - reg:0x%x, version:%d\n", 342 mtk->uwk_reg_base, mtk->uwk_vers); 343 344 return PTR_ERR_OR_ZERO(mtk->uwk); 345 } 346 347 static void usb_wakeup_set(struct xhci_hcd_mtk *mtk, bool enable) 348 { 349 if (mtk->uwk_en) 350 usb_wakeup_ip_sleep_set(mtk, enable); 351 } 352 353 static int xhci_mtk_clks_get(struct xhci_hcd_mtk *mtk) 354 { 355 struct clk_bulk_data *clks = mtk->clks; 356 357 clks[0].id = "sys_ck"; 358 clks[1].id = "xhci_ck"; 359 clks[2].id = "ref_ck"; 360 clks[3].id = "mcu_ck"; 361 clks[4].id = "dma_ck"; 362 363 return devm_clk_bulk_get_optional(mtk->dev, BULK_CLKS_NUM, clks); 364 } 365 366 static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk) 367 { 368 int ret; 369 370 ret = regulator_enable(mtk->vbus); 371 if (ret) { 372 dev_err(mtk->dev, "failed to enable vbus\n"); 373 return ret; 374 } 375 376 ret = regulator_enable(mtk->vusb33); 377 if (ret) { 378 dev_err(mtk->dev, "failed to enable vusb33\n"); 379 regulator_disable(mtk->vbus); 380 return ret; 381 } 382 return 0; 383 } 384 385 static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk) 386 { 387 regulator_disable(mtk->vbus); 388 regulator_disable(mtk->vusb33); 389 } 390 391 static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci) 392 { 393 struct usb_hcd *hcd = xhci_to_hcd(xhci); 394 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd); 395 396 /* 397 * As of now platform drivers don't provide MSI support so we ensure 398 * here that the generic code does not try to make a pci_dev from our 399 * dev struct in order to setup MSI 400 */ 401 xhci->quirks |= XHCI_PLAT; 402 xhci->quirks |= XHCI_MTK_HOST; 403 /* 404 * MTK host controller gives a spurious successful event after a 405 * short transfer. Ignore it. 406 */ 407 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 408 if (mtk->lpm_support) 409 xhci->quirks |= XHCI_LPM_SUPPORT; 410 if (mtk->u2_lpm_disable) 411 xhci->quirks |= XHCI_HW_LPM_DISABLE; 412 413 /* 414 * MTK xHCI 0.96: PSA is 1 by default even if doesn't support stream, 415 * and it's 3 when support it. 416 */ 417 if (xhci->hci_version < 0x100 && HCC_MAX_PSA(xhci->hcc_params) == 4) 418 xhci->quirks |= XHCI_BROKEN_STREAMS; 419 } 420 421 /* called during probe() after chip reset completes */ 422 static int xhci_mtk_setup(struct usb_hcd *hcd) 423 { 424 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd); 425 int ret; 426 427 if (usb_hcd_is_primary_hcd(hcd)) { 428 ret = xhci_mtk_ssusb_config(mtk); 429 if (ret) 430 return ret; 431 432 /* workaround only for mt8195 */ 433 xhci_mtk_set_frame_interval(mtk); 434 } 435 436 ret = xhci_gen_setup(hcd, xhci_mtk_quirks); 437 if (ret) 438 return ret; 439 440 if (usb_hcd_is_primary_hcd(hcd)) { 441 ret = xhci_mtk_sch_init(mtk); 442 if (ret) 443 return ret; 444 } 445 446 return ret; 447 } 448 449 static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = { 450 .reset = xhci_mtk_setup, 451 .add_endpoint = xhci_mtk_add_ep, 452 .drop_endpoint = xhci_mtk_drop_ep, 453 .check_bandwidth = xhci_mtk_check_bandwidth, 454 .reset_bandwidth = xhci_mtk_reset_bandwidth, 455 }; 456 457 static struct hc_driver __read_mostly xhci_mtk_hc_driver; 458 459 static int xhci_mtk_probe(struct platform_device *pdev) 460 { 461 struct device *dev = &pdev->dev; 462 struct device_node *node = dev->of_node; 463 struct xhci_hcd_mtk *mtk; 464 const struct hc_driver *driver; 465 struct xhci_hcd *xhci; 466 struct resource *res; 467 struct usb_hcd *hcd; 468 int ret = -ENODEV; 469 int wakeup_irq; 470 int irq; 471 472 if (usb_disabled()) 473 return -ENODEV; 474 475 driver = &xhci_mtk_hc_driver; 476 mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL); 477 if (!mtk) 478 return -ENOMEM; 479 480 mtk->dev = dev; 481 mtk->vbus = devm_regulator_get(dev, "vbus"); 482 if (IS_ERR(mtk->vbus)) { 483 dev_err(dev, "fail to get vbus\n"); 484 return PTR_ERR(mtk->vbus); 485 } 486 487 mtk->vusb33 = devm_regulator_get(dev, "vusb33"); 488 if (IS_ERR(mtk->vusb33)) { 489 dev_err(dev, "fail to get vusb33\n"); 490 return PTR_ERR(mtk->vusb33); 491 } 492 493 ret = xhci_mtk_clks_get(mtk); 494 if (ret) 495 return ret; 496 497 irq = platform_get_irq_byname_optional(pdev, "host"); 498 if (irq < 0) { 499 if (irq == -EPROBE_DEFER) 500 return irq; 501 502 /* for backward compatibility */ 503 irq = platform_get_irq(pdev, 0); 504 if (irq < 0) 505 return irq; 506 } 507 508 wakeup_irq = platform_get_irq_byname_optional(pdev, "wakeup"); 509 if (wakeup_irq == -EPROBE_DEFER) 510 return wakeup_irq; 511 512 mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable"); 513 mtk->u2_lpm_disable = of_property_read_bool(node, "usb2-lpm-disable"); 514 /* optional property, ignore the error if it does not exist */ 515 of_property_read_u32(node, "mediatek,u3p-dis-msk", 516 &mtk->u3p_dis_msk); 517 of_property_read_u32(node, "mediatek,u2p-dis-msk", 518 &mtk->u2p_dis_msk); 519 520 ret = usb_wakeup_of_property_parse(mtk, node); 521 if (ret) { 522 dev_err(dev, "failed to parse uwk property\n"); 523 return ret; 524 } 525 526 pm_runtime_set_active(dev); 527 pm_runtime_use_autosuspend(dev); 528 pm_runtime_set_autosuspend_delay(dev, 4000); 529 pm_runtime_enable(dev); 530 pm_runtime_get_sync(dev); 531 532 ret = xhci_mtk_ldos_enable(mtk); 533 if (ret) 534 goto disable_pm; 535 536 ret = clk_bulk_prepare_enable(BULK_CLKS_NUM, mtk->clks); 537 if (ret) 538 goto disable_ldos; 539 540 hcd = usb_create_hcd(driver, dev, dev_name(dev)); 541 if (!hcd) { 542 ret = -ENOMEM; 543 goto disable_clk; 544 } 545 546 /* 547 * USB 2.0 roothub is stored in the platform_device. 548 * Swap it with mtk HCD. 549 */ 550 mtk->hcd = platform_get_drvdata(pdev); 551 platform_set_drvdata(pdev, mtk); 552 553 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac"); 554 hcd->regs = devm_ioremap_resource(dev, res); 555 if (IS_ERR(hcd->regs)) { 556 ret = PTR_ERR(hcd->regs); 557 goto put_usb2_hcd; 558 } 559 hcd->rsrc_start = res->start; 560 hcd->rsrc_len = resource_size(res); 561 562 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc"); 563 if (res) { /* ippc register is optional */ 564 mtk->ippc_regs = devm_ioremap_resource(dev, res); 565 if (IS_ERR(mtk->ippc_regs)) { 566 ret = PTR_ERR(mtk->ippc_regs); 567 goto put_usb2_hcd; 568 } 569 mtk->has_ippc = true; 570 } 571 572 device_init_wakeup(dev, true); 573 574 xhci = hcd_to_xhci(hcd); 575 xhci->main_hcd = hcd; 576 577 /* 578 * imod_interval is the interrupt moderation value in nanoseconds. 579 * The increment interval is 8 times as much as that defined in 580 * the xHCI spec on MTK's controller. 581 */ 582 xhci->imod_interval = 5000; 583 device_property_read_u32(dev, "imod-interval-ns", &xhci->imod_interval); 584 585 xhci->shared_hcd = usb_create_shared_hcd(driver, dev, 586 dev_name(dev), hcd); 587 if (!xhci->shared_hcd) { 588 ret = -ENOMEM; 589 goto disable_device_wakeup; 590 } 591 592 ret = usb_add_hcd(hcd, irq, IRQF_SHARED); 593 if (ret) 594 goto put_usb3_hcd; 595 596 if (HCC_MAX_PSA(xhci->hcc_params) >= 4 && 597 !(xhci->quirks & XHCI_BROKEN_STREAMS)) 598 xhci->shared_hcd->can_do_streams = 1; 599 600 ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED); 601 if (ret) 602 goto dealloc_usb2_hcd; 603 604 if (wakeup_irq > 0) { 605 ret = dev_pm_set_dedicated_wake_irq_reverse(dev, wakeup_irq); 606 if (ret) { 607 dev_err(dev, "set wakeup irq %d failed\n", wakeup_irq); 608 goto dealloc_usb3_hcd; 609 } 610 dev_info(dev, "wakeup irq %d\n", wakeup_irq); 611 } 612 613 device_enable_async_suspend(dev); 614 pm_runtime_mark_last_busy(dev); 615 pm_runtime_put_autosuspend(dev); 616 pm_runtime_forbid(dev); 617 618 return 0; 619 620 dealloc_usb3_hcd: 621 usb_remove_hcd(xhci->shared_hcd); 622 xhci->shared_hcd = NULL; 623 624 dealloc_usb2_hcd: 625 usb_remove_hcd(hcd); 626 627 put_usb3_hcd: 628 xhci_mtk_sch_exit(mtk); 629 usb_put_hcd(xhci->shared_hcd); 630 631 disable_device_wakeup: 632 device_init_wakeup(dev, false); 633 634 put_usb2_hcd: 635 usb_put_hcd(hcd); 636 637 disable_clk: 638 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks); 639 640 disable_ldos: 641 xhci_mtk_ldos_disable(mtk); 642 643 disable_pm: 644 pm_runtime_put_noidle(dev); 645 pm_runtime_disable(dev); 646 return ret; 647 } 648 649 static int xhci_mtk_remove(struct platform_device *pdev) 650 { 651 struct xhci_hcd_mtk *mtk = platform_get_drvdata(pdev); 652 struct usb_hcd *hcd = mtk->hcd; 653 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 654 struct usb_hcd *shared_hcd = xhci->shared_hcd; 655 struct device *dev = &pdev->dev; 656 657 pm_runtime_get_sync(dev); 658 xhci->xhc_state |= XHCI_STATE_REMOVING; 659 dev_pm_clear_wake_irq(dev); 660 device_init_wakeup(dev, false); 661 662 usb_remove_hcd(shared_hcd); 663 xhci->shared_hcd = NULL; 664 usb_remove_hcd(hcd); 665 usb_put_hcd(shared_hcd); 666 usb_put_hcd(hcd); 667 xhci_mtk_sch_exit(mtk); 668 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks); 669 xhci_mtk_ldos_disable(mtk); 670 671 pm_runtime_disable(dev); 672 pm_runtime_put_noidle(dev); 673 pm_runtime_set_suspended(dev); 674 675 return 0; 676 } 677 678 static int __maybe_unused xhci_mtk_suspend(struct device *dev) 679 { 680 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); 681 struct usb_hcd *hcd = mtk->hcd; 682 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 683 int ret; 684 685 xhci_dbg(xhci, "%s: stop port polling\n", __func__); 686 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); 687 del_timer_sync(&hcd->rh_timer); 688 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); 689 del_timer_sync(&xhci->shared_hcd->rh_timer); 690 691 ret = xhci_mtk_host_disable(mtk); 692 if (ret) 693 goto restart_poll_rh; 694 695 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks); 696 usb_wakeup_set(mtk, true); 697 return 0; 698 699 restart_poll_rh: 700 xhci_dbg(xhci, "%s: restart port polling\n", __func__); 701 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); 702 usb_hcd_poll_rh_status(xhci->shared_hcd); 703 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 704 usb_hcd_poll_rh_status(hcd); 705 return ret; 706 } 707 708 static int __maybe_unused xhci_mtk_resume(struct device *dev) 709 { 710 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); 711 struct usb_hcd *hcd = mtk->hcd; 712 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 713 int ret; 714 715 usb_wakeup_set(mtk, false); 716 ret = clk_bulk_prepare_enable(BULK_CLKS_NUM, mtk->clks); 717 if (ret) 718 goto enable_wakeup; 719 720 ret = xhci_mtk_host_enable(mtk); 721 if (ret) 722 goto disable_clks; 723 724 xhci_dbg(xhci, "%s: restart port polling\n", __func__); 725 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); 726 usb_hcd_poll_rh_status(xhci->shared_hcd); 727 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 728 usb_hcd_poll_rh_status(hcd); 729 return 0; 730 731 disable_clks: 732 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks); 733 enable_wakeup: 734 usb_wakeup_set(mtk, true); 735 return ret; 736 } 737 738 static int __maybe_unused xhci_mtk_runtime_suspend(struct device *dev) 739 { 740 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); 741 struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd); 742 int ret = 0; 743 744 if (xhci->xhc_state) 745 return -ESHUTDOWN; 746 747 if (device_may_wakeup(dev)) 748 ret = xhci_mtk_suspend(dev); 749 750 /* -EBUSY: let PM automatically reschedule another autosuspend */ 751 return ret ? -EBUSY : 0; 752 } 753 754 static int __maybe_unused xhci_mtk_runtime_resume(struct device *dev) 755 { 756 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); 757 struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd); 758 int ret = 0; 759 760 if (xhci->xhc_state) 761 return -ESHUTDOWN; 762 763 if (device_may_wakeup(dev)) 764 ret = xhci_mtk_resume(dev); 765 766 return ret; 767 } 768 769 static const struct dev_pm_ops xhci_mtk_pm_ops = { 770 SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume) 771 SET_RUNTIME_PM_OPS(xhci_mtk_runtime_suspend, 772 xhci_mtk_runtime_resume, NULL) 773 }; 774 775 #define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL) 776 777 static const struct of_device_id mtk_xhci_of_match[] = { 778 { .compatible = "mediatek,mt8173-xhci"}, 779 { .compatible = "mediatek,mt8195-xhci"}, 780 { .compatible = "mediatek,mtk-xhci"}, 781 { }, 782 }; 783 MODULE_DEVICE_TABLE(of, mtk_xhci_of_match); 784 785 static struct platform_driver mtk_xhci_driver = { 786 .probe = xhci_mtk_probe, 787 .remove = xhci_mtk_remove, 788 .driver = { 789 .name = "xhci-mtk", 790 .pm = DEV_PM_OPS, 791 .of_match_table = mtk_xhci_of_match, 792 }, 793 }; 794 795 static int __init xhci_mtk_init(void) 796 { 797 xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides); 798 return platform_driver_register(&mtk_xhci_driver); 799 } 800 module_init(xhci_mtk_init); 801 802 static void __exit xhci_mtk_exit(void) 803 { 804 platform_driver_unregister(&mtk_xhci_driver); 805 } 806 module_exit(xhci_mtk_exit); 807 808 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>"); 809 MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver"); 810 MODULE_LICENSE("GPL v2"); 811