1 /* 2 * xHCI host controller driver 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/usb.h> 24 #include <linux/pci.h> 25 #include <linux/slab.h> 26 #include <linux/dmapool.h> 27 #include <linux/dma-mapping.h> 28 29 #include "xhci.h" 30 #include "xhci-trace.h" 31 32 /* 33 * Allocates a generic ring segment from the ring pool, sets the dma address, 34 * initializes the segment to zero, and sets the private next pointer to NULL. 35 * 36 * Section 4.11.1.1: 37 * "All components of all Command and Transfer TRBs shall be initialized to '0'" 38 */ 39 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, 40 unsigned int cycle_state, gfp_t flags) 41 { 42 struct xhci_segment *seg; 43 dma_addr_t dma; 44 int i; 45 46 seg = kzalloc(sizeof *seg, flags); 47 if (!seg) 48 return NULL; 49 50 seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma); 51 if (!seg->trbs) { 52 kfree(seg); 53 return NULL; 54 } 55 56 memset(seg->trbs, 0, TRB_SEGMENT_SIZE); 57 /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */ 58 if (cycle_state == 0) { 59 for (i = 0; i < TRBS_PER_SEGMENT; i++) 60 seg->trbs[i].link.control |= cpu_to_le32(TRB_CYCLE); 61 } 62 seg->dma = dma; 63 seg->next = NULL; 64 65 return seg; 66 } 67 68 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg) 69 { 70 if (seg->trbs) { 71 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma); 72 seg->trbs = NULL; 73 } 74 kfree(seg); 75 } 76 77 static void xhci_free_segments_for_ring(struct xhci_hcd *xhci, 78 struct xhci_segment *first) 79 { 80 struct xhci_segment *seg; 81 82 seg = first->next; 83 while (seg != first) { 84 struct xhci_segment *next = seg->next; 85 xhci_segment_free(xhci, seg); 86 seg = next; 87 } 88 xhci_segment_free(xhci, first); 89 } 90 91 /* 92 * Make the prev segment point to the next segment. 93 * 94 * Change the last TRB in the prev segment to be a Link TRB which points to the 95 * DMA address of the next segment. The caller needs to set any Link TRB 96 * related flags, such as End TRB, Toggle Cycle, and no snoop. 97 */ 98 static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev, 99 struct xhci_segment *next, enum xhci_ring_type type) 100 { 101 u32 val; 102 103 if (!prev || !next) 104 return; 105 prev->next = next; 106 if (type != TYPE_EVENT) { 107 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr = 108 cpu_to_le64(next->dma); 109 110 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */ 111 val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control); 112 val &= ~TRB_TYPE_BITMASK; 113 val |= TRB_TYPE(TRB_LINK); 114 /* Always set the chain bit with 0.95 hardware */ 115 /* Set chain bit for isoc rings on AMD 0.96 host */ 116 if (xhci_link_trb_quirk(xhci) || 117 (type == TYPE_ISOC && 118 (xhci->quirks & XHCI_AMD_0x96_HOST))) 119 val |= TRB_CHAIN; 120 prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val); 121 } 122 } 123 124 /* 125 * Link the ring to the new segments. 126 * Set Toggle Cycle for the new ring if needed. 127 */ 128 static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *ring, 129 struct xhci_segment *first, struct xhci_segment *last, 130 unsigned int num_segs) 131 { 132 struct xhci_segment *next; 133 134 if (!ring || !first || !last) 135 return; 136 137 next = ring->enq_seg->next; 138 xhci_link_segments(xhci, ring->enq_seg, first, ring->type); 139 xhci_link_segments(xhci, last, next, ring->type); 140 ring->num_segs += num_segs; 141 ring->num_trbs_free += (TRBS_PER_SEGMENT - 1) * num_segs; 142 143 if (ring->type != TYPE_EVENT && ring->enq_seg == ring->last_seg) { 144 ring->last_seg->trbs[TRBS_PER_SEGMENT-1].link.control 145 &= ~cpu_to_le32(LINK_TOGGLE); 146 last->trbs[TRBS_PER_SEGMENT-1].link.control 147 |= cpu_to_le32(LINK_TOGGLE); 148 ring->last_seg = last; 149 } 150 } 151 152 /* 153 * We need a radix tree for mapping physical addresses of TRBs to which stream 154 * ID they belong to. We need to do this because the host controller won't tell 155 * us which stream ring the TRB came from. We could store the stream ID in an 156 * event data TRB, but that doesn't help us for the cancellation case, since the 157 * endpoint may stop before it reaches that event data TRB. 158 * 159 * The radix tree maps the upper portion of the TRB DMA address to a ring 160 * segment that has the same upper portion of DMA addresses. For example, say I 161 * have segments of size 1KB, that are always 1KB aligned. A segment may 162 * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the 163 * key to the stream ID is 0x43244. I can use the DMA address of the TRB to 164 * pass the radix tree a key to get the right stream ID: 165 * 166 * 0x10c90fff >> 10 = 0x43243 167 * 0x10c912c0 >> 10 = 0x43244 168 * 0x10c91400 >> 10 = 0x43245 169 * 170 * Obviously, only those TRBs with DMA addresses that are within the segment 171 * will make the radix tree return the stream ID for that ring. 172 * 173 * Caveats for the radix tree: 174 * 175 * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an 176 * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be 177 * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the 178 * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit 179 * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit 180 * extended systems (where the DMA address can be bigger than 32-bits), 181 * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that. 182 */ 183 static int xhci_insert_segment_mapping(struct radix_tree_root *trb_address_map, 184 struct xhci_ring *ring, 185 struct xhci_segment *seg, 186 gfp_t mem_flags) 187 { 188 unsigned long key; 189 int ret; 190 191 key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT); 192 /* Skip any segments that were already added. */ 193 if (radix_tree_lookup(trb_address_map, key)) 194 return 0; 195 196 ret = radix_tree_maybe_preload(mem_flags); 197 if (ret) 198 return ret; 199 ret = radix_tree_insert(trb_address_map, 200 key, ring); 201 radix_tree_preload_end(); 202 return ret; 203 } 204 205 static void xhci_remove_segment_mapping(struct radix_tree_root *trb_address_map, 206 struct xhci_segment *seg) 207 { 208 unsigned long key; 209 210 key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT); 211 if (radix_tree_lookup(trb_address_map, key)) 212 radix_tree_delete(trb_address_map, key); 213 } 214 215 static int xhci_update_stream_segment_mapping( 216 struct radix_tree_root *trb_address_map, 217 struct xhci_ring *ring, 218 struct xhci_segment *first_seg, 219 struct xhci_segment *last_seg, 220 gfp_t mem_flags) 221 { 222 struct xhci_segment *seg; 223 struct xhci_segment *failed_seg; 224 int ret; 225 226 if (WARN_ON_ONCE(trb_address_map == NULL)) 227 return 0; 228 229 seg = first_seg; 230 do { 231 ret = xhci_insert_segment_mapping(trb_address_map, 232 ring, seg, mem_flags); 233 if (ret) 234 goto remove_streams; 235 if (seg == last_seg) 236 return 0; 237 seg = seg->next; 238 } while (seg != first_seg); 239 240 return 0; 241 242 remove_streams: 243 failed_seg = seg; 244 seg = first_seg; 245 do { 246 xhci_remove_segment_mapping(trb_address_map, seg); 247 if (seg == failed_seg) 248 return ret; 249 seg = seg->next; 250 } while (seg != first_seg); 251 252 return ret; 253 } 254 255 static void xhci_remove_stream_mapping(struct xhci_ring *ring) 256 { 257 struct xhci_segment *seg; 258 259 if (WARN_ON_ONCE(ring->trb_address_map == NULL)) 260 return; 261 262 seg = ring->first_seg; 263 do { 264 xhci_remove_segment_mapping(ring->trb_address_map, seg); 265 seg = seg->next; 266 } while (seg != ring->first_seg); 267 } 268 269 static int xhci_update_stream_mapping(struct xhci_ring *ring, gfp_t mem_flags) 270 { 271 return xhci_update_stream_segment_mapping(ring->trb_address_map, ring, 272 ring->first_seg, ring->last_seg, mem_flags); 273 } 274 275 /* XXX: Do we need the hcd structure in all these functions? */ 276 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring) 277 { 278 if (!ring) 279 return; 280 281 if (ring->first_seg) { 282 if (ring->type == TYPE_STREAM) 283 xhci_remove_stream_mapping(ring); 284 xhci_free_segments_for_ring(xhci, ring->first_seg); 285 } 286 287 kfree(ring); 288 } 289 290 static void xhci_initialize_ring_info(struct xhci_ring *ring, 291 unsigned int cycle_state) 292 { 293 /* The ring is empty, so the enqueue pointer == dequeue pointer */ 294 ring->enqueue = ring->first_seg->trbs; 295 ring->enq_seg = ring->first_seg; 296 ring->dequeue = ring->enqueue; 297 ring->deq_seg = ring->first_seg; 298 /* The ring is initialized to 0. The producer must write 1 to the cycle 299 * bit to handover ownership of the TRB, so PCS = 1. The consumer must 300 * compare CCS to the cycle bit to check ownership, so CCS = 1. 301 * 302 * New rings are initialized with cycle state equal to 1; if we are 303 * handling ring expansion, set the cycle state equal to the old ring. 304 */ 305 ring->cycle_state = cycle_state; 306 /* Not necessary for new rings, but needed for re-initialized rings */ 307 ring->enq_updates = 0; 308 ring->deq_updates = 0; 309 310 /* 311 * Each segment has a link TRB, and leave an extra TRB for SW 312 * accounting purpose 313 */ 314 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1; 315 } 316 317 /* Allocate segments and link them for a ring */ 318 static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci, 319 struct xhci_segment **first, struct xhci_segment **last, 320 unsigned int num_segs, unsigned int cycle_state, 321 enum xhci_ring_type type, gfp_t flags) 322 { 323 struct xhci_segment *prev; 324 325 prev = xhci_segment_alloc(xhci, cycle_state, flags); 326 if (!prev) 327 return -ENOMEM; 328 num_segs--; 329 330 *first = prev; 331 while (num_segs > 0) { 332 struct xhci_segment *next; 333 334 next = xhci_segment_alloc(xhci, cycle_state, flags); 335 if (!next) { 336 prev = *first; 337 while (prev) { 338 next = prev->next; 339 xhci_segment_free(xhci, prev); 340 prev = next; 341 } 342 return -ENOMEM; 343 } 344 xhci_link_segments(xhci, prev, next, type); 345 346 prev = next; 347 num_segs--; 348 } 349 xhci_link_segments(xhci, prev, *first, type); 350 *last = prev; 351 352 return 0; 353 } 354 355 /** 356 * Create a new ring with zero or more segments. 357 * 358 * Link each segment together into a ring. 359 * Set the end flag and the cycle toggle bit on the last segment. 360 * See section 4.9.1 and figures 15 and 16. 361 */ 362 static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, 363 unsigned int num_segs, unsigned int cycle_state, 364 enum xhci_ring_type type, gfp_t flags) 365 { 366 struct xhci_ring *ring; 367 int ret; 368 369 ring = kzalloc(sizeof *(ring), flags); 370 if (!ring) 371 return NULL; 372 373 ring->num_segs = num_segs; 374 INIT_LIST_HEAD(&ring->td_list); 375 ring->type = type; 376 if (num_segs == 0) 377 return ring; 378 379 ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg, 380 &ring->last_seg, num_segs, cycle_state, type, flags); 381 if (ret) 382 goto fail; 383 384 /* Only event ring does not use link TRB */ 385 if (type != TYPE_EVENT) { 386 /* See section 4.9.2.1 and 6.4.4.1 */ 387 ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |= 388 cpu_to_le32(LINK_TOGGLE); 389 } 390 xhci_initialize_ring_info(ring, cycle_state); 391 return ring; 392 393 fail: 394 kfree(ring); 395 return NULL; 396 } 397 398 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci, 399 struct xhci_virt_device *virt_dev, 400 unsigned int ep_index) 401 { 402 int rings_cached; 403 404 rings_cached = virt_dev->num_rings_cached; 405 if (rings_cached < XHCI_MAX_RINGS_CACHED) { 406 virt_dev->ring_cache[rings_cached] = 407 virt_dev->eps[ep_index].ring; 408 virt_dev->num_rings_cached++; 409 xhci_dbg(xhci, "Cached old ring, " 410 "%d ring%s cached\n", 411 virt_dev->num_rings_cached, 412 (virt_dev->num_rings_cached > 1) ? "s" : ""); 413 } else { 414 xhci_ring_free(xhci, virt_dev->eps[ep_index].ring); 415 xhci_dbg(xhci, "Ring cache full (%d rings), " 416 "freeing ring\n", 417 virt_dev->num_rings_cached); 418 } 419 virt_dev->eps[ep_index].ring = NULL; 420 } 421 422 /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue 423 * pointers to the beginning of the ring. 424 */ 425 static void xhci_reinit_cached_ring(struct xhci_hcd *xhci, 426 struct xhci_ring *ring, unsigned int cycle_state, 427 enum xhci_ring_type type) 428 { 429 struct xhci_segment *seg = ring->first_seg; 430 int i; 431 432 do { 433 memset(seg->trbs, 0, 434 sizeof(union xhci_trb)*TRBS_PER_SEGMENT); 435 if (cycle_state == 0) { 436 for (i = 0; i < TRBS_PER_SEGMENT; i++) 437 seg->trbs[i].link.control |= 438 cpu_to_le32(TRB_CYCLE); 439 } 440 /* All endpoint rings have link TRBs */ 441 xhci_link_segments(xhci, seg, seg->next, type); 442 seg = seg->next; 443 } while (seg != ring->first_seg); 444 ring->type = type; 445 xhci_initialize_ring_info(ring, cycle_state); 446 /* td list should be empty since all URBs have been cancelled, 447 * but just in case... 448 */ 449 INIT_LIST_HEAD(&ring->td_list); 450 } 451 452 /* 453 * Expand an existing ring. 454 * Look for a cached ring or allocate a new ring which has same segment numbers 455 * and link the two rings. 456 */ 457 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, 458 unsigned int num_trbs, gfp_t flags) 459 { 460 struct xhci_segment *first; 461 struct xhci_segment *last; 462 unsigned int num_segs; 463 unsigned int num_segs_needed; 464 int ret; 465 466 num_segs_needed = (num_trbs + (TRBS_PER_SEGMENT - 1) - 1) / 467 (TRBS_PER_SEGMENT - 1); 468 469 /* Allocate number of segments we needed, or double the ring size */ 470 num_segs = ring->num_segs > num_segs_needed ? 471 ring->num_segs : num_segs_needed; 472 473 ret = xhci_alloc_segments_for_ring(xhci, &first, &last, 474 num_segs, ring->cycle_state, ring->type, flags); 475 if (ret) 476 return -ENOMEM; 477 478 if (ring->type == TYPE_STREAM) 479 ret = xhci_update_stream_segment_mapping(ring->trb_address_map, 480 ring, first, last, flags); 481 if (ret) { 482 struct xhci_segment *next; 483 do { 484 next = first->next; 485 xhci_segment_free(xhci, first); 486 if (first == last) 487 break; 488 first = next; 489 } while (true); 490 return ret; 491 } 492 493 xhci_link_rings(xhci, ring, first, last, num_segs); 494 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion, 495 "ring expansion succeed, now has %d segments", 496 ring->num_segs); 497 498 return 0; 499 } 500 501 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32) 502 503 static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci, 504 int type, gfp_t flags) 505 { 506 struct xhci_container_ctx *ctx; 507 508 if ((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT)) 509 return NULL; 510 511 ctx = kzalloc(sizeof(*ctx), flags); 512 if (!ctx) 513 return NULL; 514 515 ctx->type = type; 516 ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024; 517 if (type == XHCI_CTX_TYPE_INPUT) 518 ctx->size += CTX_SIZE(xhci->hcc_params); 519 520 ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma); 521 if (!ctx->bytes) { 522 kfree(ctx); 523 return NULL; 524 } 525 memset(ctx->bytes, 0, ctx->size); 526 return ctx; 527 } 528 529 static void xhci_free_container_ctx(struct xhci_hcd *xhci, 530 struct xhci_container_ctx *ctx) 531 { 532 if (!ctx) 533 return; 534 dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma); 535 kfree(ctx); 536 } 537 538 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, 539 struct xhci_container_ctx *ctx) 540 { 541 if (ctx->type != XHCI_CTX_TYPE_INPUT) 542 return NULL; 543 544 return (struct xhci_input_control_ctx *)ctx->bytes; 545 } 546 547 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, 548 struct xhci_container_ctx *ctx) 549 { 550 if (ctx->type == XHCI_CTX_TYPE_DEVICE) 551 return (struct xhci_slot_ctx *)ctx->bytes; 552 553 return (struct xhci_slot_ctx *) 554 (ctx->bytes + CTX_SIZE(xhci->hcc_params)); 555 } 556 557 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, 558 struct xhci_container_ctx *ctx, 559 unsigned int ep_index) 560 { 561 /* increment ep index by offset of start of ep ctx array */ 562 ep_index++; 563 if (ctx->type == XHCI_CTX_TYPE_INPUT) 564 ep_index++; 565 566 return (struct xhci_ep_ctx *) 567 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params))); 568 } 569 570 571 /***************** Streams structures manipulation *************************/ 572 573 static void xhci_free_stream_ctx(struct xhci_hcd *xhci, 574 unsigned int num_stream_ctxs, 575 struct xhci_stream_ctx *stream_ctx, dma_addr_t dma) 576 { 577 struct device *dev = xhci_to_hcd(xhci)->self.controller; 578 size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs; 579 580 if (size > MEDIUM_STREAM_ARRAY_SIZE) 581 dma_free_coherent(dev, size, 582 stream_ctx, dma); 583 else if (size <= SMALL_STREAM_ARRAY_SIZE) 584 return dma_pool_free(xhci->small_streams_pool, 585 stream_ctx, dma); 586 else 587 return dma_pool_free(xhci->medium_streams_pool, 588 stream_ctx, dma); 589 } 590 591 /* 592 * The stream context array for each endpoint with bulk streams enabled can 593 * vary in size, based on: 594 * - how many streams the endpoint supports, 595 * - the maximum primary stream array size the host controller supports, 596 * - and how many streams the device driver asks for. 597 * 598 * The stream context array must be a power of 2, and can be as small as 599 * 64 bytes or as large as 1MB. 600 */ 601 static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci, 602 unsigned int num_stream_ctxs, dma_addr_t *dma, 603 gfp_t mem_flags) 604 { 605 struct device *dev = xhci_to_hcd(xhci)->self.controller; 606 size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs; 607 608 if (size > MEDIUM_STREAM_ARRAY_SIZE) 609 return dma_alloc_coherent(dev, size, 610 dma, mem_flags); 611 else if (size <= SMALL_STREAM_ARRAY_SIZE) 612 return dma_pool_alloc(xhci->small_streams_pool, 613 mem_flags, dma); 614 else 615 return dma_pool_alloc(xhci->medium_streams_pool, 616 mem_flags, dma); 617 } 618 619 struct xhci_ring *xhci_dma_to_transfer_ring( 620 struct xhci_virt_ep *ep, 621 u64 address) 622 { 623 if (ep->ep_state & EP_HAS_STREAMS) 624 return radix_tree_lookup(&ep->stream_info->trb_address_map, 625 address >> TRB_SEGMENT_SHIFT); 626 return ep->ring; 627 } 628 629 struct xhci_ring *xhci_stream_id_to_ring( 630 struct xhci_virt_device *dev, 631 unsigned int ep_index, 632 unsigned int stream_id) 633 { 634 struct xhci_virt_ep *ep = &dev->eps[ep_index]; 635 636 if (stream_id == 0) 637 return ep->ring; 638 if (!ep->stream_info) 639 return NULL; 640 641 if (stream_id > ep->stream_info->num_streams) 642 return NULL; 643 return ep->stream_info->stream_rings[stream_id]; 644 } 645 646 /* 647 * Change an endpoint's internal structure so it supports stream IDs. The 648 * number of requested streams includes stream 0, which cannot be used by device 649 * drivers. 650 * 651 * The number of stream contexts in the stream context array may be bigger than 652 * the number of streams the driver wants to use. This is because the number of 653 * stream context array entries must be a power of two. 654 */ 655 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 656 unsigned int num_stream_ctxs, 657 unsigned int num_streams, gfp_t mem_flags) 658 { 659 struct xhci_stream_info *stream_info; 660 u32 cur_stream; 661 struct xhci_ring *cur_ring; 662 u64 addr; 663 int ret; 664 665 xhci_dbg(xhci, "Allocating %u streams and %u " 666 "stream context array entries.\n", 667 num_streams, num_stream_ctxs); 668 if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) { 669 xhci_dbg(xhci, "Command ring has no reserved TRBs available\n"); 670 return NULL; 671 } 672 xhci->cmd_ring_reserved_trbs++; 673 674 stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags); 675 if (!stream_info) 676 goto cleanup_trbs; 677 678 stream_info->num_streams = num_streams; 679 stream_info->num_stream_ctxs = num_stream_ctxs; 680 681 /* Initialize the array of virtual pointers to stream rings. */ 682 stream_info->stream_rings = kzalloc( 683 sizeof(struct xhci_ring *)*num_streams, 684 mem_flags); 685 if (!stream_info->stream_rings) 686 goto cleanup_info; 687 688 /* Initialize the array of DMA addresses for stream rings for the HW. */ 689 stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci, 690 num_stream_ctxs, &stream_info->ctx_array_dma, 691 mem_flags); 692 if (!stream_info->stream_ctx_array) 693 goto cleanup_ctx; 694 memset(stream_info->stream_ctx_array, 0, 695 sizeof(struct xhci_stream_ctx)*num_stream_ctxs); 696 697 /* Allocate everything needed to free the stream rings later */ 698 stream_info->free_streams_command = 699 xhci_alloc_command(xhci, true, true, mem_flags); 700 if (!stream_info->free_streams_command) 701 goto cleanup_ctx; 702 703 INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC); 704 705 /* Allocate rings for all the streams that the driver will use, 706 * and add their segment DMA addresses to the radix tree. 707 * Stream 0 is reserved. 708 */ 709 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) { 710 stream_info->stream_rings[cur_stream] = 711 xhci_ring_alloc(xhci, 2, 1, TYPE_STREAM, mem_flags); 712 cur_ring = stream_info->stream_rings[cur_stream]; 713 if (!cur_ring) 714 goto cleanup_rings; 715 cur_ring->stream_id = cur_stream; 716 cur_ring->trb_address_map = &stream_info->trb_address_map; 717 /* Set deq ptr, cycle bit, and stream context type */ 718 addr = cur_ring->first_seg->dma | 719 SCT_FOR_CTX(SCT_PRI_TR) | 720 cur_ring->cycle_state; 721 stream_info->stream_ctx_array[cur_stream].stream_ring = 722 cpu_to_le64(addr); 723 xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n", 724 cur_stream, (unsigned long long) addr); 725 726 ret = xhci_update_stream_mapping(cur_ring, mem_flags); 727 if (ret) { 728 xhci_ring_free(xhci, cur_ring); 729 stream_info->stream_rings[cur_stream] = NULL; 730 goto cleanup_rings; 731 } 732 } 733 /* Leave the other unused stream ring pointers in the stream context 734 * array initialized to zero. This will cause the xHC to give us an 735 * error if the device asks for a stream ID we don't have setup (if it 736 * was any other way, the host controller would assume the ring is 737 * "empty" and wait forever for data to be queued to that stream ID). 738 */ 739 740 return stream_info; 741 742 cleanup_rings: 743 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) { 744 cur_ring = stream_info->stream_rings[cur_stream]; 745 if (cur_ring) { 746 xhci_ring_free(xhci, cur_ring); 747 stream_info->stream_rings[cur_stream] = NULL; 748 } 749 } 750 xhci_free_command(xhci, stream_info->free_streams_command); 751 cleanup_ctx: 752 kfree(stream_info->stream_rings); 753 cleanup_info: 754 kfree(stream_info); 755 cleanup_trbs: 756 xhci->cmd_ring_reserved_trbs--; 757 return NULL; 758 } 759 /* 760 * Sets the MaxPStreams field and the Linear Stream Array field. 761 * Sets the dequeue pointer to the stream context array. 762 */ 763 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 764 struct xhci_ep_ctx *ep_ctx, 765 struct xhci_stream_info *stream_info) 766 { 767 u32 max_primary_streams; 768 /* MaxPStreams is the number of stream context array entries, not the 769 * number we're actually using. Must be in 2^(MaxPstreams + 1) format. 770 * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc. 771 */ 772 max_primary_streams = fls(stream_info->num_stream_ctxs) - 2; 773 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, 774 "Setting number of stream ctx array entries to %u", 775 1 << (max_primary_streams + 1)); 776 ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK); 777 ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams) 778 | EP_HAS_LSA); 779 ep_ctx->deq = cpu_to_le64(stream_info->ctx_array_dma); 780 } 781 782 /* 783 * Sets the MaxPStreams field and the Linear Stream Array field to 0. 784 * Reinstalls the "normal" endpoint ring (at its previous dequeue mark, 785 * not at the beginning of the ring). 786 */ 787 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci, 788 struct xhci_ep_ctx *ep_ctx, 789 struct xhci_virt_ep *ep) 790 { 791 dma_addr_t addr; 792 ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA)); 793 addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue); 794 ep_ctx->deq = cpu_to_le64(addr | ep->ring->cycle_state); 795 } 796 797 /* Frees all stream contexts associated with the endpoint, 798 * 799 * Caller should fix the endpoint context streams fields. 800 */ 801 void xhci_free_stream_info(struct xhci_hcd *xhci, 802 struct xhci_stream_info *stream_info) 803 { 804 int cur_stream; 805 struct xhci_ring *cur_ring; 806 807 if (!stream_info) 808 return; 809 810 for (cur_stream = 1; cur_stream < stream_info->num_streams; 811 cur_stream++) { 812 cur_ring = stream_info->stream_rings[cur_stream]; 813 if (cur_ring) { 814 xhci_ring_free(xhci, cur_ring); 815 stream_info->stream_rings[cur_stream] = NULL; 816 } 817 } 818 xhci_free_command(xhci, stream_info->free_streams_command); 819 xhci->cmd_ring_reserved_trbs--; 820 if (stream_info->stream_ctx_array) 821 xhci_free_stream_ctx(xhci, 822 stream_info->num_stream_ctxs, 823 stream_info->stream_ctx_array, 824 stream_info->ctx_array_dma); 825 826 kfree(stream_info->stream_rings); 827 kfree(stream_info); 828 } 829 830 831 /***************** Device context manipulation *************************/ 832 833 static void xhci_init_endpoint_timer(struct xhci_hcd *xhci, 834 struct xhci_virt_ep *ep) 835 { 836 init_timer(&ep->stop_cmd_timer); 837 ep->stop_cmd_timer.data = (unsigned long) ep; 838 ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog; 839 ep->xhci = xhci; 840 } 841 842 static void xhci_free_tt_info(struct xhci_hcd *xhci, 843 struct xhci_virt_device *virt_dev, 844 int slot_id) 845 { 846 struct list_head *tt_list_head; 847 struct xhci_tt_bw_info *tt_info, *next; 848 bool slot_found = false; 849 850 /* If the device never made it past the Set Address stage, 851 * it may not have the real_port set correctly. 852 */ 853 if (virt_dev->real_port == 0 || 854 virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) { 855 xhci_dbg(xhci, "Bad real port.\n"); 856 return; 857 } 858 859 tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts); 860 list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) { 861 /* Multi-TT hubs will have more than one entry */ 862 if (tt_info->slot_id == slot_id) { 863 slot_found = true; 864 list_del(&tt_info->tt_list); 865 kfree(tt_info); 866 } else if (slot_found) { 867 break; 868 } 869 } 870 } 871 872 int xhci_alloc_tt_info(struct xhci_hcd *xhci, 873 struct xhci_virt_device *virt_dev, 874 struct usb_device *hdev, 875 struct usb_tt *tt, gfp_t mem_flags) 876 { 877 struct xhci_tt_bw_info *tt_info; 878 unsigned int num_ports; 879 int i, j; 880 881 if (!tt->multi) 882 num_ports = 1; 883 else 884 num_ports = hdev->maxchild; 885 886 for (i = 0; i < num_ports; i++, tt_info++) { 887 struct xhci_interval_bw_table *bw_table; 888 889 tt_info = kzalloc(sizeof(*tt_info), mem_flags); 890 if (!tt_info) 891 goto free_tts; 892 INIT_LIST_HEAD(&tt_info->tt_list); 893 list_add(&tt_info->tt_list, 894 &xhci->rh_bw[virt_dev->real_port - 1].tts); 895 tt_info->slot_id = virt_dev->udev->slot_id; 896 if (tt->multi) 897 tt_info->ttport = i+1; 898 bw_table = &tt_info->bw_table; 899 for (j = 0; j < XHCI_MAX_INTERVAL; j++) 900 INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints); 901 } 902 return 0; 903 904 free_tts: 905 xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id); 906 return -ENOMEM; 907 } 908 909 910 /* All the xhci_tds in the ring's TD list should be freed at this point. 911 * Should be called with xhci->lock held if there is any chance the TT lists 912 * will be manipulated by the configure endpoint, allocate device, or update 913 * hub functions while this function is removing the TT entries from the list. 914 */ 915 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id) 916 { 917 struct xhci_virt_device *dev; 918 int i; 919 int old_active_eps = 0; 920 921 /* Slot ID 0 is reserved */ 922 if (slot_id == 0 || !xhci->devs[slot_id]) 923 return; 924 925 dev = xhci->devs[slot_id]; 926 xhci->dcbaa->dev_context_ptrs[slot_id] = 0; 927 if (!dev) 928 return; 929 930 if (dev->tt_info) 931 old_active_eps = dev->tt_info->active_eps; 932 933 for (i = 0; i < 31; ++i) { 934 if (dev->eps[i].ring) 935 xhci_ring_free(xhci, dev->eps[i].ring); 936 if (dev->eps[i].stream_info) 937 xhci_free_stream_info(xhci, 938 dev->eps[i].stream_info); 939 /* Endpoints on the TT/root port lists should have been removed 940 * when usb_disable_device() was called for the device. 941 * We can't drop them anyway, because the udev might have gone 942 * away by this point, and we can't tell what speed it was. 943 */ 944 if (!list_empty(&dev->eps[i].bw_endpoint_list)) 945 xhci_warn(xhci, "Slot %u endpoint %u " 946 "not removed from BW list!\n", 947 slot_id, i); 948 } 949 /* If this is a hub, free the TT(s) from the TT list */ 950 xhci_free_tt_info(xhci, dev, slot_id); 951 /* If necessary, update the number of active TTs on this root port */ 952 xhci_update_tt_active_eps(xhci, dev, old_active_eps); 953 954 if (dev->ring_cache) { 955 for (i = 0; i < dev->num_rings_cached; i++) 956 xhci_ring_free(xhci, dev->ring_cache[i]); 957 kfree(dev->ring_cache); 958 } 959 960 if (dev->in_ctx) 961 xhci_free_container_ctx(xhci, dev->in_ctx); 962 if (dev->out_ctx) 963 xhci_free_container_ctx(xhci, dev->out_ctx); 964 965 kfree(xhci->devs[slot_id]); 966 xhci->devs[slot_id] = NULL; 967 } 968 969 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, 970 struct usb_device *udev, gfp_t flags) 971 { 972 struct xhci_virt_device *dev; 973 int i; 974 975 /* Slot ID 0 is reserved */ 976 if (slot_id == 0 || xhci->devs[slot_id]) { 977 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id); 978 return 0; 979 } 980 981 xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags); 982 if (!xhci->devs[slot_id]) 983 return 0; 984 dev = xhci->devs[slot_id]; 985 986 /* Allocate the (output) device context that will be used in the HC. */ 987 dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags); 988 if (!dev->out_ctx) 989 goto fail; 990 991 xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id, 992 (unsigned long long)dev->out_ctx->dma); 993 994 /* Allocate the (input) device context for address device command */ 995 dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags); 996 if (!dev->in_ctx) 997 goto fail; 998 999 xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id, 1000 (unsigned long long)dev->in_ctx->dma); 1001 1002 /* Initialize the cancellation list and watchdog timers for each ep */ 1003 for (i = 0; i < 31; i++) { 1004 xhci_init_endpoint_timer(xhci, &dev->eps[i]); 1005 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list); 1006 INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list); 1007 } 1008 1009 /* Allocate endpoint 0 ring */ 1010 dev->eps[0].ring = xhci_ring_alloc(xhci, 2, 1, TYPE_CTRL, flags); 1011 if (!dev->eps[0].ring) 1012 goto fail; 1013 1014 /* Allocate pointers to the ring cache */ 1015 dev->ring_cache = kzalloc( 1016 sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED, 1017 flags); 1018 if (!dev->ring_cache) 1019 goto fail; 1020 dev->num_rings_cached = 0; 1021 1022 init_completion(&dev->cmd_completion); 1023 dev->udev = udev; 1024 1025 /* Point to output device context in dcbaa. */ 1026 xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma); 1027 xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n", 1028 slot_id, 1029 &xhci->dcbaa->dev_context_ptrs[slot_id], 1030 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id])); 1031 1032 return 1; 1033 fail: 1034 xhci_free_virt_device(xhci, slot_id); 1035 return 0; 1036 } 1037 1038 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 1039 struct usb_device *udev) 1040 { 1041 struct xhci_virt_device *virt_dev; 1042 struct xhci_ep_ctx *ep0_ctx; 1043 struct xhci_ring *ep_ring; 1044 1045 virt_dev = xhci->devs[udev->slot_id]; 1046 ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0); 1047 ep_ring = virt_dev->eps[0].ring; 1048 /* 1049 * FIXME we don't keep track of the dequeue pointer very well after a 1050 * Set TR dequeue pointer, so we're setting the dequeue pointer of the 1051 * host to our enqueue pointer. This should only be called after a 1052 * configured device has reset, so all control transfers should have 1053 * been completed or cancelled before the reset. 1054 */ 1055 ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg, 1056 ep_ring->enqueue) 1057 | ep_ring->cycle_state); 1058 } 1059 1060 /* 1061 * The xHCI roothub may have ports of differing speeds in any order in the port 1062 * status registers. xhci->port_array provides an array of the port speed for 1063 * each offset into the port status registers. 1064 * 1065 * The xHCI hardware wants to know the roothub port number that the USB device 1066 * is attached to (or the roothub port its ancestor hub is attached to). All we 1067 * know is the index of that port under either the USB 2.0 or the USB 3.0 1068 * roothub, but that doesn't give us the real index into the HW port status 1069 * registers. Call xhci_find_raw_port_number() to get real index. 1070 */ 1071 static u32 xhci_find_real_port_number(struct xhci_hcd *xhci, 1072 struct usb_device *udev) 1073 { 1074 struct usb_device *top_dev; 1075 struct usb_hcd *hcd; 1076 1077 if (udev->speed == USB_SPEED_SUPER) 1078 hcd = xhci->shared_hcd; 1079 else 1080 hcd = xhci->main_hcd; 1081 1082 for (top_dev = udev; top_dev->parent && top_dev->parent->parent; 1083 top_dev = top_dev->parent) 1084 /* Found device below root hub */; 1085 1086 return xhci_find_raw_port_number(hcd, top_dev->portnum); 1087 } 1088 1089 /* Setup an xHCI virtual device for a Set Address command */ 1090 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev) 1091 { 1092 struct xhci_virt_device *dev; 1093 struct xhci_ep_ctx *ep0_ctx; 1094 struct xhci_slot_ctx *slot_ctx; 1095 u32 port_num; 1096 u32 max_packets; 1097 struct usb_device *top_dev; 1098 1099 dev = xhci->devs[udev->slot_id]; 1100 /* Slot ID 0 is reserved */ 1101 if (udev->slot_id == 0 || !dev) { 1102 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n", 1103 udev->slot_id); 1104 return -EINVAL; 1105 } 1106 ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0); 1107 slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx); 1108 1109 /* 3) Only the control endpoint is valid - one endpoint context */ 1110 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route); 1111 switch (udev->speed) { 1112 case USB_SPEED_SUPER: 1113 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS); 1114 max_packets = MAX_PACKET(512); 1115 break; 1116 case USB_SPEED_HIGH: 1117 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS); 1118 max_packets = MAX_PACKET(64); 1119 break; 1120 /* USB core guesses at a 64-byte max packet first for FS devices */ 1121 case USB_SPEED_FULL: 1122 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS); 1123 max_packets = MAX_PACKET(64); 1124 break; 1125 case USB_SPEED_LOW: 1126 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS); 1127 max_packets = MAX_PACKET(8); 1128 break; 1129 case USB_SPEED_WIRELESS: 1130 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n"); 1131 return -EINVAL; 1132 break; 1133 default: 1134 /* Speed was set earlier, this shouldn't happen. */ 1135 return -EINVAL; 1136 } 1137 /* Find the root hub port this device is under */ 1138 port_num = xhci_find_real_port_number(xhci, udev); 1139 if (!port_num) 1140 return -EINVAL; 1141 slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num)); 1142 /* Set the port number in the virtual_device to the faked port number */ 1143 for (top_dev = udev; top_dev->parent && top_dev->parent->parent; 1144 top_dev = top_dev->parent) 1145 /* Found device below root hub */; 1146 dev->fake_port = top_dev->portnum; 1147 dev->real_port = port_num; 1148 xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num); 1149 xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port); 1150 1151 /* Find the right bandwidth table that this device will be a part of. 1152 * If this is a full speed device attached directly to a root port (or a 1153 * decendent of one), it counts as a primary bandwidth domain, not a 1154 * secondary bandwidth domain under a TT. An xhci_tt_info structure 1155 * will never be created for the HS root hub. 1156 */ 1157 if (!udev->tt || !udev->tt->hub->parent) { 1158 dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table; 1159 } else { 1160 struct xhci_root_port_bw_info *rh_bw; 1161 struct xhci_tt_bw_info *tt_bw; 1162 1163 rh_bw = &xhci->rh_bw[port_num - 1]; 1164 /* Find the right TT. */ 1165 list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) { 1166 if (tt_bw->slot_id != udev->tt->hub->slot_id) 1167 continue; 1168 1169 if (!dev->udev->tt->multi || 1170 (udev->tt->multi && 1171 tt_bw->ttport == dev->udev->ttport)) { 1172 dev->bw_table = &tt_bw->bw_table; 1173 dev->tt_info = tt_bw; 1174 break; 1175 } 1176 } 1177 if (!dev->tt_info) 1178 xhci_warn(xhci, "WARN: Didn't find a matching TT\n"); 1179 } 1180 1181 /* Is this a LS/FS device under an external HS hub? */ 1182 if (udev->tt && udev->tt->hub->parent) { 1183 slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id | 1184 (udev->ttport << 8)); 1185 if (udev->tt->multi) 1186 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT); 1187 } 1188 xhci_dbg(xhci, "udev->tt = %p\n", udev->tt); 1189 xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport); 1190 1191 /* Step 4 - ring already allocated */ 1192 /* Step 5 */ 1193 ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP)); 1194 1195 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */ 1196 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3) | 1197 max_packets); 1198 1199 ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma | 1200 dev->eps[0].ring->cycle_state); 1201 1202 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */ 1203 1204 return 0; 1205 } 1206 1207 /* 1208 * Convert interval expressed as 2^(bInterval - 1) == interval into 1209 * straight exponent value 2^n == interval. 1210 * 1211 */ 1212 static unsigned int xhci_parse_exponent_interval(struct usb_device *udev, 1213 struct usb_host_endpoint *ep) 1214 { 1215 unsigned int interval; 1216 1217 interval = clamp_val(ep->desc.bInterval, 1, 16) - 1; 1218 if (interval != ep->desc.bInterval - 1) 1219 dev_warn(&udev->dev, 1220 "ep %#x - rounding interval to %d %sframes\n", 1221 ep->desc.bEndpointAddress, 1222 1 << interval, 1223 udev->speed == USB_SPEED_FULL ? "" : "micro"); 1224 1225 if (udev->speed == USB_SPEED_FULL) { 1226 /* 1227 * Full speed isoc endpoints specify interval in frames, 1228 * not microframes. We are using microframes everywhere, 1229 * so adjust accordingly. 1230 */ 1231 interval += 3; /* 1 frame = 2^3 uframes */ 1232 } 1233 1234 return interval; 1235 } 1236 1237 /* 1238 * Convert bInterval expressed in microframes (in 1-255 range) to exponent of 1239 * microframes, rounded down to nearest power of 2. 1240 */ 1241 static unsigned int xhci_microframes_to_exponent(struct usb_device *udev, 1242 struct usb_host_endpoint *ep, unsigned int desc_interval, 1243 unsigned int min_exponent, unsigned int max_exponent) 1244 { 1245 unsigned int interval; 1246 1247 interval = fls(desc_interval) - 1; 1248 interval = clamp_val(interval, min_exponent, max_exponent); 1249 if ((1 << interval) != desc_interval) 1250 dev_warn(&udev->dev, 1251 "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n", 1252 ep->desc.bEndpointAddress, 1253 1 << interval, 1254 desc_interval); 1255 1256 return interval; 1257 } 1258 1259 static unsigned int xhci_parse_microframe_interval(struct usb_device *udev, 1260 struct usb_host_endpoint *ep) 1261 { 1262 if (ep->desc.bInterval == 0) 1263 return 0; 1264 return xhci_microframes_to_exponent(udev, ep, 1265 ep->desc.bInterval, 0, 15); 1266 } 1267 1268 1269 static unsigned int xhci_parse_frame_interval(struct usb_device *udev, 1270 struct usb_host_endpoint *ep) 1271 { 1272 return xhci_microframes_to_exponent(udev, ep, 1273 ep->desc.bInterval * 8, 3, 10); 1274 } 1275 1276 /* Return the polling or NAK interval. 1277 * 1278 * The polling interval is expressed in "microframes". If xHCI's Interval field 1279 * is set to N, it will service the endpoint every 2^(Interval)*125us. 1280 * 1281 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval 1282 * is set to 0. 1283 */ 1284 static unsigned int xhci_get_endpoint_interval(struct usb_device *udev, 1285 struct usb_host_endpoint *ep) 1286 { 1287 unsigned int interval = 0; 1288 1289 switch (udev->speed) { 1290 case USB_SPEED_HIGH: 1291 /* Max NAK rate */ 1292 if (usb_endpoint_xfer_control(&ep->desc) || 1293 usb_endpoint_xfer_bulk(&ep->desc)) { 1294 interval = xhci_parse_microframe_interval(udev, ep); 1295 break; 1296 } 1297 /* Fall through - SS and HS isoc/int have same decoding */ 1298 1299 case USB_SPEED_SUPER: 1300 if (usb_endpoint_xfer_int(&ep->desc) || 1301 usb_endpoint_xfer_isoc(&ep->desc)) { 1302 interval = xhci_parse_exponent_interval(udev, ep); 1303 } 1304 break; 1305 1306 case USB_SPEED_FULL: 1307 if (usb_endpoint_xfer_isoc(&ep->desc)) { 1308 interval = xhci_parse_exponent_interval(udev, ep); 1309 break; 1310 } 1311 /* 1312 * Fall through for interrupt endpoint interval decoding 1313 * since it uses the same rules as low speed interrupt 1314 * endpoints. 1315 */ 1316 1317 case USB_SPEED_LOW: 1318 if (usb_endpoint_xfer_int(&ep->desc) || 1319 usb_endpoint_xfer_isoc(&ep->desc)) { 1320 1321 interval = xhci_parse_frame_interval(udev, ep); 1322 } 1323 break; 1324 1325 default: 1326 BUG(); 1327 } 1328 return EP_INTERVAL(interval); 1329 } 1330 1331 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps. 1332 * High speed endpoint descriptors can define "the number of additional 1333 * transaction opportunities per microframe", but that goes in the Max Burst 1334 * endpoint context field. 1335 */ 1336 static u32 xhci_get_endpoint_mult(struct usb_device *udev, 1337 struct usb_host_endpoint *ep) 1338 { 1339 if (udev->speed != USB_SPEED_SUPER || 1340 !usb_endpoint_xfer_isoc(&ep->desc)) 1341 return 0; 1342 return ep->ss_ep_comp.bmAttributes; 1343 } 1344 1345 static u32 xhci_get_endpoint_type(struct usb_device *udev, 1346 struct usb_host_endpoint *ep) 1347 { 1348 int in; 1349 u32 type; 1350 1351 in = usb_endpoint_dir_in(&ep->desc); 1352 if (usb_endpoint_xfer_control(&ep->desc)) { 1353 type = EP_TYPE(CTRL_EP); 1354 } else if (usb_endpoint_xfer_bulk(&ep->desc)) { 1355 if (in) 1356 type = EP_TYPE(BULK_IN_EP); 1357 else 1358 type = EP_TYPE(BULK_OUT_EP); 1359 } else if (usb_endpoint_xfer_isoc(&ep->desc)) { 1360 if (in) 1361 type = EP_TYPE(ISOC_IN_EP); 1362 else 1363 type = EP_TYPE(ISOC_OUT_EP); 1364 } else if (usb_endpoint_xfer_int(&ep->desc)) { 1365 if (in) 1366 type = EP_TYPE(INT_IN_EP); 1367 else 1368 type = EP_TYPE(INT_OUT_EP); 1369 } else { 1370 type = 0; 1371 } 1372 return type; 1373 } 1374 1375 /* Return the maximum endpoint service interval time (ESIT) payload. 1376 * Basically, this is the maxpacket size, multiplied by the burst size 1377 * and mult size. 1378 */ 1379 static u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci, 1380 struct usb_device *udev, 1381 struct usb_host_endpoint *ep) 1382 { 1383 int max_burst; 1384 int max_packet; 1385 1386 /* Only applies for interrupt or isochronous endpoints */ 1387 if (usb_endpoint_xfer_control(&ep->desc) || 1388 usb_endpoint_xfer_bulk(&ep->desc)) 1389 return 0; 1390 1391 if (udev->speed == USB_SPEED_SUPER) 1392 return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval); 1393 1394 max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc)); 1395 max_burst = (usb_endpoint_maxp(&ep->desc) & 0x1800) >> 11; 1396 /* A 0 in max burst means 1 transfer per ESIT */ 1397 return max_packet * (max_burst + 1); 1398 } 1399 1400 /* Set up an endpoint with one ring segment. Do not allocate stream rings. 1401 * Drivers will have to call usb_alloc_streams() to do that. 1402 */ 1403 int xhci_endpoint_init(struct xhci_hcd *xhci, 1404 struct xhci_virt_device *virt_dev, 1405 struct usb_device *udev, 1406 struct usb_host_endpoint *ep, 1407 gfp_t mem_flags) 1408 { 1409 unsigned int ep_index; 1410 struct xhci_ep_ctx *ep_ctx; 1411 struct xhci_ring *ep_ring; 1412 unsigned int max_packet; 1413 unsigned int max_burst; 1414 enum xhci_ring_type type; 1415 u32 max_esit_payload; 1416 u32 endpoint_type; 1417 1418 ep_index = xhci_get_endpoint_index(&ep->desc); 1419 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index); 1420 1421 endpoint_type = xhci_get_endpoint_type(udev, ep); 1422 if (!endpoint_type) 1423 return -EINVAL; 1424 ep_ctx->ep_info2 = cpu_to_le32(endpoint_type); 1425 1426 type = usb_endpoint_type(&ep->desc); 1427 /* Set up the endpoint ring */ 1428 virt_dev->eps[ep_index].new_ring = 1429 xhci_ring_alloc(xhci, 2, 1, type, mem_flags); 1430 if (!virt_dev->eps[ep_index].new_ring) { 1431 /* Attempt to use the ring cache */ 1432 if (virt_dev->num_rings_cached == 0) 1433 return -ENOMEM; 1434 virt_dev->eps[ep_index].new_ring = 1435 virt_dev->ring_cache[virt_dev->num_rings_cached]; 1436 virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL; 1437 virt_dev->num_rings_cached--; 1438 xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring, 1439 1, type); 1440 } 1441 virt_dev->eps[ep_index].skip = false; 1442 ep_ring = virt_dev->eps[ep_index].new_ring; 1443 ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | ep_ring->cycle_state); 1444 1445 ep_ctx->ep_info = cpu_to_le32(xhci_get_endpoint_interval(udev, ep) 1446 | EP_MULT(xhci_get_endpoint_mult(udev, ep))); 1447 1448 /* FIXME dig Mult and streams info out of ep companion desc */ 1449 1450 /* Allow 3 retries for everything but isoc; 1451 * CErr shall be set to 0 for Isoch endpoints. 1452 */ 1453 if (!usb_endpoint_xfer_isoc(&ep->desc)) 1454 ep_ctx->ep_info2 |= cpu_to_le32(ERROR_COUNT(3)); 1455 else 1456 ep_ctx->ep_info2 |= cpu_to_le32(ERROR_COUNT(0)); 1457 1458 /* Set the max packet size and max burst */ 1459 max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc)); 1460 max_burst = 0; 1461 switch (udev->speed) { 1462 case USB_SPEED_SUPER: 1463 /* dig out max burst from ep companion desc */ 1464 max_burst = ep->ss_ep_comp.bMaxBurst; 1465 break; 1466 case USB_SPEED_HIGH: 1467 /* Some devices get this wrong */ 1468 if (usb_endpoint_xfer_bulk(&ep->desc)) 1469 max_packet = 512; 1470 /* bits 11:12 specify the number of additional transaction 1471 * opportunities per microframe (USB 2.0, section 9.6.6) 1472 */ 1473 if (usb_endpoint_xfer_isoc(&ep->desc) || 1474 usb_endpoint_xfer_int(&ep->desc)) { 1475 max_burst = (usb_endpoint_maxp(&ep->desc) 1476 & 0x1800) >> 11; 1477 } 1478 break; 1479 case USB_SPEED_FULL: 1480 case USB_SPEED_LOW: 1481 break; 1482 default: 1483 BUG(); 1484 } 1485 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet) | 1486 MAX_BURST(max_burst)); 1487 max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep); 1488 ep_ctx->tx_info = cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload)); 1489 1490 /* 1491 * XXX no idea how to calculate the average TRB buffer length for bulk 1492 * endpoints, as the driver gives us no clue how big each scatter gather 1493 * list entry (or buffer) is going to be. 1494 * 1495 * For isochronous and interrupt endpoints, we set it to the max 1496 * available, until we have new API in the USB core to allow drivers to 1497 * declare how much bandwidth they actually need. 1498 * 1499 * Normally, it would be calculated by taking the total of the buffer 1500 * lengths in the TD and then dividing by the number of TRBs in a TD, 1501 * including link TRBs, No-op TRBs, and Event data TRBs. Since we don't 1502 * use Event Data TRBs, and we don't chain in a link TRB on short 1503 * transfers, we're basically dividing by 1. 1504 * 1505 * xHCI 1.0 specification indicates that the Average TRB Length should 1506 * be set to 8 for control endpoints. 1507 */ 1508 if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version == 0x100) 1509 ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8)); 1510 else 1511 ep_ctx->tx_info |= 1512 cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload)); 1513 1514 /* FIXME Debug endpoint context */ 1515 return 0; 1516 } 1517 1518 void xhci_endpoint_zero(struct xhci_hcd *xhci, 1519 struct xhci_virt_device *virt_dev, 1520 struct usb_host_endpoint *ep) 1521 { 1522 unsigned int ep_index; 1523 struct xhci_ep_ctx *ep_ctx; 1524 1525 ep_index = xhci_get_endpoint_index(&ep->desc); 1526 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index); 1527 1528 ep_ctx->ep_info = 0; 1529 ep_ctx->ep_info2 = 0; 1530 ep_ctx->deq = 0; 1531 ep_ctx->tx_info = 0; 1532 /* Don't free the endpoint ring until the set interface or configuration 1533 * request succeeds. 1534 */ 1535 } 1536 1537 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info) 1538 { 1539 bw_info->ep_interval = 0; 1540 bw_info->mult = 0; 1541 bw_info->num_packets = 0; 1542 bw_info->max_packet_size = 0; 1543 bw_info->type = 0; 1544 bw_info->max_esit_payload = 0; 1545 } 1546 1547 void xhci_update_bw_info(struct xhci_hcd *xhci, 1548 struct xhci_container_ctx *in_ctx, 1549 struct xhci_input_control_ctx *ctrl_ctx, 1550 struct xhci_virt_device *virt_dev) 1551 { 1552 struct xhci_bw_info *bw_info; 1553 struct xhci_ep_ctx *ep_ctx; 1554 unsigned int ep_type; 1555 int i; 1556 1557 for (i = 1; i < 31; ++i) { 1558 bw_info = &virt_dev->eps[i].bw_info; 1559 1560 /* We can't tell what endpoint type is being dropped, but 1561 * unconditionally clearing the bandwidth info for non-periodic 1562 * endpoints should be harmless because the info will never be 1563 * set in the first place. 1564 */ 1565 if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) { 1566 /* Dropped endpoint */ 1567 xhci_clear_endpoint_bw_info(bw_info); 1568 continue; 1569 } 1570 1571 if (EP_IS_ADDED(ctrl_ctx, i)) { 1572 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i); 1573 ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2)); 1574 1575 /* Ignore non-periodic endpoints */ 1576 if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP && 1577 ep_type != ISOC_IN_EP && 1578 ep_type != INT_IN_EP) 1579 continue; 1580 1581 /* Added or changed endpoint */ 1582 bw_info->ep_interval = CTX_TO_EP_INTERVAL( 1583 le32_to_cpu(ep_ctx->ep_info)); 1584 /* Number of packets and mult are zero-based in the 1585 * input context, but we want one-based for the 1586 * interval table. 1587 */ 1588 bw_info->mult = CTX_TO_EP_MULT( 1589 le32_to_cpu(ep_ctx->ep_info)) + 1; 1590 bw_info->num_packets = CTX_TO_MAX_BURST( 1591 le32_to_cpu(ep_ctx->ep_info2)) + 1; 1592 bw_info->max_packet_size = MAX_PACKET_DECODED( 1593 le32_to_cpu(ep_ctx->ep_info2)); 1594 bw_info->type = ep_type; 1595 bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD( 1596 le32_to_cpu(ep_ctx->tx_info)); 1597 } 1598 } 1599 } 1600 1601 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy. 1602 * Useful when you want to change one particular aspect of the endpoint and then 1603 * issue a configure endpoint command. 1604 */ 1605 void xhci_endpoint_copy(struct xhci_hcd *xhci, 1606 struct xhci_container_ctx *in_ctx, 1607 struct xhci_container_ctx *out_ctx, 1608 unsigned int ep_index) 1609 { 1610 struct xhci_ep_ctx *out_ep_ctx; 1611 struct xhci_ep_ctx *in_ep_ctx; 1612 1613 out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); 1614 in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index); 1615 1616 in_ep_ctx->ep_info = out_ep_ctx->ep_info; 1617 in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2; 1618 in_ep_ctx->deq = out_ep_ctx->deq; 1619 in_ep_ctx->tx_info = out_ep_ctx->tx_info; 1620 } 1621 1622 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx. 1623 * Useful when you want to change one particular aspect of the endpoint and then 1624 * issue a configure endpoint command. Only the context entries field matters, 1625 * but we'll copy the whole thing anyway. 1626 */ 1627 void xhci_slot_copy(struct xhci_hcd *xhci, 1628 struct xhci_container_ctx *in_ctx, 1629 struct xhci_container_ctx *out_ctx) 1630 { 1631 struct xhci_slot_ctx *in_slot_ctx; 1632 struct xhci_slot_ctx *out_slot_ctx; 1633 1634 in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx); 1635 out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx); 1636 1637 in_slot_ctx->dev_info = out_slot_ctx->dev_info; 1638 in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2; 1639 in_slot_ctx->tt_info = out_slot_ctx->tt_info; 1640 in_slot_ctx->dev_state = out_slot_ctx->dev_state; 1641 } 1642 1643 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */ 1644 static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags) 1645 { 1646 int i; 1647 struct device *dev = xhci_to_hcd(xhci)->self.controller; 1648 int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2); 1649 1650 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 1651 "Allocating %d scratchpad buffers", num_sp); 1652 1653 if (!num_sp) 1654 return 0; 1655 1656 xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags); 1657 if (!xhci->scratchpad) 1658 goto fail_sp; 1659 1660 xhci->scratchpad->sp_array = dma_alloc_coherent(dev, 1661 num_sp * sizeof(u64), 1662 &xhci->scratchpad->sp_dma, flags); 1663 if (!xhci->scratchpad->sp_array) 1664 goto fail_sp2; 1665 1666 xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags); 1667 if (!xhci->scratchpad->sp_buffers) 1668 goto fail_sp3; 1669 1670 xhci->scratchpad->sp_dma_buffers = 1671 kzalloc(sizeof(dma_addr_t) * num_sp, flags); 1672 1673 if (!xhci->scratchpad->sp_dma_buffers) 1674 goto fail_sp4; 1675 1676 xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma); 1677 for (i = 0; i < num_sp; i++) { 1678 dma_addr_t dma; 1679 void *buf = dma_alloc_coherent(dev, xhci->page_size, &dma, 1680 flags); 1681 if (!buf) 1682 goto fail_sp5; 1683 1684 xhci->scratchpad->sp_array[i] = dma; 1685 xhci->scratchpad->sp_buffers[i] = buf; 1686 xhci->scratchpad->sp_dma_buffers[i] = dma; 1687 } 1688 1689 return 0; 1690 1691 fail_sp5: 1692 for (i = i - 1; i >= 0; i--) { 1693 dma_free_coherent(dev, xhci->page_size, 1694 xhci->scratchpad->sp_buffers[i], 1695 xhci->scratchpad->sp_dma_buffers[i]); 1696 } 1697 kfree(xhci->scratchpad->sp_dma_buffers); 1698 1699 fail_sp4: 1700 kfree(xhci->scratchpad->sp_buffers); 1701 1702 fail_sp3: 1703 dma_free_coherent(dev, num_sp * sizeof(u64), 1704 xhci->scratchpad->sp_array, 1705 xhci->scratchpad->sp_dma); 1706 1707 fail_sp2: 1708 kfree(xhci->scratchpad); 1709 xhci->scratchpad = NULL; 1710 1711 fail_sp: 1712 return -ENOMEM; 1713 } 1714 1715 static void scratchpad_free(struct xhci_hcd *xhci) 1716 { 1717 int num_sp; 1718 int i; 1719 struct device *dev = xhci_to_hcd(xhci)->self.controller; 1720 1721 if (!xhci->scratchpad) 1722 return; 1723 1724 num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2); 1725 1726 for (i = 0; i < num_sp; i++) { 1727 dma_free_coherent(dev, xhci->page_size, 1728 xhci->scratchpad->sp_buffers[i], 1729 xhci->scratchpad->sp_dma_buffers[i]); 1730 } 1731 kfree(xhci->scratchpad->sp_dma_buffers); 1732 kfree(xhci->scratchpad->sp_buffers); 1733 dma_free_coherent(dev, num_sp * sizeof(u64), 1734 xhci->scratchpad->sp_array, 1735 xhci->scratchpad->sp_dma); 1736 kfree(xhci->scratchpad); 1737 xhci->scratchpad = NULL; 1738 } 1739 1740 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 1741 bool allocate_in_ctx, bool allocate_completion, 1742 gfp_t mem_flags) 1743 { 1744 struct xhci_command *command; 1745 1746 command = kzalloc(sizeof(*command), mem_flags); 1747 if (!command) 1748 return NULL; 1749 1750 if (allocate_in_ctx) { 1751 command->in_ctx = 1752 xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, 1753 mem_flags); 1754 if (!command->in_ctx) { 1755 kfree(command); 1756 return NULL; 1757 } 1758 } 1759 1760 if (allocate_completion) { 1761 command->completion = 1762 kzalloc(sizeof(struct completion), mem_flags); 1763 if (!command->completion) { 1764 xhci_free_container_ctx(xhci, command->in_ctx); 1765 kfree(command); 1766 return NULL; 1767 } 1768 init_completion(command->completion); 1769 } 1770 1771 command->status = 0; 1772 INIT_LIST_HEAD(&command->cmd_list); 1773 return command; 1774 } 1775 1776 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv) 1777 { 1778 if (urb_priv) { 1779 kfree(urb_priv->td[0]); 1780 kfree(urb_priv); 1781 } 1782 } 1783 1784 void xhci_free_command(struct xhci_hcd *xhci, 1785 struct xhci_command *command) 1786 { 1787 xhci_free_container_ctx(xhci, 1788 command->in_ctx); 1789 kfree(command->completion); 1790 kfree(command); 1791 } 1792 1793 void xhci_mem_cleanup(struct xhci_hcd *xhci) 1794 { 1795 struct device *dev = xhci_to_hcd(xhci)->self.controller; 1796 int size; 1797 int i, j, num_ports; 1798 1799 del_timer_sync(&xhci->cmd_timer); 1800 1801 /* Free the Event Ring Segment Table and the actual Event Ring */ 1802 size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries); 1803 if (xhci->erst.entries) 1804 dma_free_coherent(dev, size, 1805 xhci->erst.entries, xhci->erst.erst_dma_addr); 1806 xhci->erst.entries = NULL; 1807 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed ERST"); 1808 if (xhci->event_ring) 1809 xhci_ring_free(xhci, xhci->event_ring); 1810 xhci->event_ring = NULL; 1811 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed event ring"); 1812 1813 if (xhci->lpm_command) 1814 xhci_free_command(xhci, xhci->lpm_command); 1815 if (xhci->cmd_ring) 1816 xhci_ring_free(xhci, xhci->cmd_ring); 1817 xhci->cmd_ring = NULL; 1818 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed command ring"); 1819 xhci_cleanup_command_queue(xhci); 1820 1821 num_ports = HCS_MAX_PORTS(xhci->hcs_params1); 1822 for (i = 0; i < num_ports; i++) { 1823 struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table; 1824 for (j = 0; j < XHCI_MAX_INTERVAL; j++) { 1825 struct list_head *ep = &bwt->interval_bw[j].endpoints; 1826 while (!list_empty(ep)) 1827 list_del_init(ep->next); 1828 } 1829 } 1830 1831 for (i = 1; i < MAX_HC_SLOTS; ++i) 1832 xhci_free_virt_device(xhci, i); 1833 1834 if (xhci->segment_pool) 1835 dma_pool_destroy(xhci->segment_pool); 1836 xhci->segment_pool = NULL; 1837 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed segment pool"); 1838 1839 if (xhci->device_pool) 1840 dma_pool_destroy(xhci->device_pool); 1841 xhci->device_pool = NULL; 1842 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed device context pool"); 1843 1844 if (xhci->small_streams_pool) 1845 dma_pool_destroy(xhci->small_streams_pool); 1846 xhci->small_streams_pool = NULL; 1847 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 1848 "Freed small stream array pool"); 1849 1850 if (xhci->medium_streams_pool) 1851 dma_pool_destroy(xhci->medium_streams_pool); 1852 xhci->medium_streams_pool = NULL; 1853 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 1854 "Freed medium stream array pool"); 1855 1856 if (xhci->dcbaa) 1857 dma_free_coherent(dev, sizeof(*xhci->dcbaa), 1858 xhci->dcbaa, xhci->dcbaa->dma); 1859 xhci->dcbaa = NULL; 1860 1861 scratchpad_free(xhci); 1862 1863 if (!xhci->rh_bw) 1864 goto no_bw; 1865 1866 for (i = 0; i < num_ports; i++) { 1867 struct xhci_tt_bw_info *tt, *n; 1868 list_for_each_entry_safe(tt, n, &xhci->rh_bw[i].tts, tt_list) { 1869 list_del(&tt->tt_list); 1870 kfree(tt); 1871 } 1872 } 1873 1874 no_bw: 1875 xhci->cmd_ring_reserved_trbs = 0; 1876 xhci->num_usb2_ports = 0; 1877 xhci->num_usb3_ports = 0; 1878 xhci->num_active_eps = 0; 1879 kfree(xhci->usb2_ports); 1880 kfree(xhci->usb3_ports); 1881 kfree(xhci->port_array); 1882 kfree(xhci->rh_bw); 1883 kfree(xhci->ext_caps); 1884 1885 xhci->page_size = 0; 1886 xhci->page_shift = 0; 1887 xhci->bus_state[0].bus_suspended = 0; 1888 xhci->bus_state[1].bus_suspended = 0; 1889 } 1890 1891 static int xhci_test_trb_in_td(struct xhci_hcd *xhci, 1892 struct xhci_segment *input_seg, 1893 union xhci_trb *start_trb, 1894 union xhci_trb *end_trb, 1895 dma_addr_t input_dma, 1896 struct xhci_segment *result_seg, 1897 char *test_name, int test_number) 1898 { 1899 unsigned long long start_dma; 1900 unsigned long long end_dma; 1901 struct xhci_segment *seg; 1902 1903 start_dma = xhci_trb_virt_to_dma(input_seg, start_trb); 1904 end_dma = xhci_trb_virt_to_dma(input_seg, end_trb); 1905 1906 seg = trb_in_td(input_seg, start_trb, end_trb, input_dma); 1907 if (seg != result_seg) { 1908 xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n", 1909 test_name, test_number); 1910 xhci_warn(xhci, "Tested TRB math w/ seg %p and " 1911 "input DMA 0x%llx\n", 1912 input_seg, 1913 (unsigned long long) input_dma); 1914 xhci_warn(xhci, "starting TRB %p (0x%llx DMA), " 1915 "ending TRB %p (0x%llx DMA)\n", 1916 start_trb, start_dma, 1917 end_trb, end_dma); 1918 xhci_warn(xhci, "Expected seg %p, got seg %p\n", 1919 result_seg, seg); 1920 return -1; 1921 } 1922 return 0; 1923 } 1924 1925 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */ 1926 static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags) 1927 { 1928 struct { 1929 dma_addr_t input_dma; 1930 struct xhci_segment *result_seg; 1931 } simple_test_vector [] = { 1932 /* A zeroed DMA field should fail */ 1933 { 0, NULL }, 1934 /* One TRB before the ring start should fail */ 1935 { xhci->event_ring->first_seg->dma - 16, NULL }, 1936 /* One byte before the ring start should fail */ 1937 { xhci->event_ring->first_seg->dma - 1, NULL }, 1938 /* Starting TRB should succeed */ 1939 { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg }, 1940 /* Ending TRB should succeed */ 1941 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16, 1942 xhci->event_ring->first_seg }, 1943 /* One byte after the ring end should fail */ 1944 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL }, 1945 /* One TRB after the ring end should fail */ 1946 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL }, 1947 /* An address of all ones should fail */ 1948 { (dma_addr_t) (~0), NULL }, 1949 }; 1950 struct { 1951 struct xhci_segment *input_seg; 1952 union xhci_trb *start_trb; 1953 union xhci_trb *end_trb; 1954 dma_addr_t input_dma; 1955 struct xhci_segment *result_seg; 1956 } complex_test_vector [] = { 1957 /* Test feeding a valid DMA address from a different ring */ 1958 { .input_seg = xhci->event_ring->first_seg, 1959 .start_trb = xhci->event_ring->first_seg->trbs, 1960 .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], 1961 .input_dma = xhci->cmd_ring->first_seg->dma, 1962 .result_seg = NULL, 1963 }, 1964 /* Test feeding a valid end TRB from a different ring */ 1965 { .input_seg = xhci->event_ring->first_seg, 1966 .start_trb = xhci->event_ring->first_seg->trbs, 1967 .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], 1968 .input_dma = xhci->cmd_ring->first_seg->dma, 1969 .result_seg = NULL, 1970 }, 1971 /* Test feeding a valid start and end TRB from a different ring */ 1972 { .input_seg = xhci->event_ring->first_seg, 1973 .start_trb = xhci->cmd_ring->first_seg->trbs, 1974 .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], 1975 .input_dma = xhci->cmd_ring->first_seg->dma, 1976 .result_seg = NULL, 1977 }, 1978 /* TRB in this ring, but after this TD */ 1979 { .input_seg = xhci->event_ring->first_seg, 1980 .start_trb = &xhci->event_ring->first_seg->trbs[0], 1981 .end_trb = &xhci->event_ring->first_seg->trbs[3], 1982 .input_dma = xhci->event_ring->first_seg->dma + 4*16, 1983 .result_seg = NULL, 1984 }, 1985 /* TRB in this ring, but before this TD */ 1986 { .input_seg = xhci->event_ring->first_seg, 1987 .start_trb = &xhci->event_ring->first_seg->trbs[3], 1988 .end_trb = &xhci->event_ring->first_seg->trbs[6], 1989 .input_dma = xhci->event_ring->first_seg->dma + 2*16, 1990 .result_seg = NULL, 1991 }, 1992 /* TRB in this ring, but after this wrapped TD */ 1993 { .input_seg = xhci->event_ring->first_seg, 1994 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], 1995 .end_trb = &xhci->event_ring->first_seg->trbs[1], 1996 .input_dma = xhci->event_ring->first_seg->dma + 2*16, 1997 .result_seg = NULL, 1998 }, 1999 /* TRB in this ring, but before this wrapped TD */ 2000 { .input_seg = xhci->event_ring->first_seg, 2001 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], 2002 .end_trb = &xhci->event_ring->first_seg->trbs[1], 2003 .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16, 2004 .result_seg = NULL, 2005 }, 2006 /* TRB not in this ring, and we have a wrapped TD */ 2007 { .input_seg = xhci->event_ring->first_seg, 2008 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], 2009 .end_trb = &xhci->event_ring->first_seg->trbs[1], 2010 .input_dma = xhci->cmd_ring->first_seg->dma + 2*16, 2011 .result_seg = NULL, 2012 }, 2013 }; 2014 2015 unsigned int num_tests; 2016 int i, ret; 2017 2018 num_tests = ARRAY_SIZE(simple_test_vector); 2019 for (i = 0; i < num_tests; i++) { 2020 ret = xhci_test_trb_in_td(xhci, 2021 xhci->event_ring->first_seg, 2022 xhci->event_ring->first_seg->trbs, 2023 &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], 2024 simple_test_vector[i].input_dma, 2025 simple_test_vector[i].result_seg, 2026 "Simple", i); 2027 if (ret < 0) 2028 return ret; 2029 } 2030 2031 num_tests = ARRAY_SIZE(complex_test_vector); 2032 for (i = 0; i < num_tests; i++) { 2033 ret = xhci_test_trb_in_td(xhci, 2034 complex_test_vector[i].input_seg, 2035 complex_test_vector[i].start_trb, 2036 complex_test_vector[i].end_trb, 2037 complex_test_vector[i].input_dma, 2038 complex_test_vector[i].result_seg, 2039 "Complex", i); 2040 if (ret < 0) 2041 return ret; 2042 } 2043 xhci_dbg(xhci, "TRB math tests passed.\n"); 2044 return 0; 2045 } 2046 2047 static void xhci_set_hc_event_deq(struct xhci_hcd *xhci) 2048 { 2049 u64 temp; 2050 dma_addr_t deq; 2051 2052 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, 2053 xhci->event_ring->dequeue); 2054 if (deq == 0 && !in_interrupt()) 2055 xhci_warn(xhci, "WARN something wrong with SW event ring " 2056 "dequeue ptr.\n"); 2057 /* Update HC event ring dequeue pointer */ 2058 temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); 2059 temp &= ERST_PTR_MASK; 2060 /* Don't clear the EHB bit (which is RW1C) because 2061 * there might be more events to service. 2062 */ 2063 temp &= ~ERST_EHB; 2064 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2065 "// Write event ring dequeue pointer, " 2066 "preserving EHB bit"); 2067 xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp, 2068 &xhci->ir_set->erst_dequeue); 2069 } 2070 2071 static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports, 2072 __le32 __iomem *addr, u8 major_revision, int max_caps) 2073 { 2074 u32 temp, port_offset, port_count; 2075 int i; 2076 2077 if (major_revision > 0x03) { 2078 xhci_warn(xhci, "Ignoring unknown port speed, " 2079 "Ext Cap %p, revision = 0x%x\n", 2080 addr, major_revision); 2081 /* Ignoring port protocol we can't understand. FIXME */ 2082 return; 2083 } 2084 2085 /* Port offset and count in the third dword, see section 7.2 */ 2086 temp = readl(addr + 2); 2087 port_offset = XHCI_EXT_PORT_OFF(temp); 2088 port_count = XHCI_EXT_PORT_COUNT(temp); 2089 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2090 "Ext Cap %p, port offset = %u, " 2091 "count = %u, revision = 0x%x", 2092 addr, port_offset, port_count, major_revision); 2093 /* Port count includes the current port offset */ 2094 if (port_offset == 0 || (port_offset + port_count - 1) > num_ports) 2095 /* WTF? "Valid values are ‘1’ to MaxPorts" */ 2096 return; 2097 2098 /* cache usb2 port capabilities */ 2099 if (major_revision < 0x03 && xhci->num_ext_caps < max_caps) 2100 xhci->ext_caps[xhci->num_ext_caps++] = temp; 2101 2102 /* Check the host's USB2 LPM capability */ 2103 if ((xhci->hci_version == 0x96) && (major_revision != 0x03) && 2104 (temp & XHCI_L1C)) { 2105 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2106 "xHCI 0.96: support USB2 software lpm"); 2107 xhci->sw_lpm_support = 1; 2108 } 2109 2110 if ((xhci->hci_version >= 0x100) && (major_revision != 0x03)) { 2111 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2112 "xHCI 1.0: support USB2 software lpm"); 2113 xhci->sw_lpm_support = 1; 2114 if (temp & XHCI_HLC) { 2115 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2116 "xHCI 1.0: support USB2 hardware lpm"); 2117 xhci->hw_lpm_support = 1; 2118 } 2119 } 2120 2121 port_offset--; 2122 for (i = port_offset; i < (port_offset + port_count); i++) { 2123 /* Duplicate entry. Ignore the port if the revisions differ. */ 2124 if (xhci->port_array[i] != 0) { 2125 xhci_warn(xhci, "Duplicate port entry, Ext Cap %p," 2126 " port %u\n", addr, i); 2127 xhci_warn(xhci, "Port was marked as USB %u, " 2128 "duplicated as USB %u\n", 2129 xhci->port_array[i], major_revision); 2130 /* Only adjust the roothub port counts if we haven't 2131 * found a similar duplicate. 2132 */ 2133 if (xhci->port_array[i] != major_revision && 2134 xhci->port_array[i] != DUPLICATE_ENTRY) { 2135 if (xhci->port_array[i] == 0x03) 2136 xhci->num_usb3_ports--; 2137 else 2138 xhci->num_usb2_ports--; 2139 xhci->port_array[i] = DUPLICATE_ENTRY; 2140 } 2141 /* FIXME: Should we disable the port? */ 2142 continue; 2143 } 2144 xhci->port_array[i] = major_revision; 2145 if (major_revision == 0x03) 2146 xhci->num_usb3_ports++; 2147 else 2148 xhci->num_usb2_ports++; 2149 } 2150 /* FIXME: Should we disable ports not in the Extended Capabilities? */ 2151 } 2152 2153 /* 2154 * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that 2155 * specify what speeds each port is supposed to be. We can't count on the port 2156 * speed bits in the PORTSC register being correct until a device is connected, 2157 * but we need to set up the two fake roothubs with the correct number of USB 2158 * 3.0 and USB 2.0 ports at host controller initialization time. 2159 */ 2160 static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags) 2161 { 2162 __le32 __iomem *addr, *tmp_addr; 2163 u32 offset, tmp_offset; 2164 unsigned int num_ports; 2165 int i, j, port_index; 2166 int cap_count = 0; 2167 2168 addr = &xhci->cap_regs->hcc_params; 2169 offset = XHCI_HCC_EXT_CAPS(readl(addr)); 2170 if (offset == 0) { 2171 xhci_err(xhci, "No Extended Capability registers, " 2172 "unable to set up roothub.\n"); 2173 return -ENODEV; 2174 } 2175 2176 num_ports = HCS_MAX_PORTS(xhci->hcs_params1); 2177 xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags); 2178 if (!xhci->port_array) 2179 return -ENOMEM; 2180 2181 xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags); 2182 if (!xhci->rh_bw) 2183 return -ENOMEM; 2184 for (i = 0; i < num_ports; i++) { 2185 struct xhci_interval_bw_table *bw_table; 2186 2187 INIT_LIST_HEAD(&xhci->rh_bw[i].tts); 2188 bw_table = &xhci->rh_bw[i].bw_table; 2189 for (j = 0; j < XHCI_MAX_INTERVAL; j++) 2190 INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints); 2191 } 2192 2193 /* 2194 * For whatever reason, the first capability offset is from the 2195 * capability register base, not from the HCCPARAMS register. 2196 * See section 5.3.6 for offset calculation. 2197 */ 2198 addr = &xhci->cap_regs->hc_capbase + offset; 2199 2200 tmp_addr = addr; 2201 tmp_offset = offset; 2202 2203 /* count extended protocol capability entries for later caching */ 2204 do { 2205 u32 cap_id; 2206 cap_id = readl(tmp_addr); 2207 if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL) 2208 cap_count++; 2209 tmp_offset = XHCI_EXT_CAPS_NEXT(cap_id); 2210 tmp_addr += tmp_offset; 2211 } while (tmp_offset); 2212 2213 xhci->ext_caps = kzalloc(sizeof(*xhci->ext_caps) * cap_count, flags); 2214 if (!xhci->ext_caps) 2215 return -ENOMEM; 2216 2217 while (1) { 2218 u32 cap_id; 2219 2220 cap_id = readl(addr); 2221 if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL) 2222 xhci_add_in_port(xhci, num_ports, addr, 2223 (u8) XHCI_EXT_PORT_MAJOR(cap_id), 2224 cap_count); 2225 offset = XHCI_EXT_CAPS_NEXT(cap_id); 2226 if (!offset || (xhci->num_usb2_ports + xhci->num_usb3_ports) 2227 == num_ports) 2228 break; 2229 /* 2230 * Once you're into the Extended Capabilities, the offset is 2231 * always relative to the register holding the offset. 2232 */ 2233 addr += offset; 2234 } 2235 2236 if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) { 2237 xhci_warn(xhci, "No ports on the roothubs?\n"); 2238 return -ENODEV; 2239 } 2240 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2241 "Found %u USB 2.0 ports and %u USB 3.0 ports.", 2242 xhci->num_usb2_ports, xhci->num_usb3_ports); 2243 2244 /* Place limits on the number of roothub ports so that the hub 2245 * descriptors aren't longer than the USB core will allocate. 2246 */ 2247 if (xhci->num_usb3_ports > 15) { 2248 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2249 "Limiting USB 3.0 roothub ports to 15."); 2250 xhci->num_usb3_ports = 15; 2251 } 2252 if (xhci->num_usb2_ports > USB_MAXCHILDREN) { 2253 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2254 "Limiting USB 2.0 roothub ports to %u.", 2255 USB_MAXCHILDREN); 2256 xhci->num_usb2_ports = USB_MAXCHILDREN; 2257 } 2258 2259 /* 2260 * Note we could have all USB 3.0 ports, or all USB 2.0 ports. 2261 * Not sure how the USB core will handle a hub with no ports... 2262 */ 2263 if (xhci->num_usb2_ports) { 2264 xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)* 2265 xhci->num_usb2_ports, flags); 2266 if (!xhci->usb2_ports) 2267 return -ENOMEM; 2268 2269 port_index = 0; 2270 for (i = 0; i < num_ports; i++) { 2271 if (xhci->port_array[i] == 0x03 || 2272 xhci->port_array[i] == 0 || 2273 xhci->port_array[i] == DUPLICATE_ENTRY) 2274 continue; 2275 2276 xhci->usb2_ports[port_index] = 2277 &xhci->op_regs->port_status_base + 2278 NUM_PORT_REGS*i; 2279 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2280 "USB 2.0 port at index %u, " 2281 "addr = %p", i, 2282 xhci->usb2_ports[port_index]); 2283 port_index++; 2284 if (port_index == xhci->num_usb2_ports) 2285 break; 2286 } 2287 } 2288 if (xhci->num_usb3_ports) { 2289 xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)* 2290 xhci->num_usb3_ports, flags); 2291 if (!xhci->usb3_ports) 2292 return -ENOMEM; 2293 2294 port_index = 0; 2295 for (i = 0; i < num_ports; i++) 2296 if (xhci->port_array[i] == 0x03) { 2297 xhci->usb3_ports[port_index] = 2298 &xhci->op_regs->port_status_base + 2299 NUM_PORT_REGS*i; 2300 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2301 "USB 3.0 port at index %u, " 2302 "addr = %p", i, 2303 xhci->usb3_ports[port_index]); 2304 port_index++; 2305 if (port_index == xhci->num_usb3_ports) 2306 break; 2307 } 2308 } 2309 return 0; 2310 } 2311 2312 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) 2313 { 2314 dma_addr_t dma; 2315 struct device *dev = xhci_to_hcd(xhci)->self.controller; 2316 unsigned int val, val2; 2317 u64 val_64; 2318 struct xhci_segment *seg; 2319 u32 page_size, temp; 2320 int i; 2321 2322 INIT_LIST_HEAD(&xhci->cmd_list); 2323 2324 page_size = readl(&xhci->op_regs->page_size); 2325 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2326 "Supported page size register = 0x%x", page_size); 2327 for (i = 0; i < 16; i++) { 2328 if ((0x1 & page_size) != 0) 2329 break; 2330 page_size = page_size >> 1; 2331 } 2332 if (i < 16) 2333 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2334 "Supported page size of %iK", (1 << (i+12)) / 1024); 2335 else 2336 xhci_warn(xhci, "WARN: no supported page size\n"); 2337 /* Use 4K pages, since that's common and the minimum the HC supports */ 2338 xhci->page_shift = 12; 2339 xhci->page_size = 1 << xhci->page_shift; 2340 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2341 "HCD page size set to %iK", xhci->page_size / 1024); 2342 2343 /* 2344 * Program the Number of Device Slots Enabled field in the CONFIG 2345 * register with the max value of slots the HC can handle. 2346 */ 2347 val = HCS_MAX_SLOTS(readl(&xhci->cap_regs->hcs_params1)); 2348 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2349 "// xHC can handle at most %d device slots.", val); 2350 val2 = readl(&xhci->op_regs->config_reg); 2351 val |= (val2 & ~HCS_SLOTS_MASK); 2352 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2353 "// Setting Max device slots reg = 0x%x.", val); 2354 writel(val, &xhci->op_regs->config_reg); 2355 2356 /* 2357 * Section 5.4.8 - doorbell array must be 2358 * "physically contiguous and 64-byte (cache line) aligned". 2359 */ 2360 xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma, 2361 GFP_KERNEL); 2362 if (!xhci->dcbaa) 2363 goto fail; 2364 memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa)); 2365 xhci->dcbaa->dma = dma; 2366 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2367 "// Device context base array address = 0x%llx (DMA), %p (virt)", 2368 (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa); 2369 xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr); 2370 2371 /* 2372 * Initialize the ring segment pool. The ring must be a contiguous 2373 * structure comprised of TRBs. The TRBs must be 16 byte aligned, 2374 * however, the command ring segment needs 64-byte aligned segments 2375 * and our use of dma addresses in the trb_address_map radix tree needs 2376 * TRB_SEGMENT_SIZE alignment, so we pick the greater alignment need. 2377 */ 2378 xhci->segment_pool = dma_pool_create("xHCI ring segments", dev, 2379 TRB_SEGMENT_SIZE, TRB_SEGMENT_SIZE, xhci->page_size); 2380 2381 /* See Table 46 and Note on Figure 55 */ 2382 xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev, 2383 2112, 64, xhci->page_size); 2384 if (!xhci->segment_pool || !xhci->device_pool) 2385 goto fail; 2386 2387 /* Linear stream context arrays don't have any boundary restrictions, 2388 * and only need to be 16-byte aligned. 2389 */ 2390 xhci->small_streams_pool = 2391 dma_pool_create("xHCI 256 byte stream ctx arrays", 2392 dev, SMALL_STREAM_ARRAY_SIZE, 16, 0); 2393 xhci->medium_streams_pool = 2394 dma_pool_create("xHCI 1KB stream ctx arrays", 2395 dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0); 2396 /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE 2397 * will be allocated with dma_alloc_coherent() 2398 */ 2399 2400 if (!xhci->small_streams_pool || !xhci->medium_streams_pool) 2401 goto fail; 2402 2403 /* Set up the command ring to have one segments for now. */ 2404 xhci->cmd_ring = xhci_ring_alloc(xhci, 1, 1, TYPE_COMMAND, flags); 2405 if (!xhci->cmd_ring) 2406 goto fail; 2407 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2408 "Allocated command ring at %p", xhci->cmd_ring); 2409 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "First segment DMA is 0x%llx", 2410 (unsigned long long)xhci->cmd_ring->first_seg->dma); 2411 2412 /* Set the address in the Command Ring Control register */ 2413 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); 2414 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) | 2415 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) | 2416 xhci->cmd_ring->cycle_state; 2417 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2418 "// Setting command ring address to 0x%x", val); 2419 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring); 2420 xhci_dbg_cmd_ptrs(xhci); 2421 2422 xhci->lpm_command = xhci_alloc_command(xhci, true, true, flags); 2423 if (!xhci->lpm_command) 2424 goto fail; 2425 2426 /* Reserve one command ring TRB for disabling LPM. 2427 * Since the USB core grabs the shared usb_bus bandwidth mutex before 2428 * disabling LPM, we only need to reserve one TRB for all devices. 2429 */ 2430 xhci->cmd_ring_reserved_trbs++; 2431 2432 val = readl(&xhci->cap_regs->db_off); 2433 val &= DBOFF_MASK; 2434 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2435 "// Doorbell array is located at offset 0x%x" 2436 " from cap regs base addr", val); 2437 xhci->dba = (void __iomem *) xhci->cap_regs + val; 2438 xhci_dbg_regs(xhci); 2439 xhci_print_run_regs(xhci); 2440 /* Set ir_set to interrupt register set 0 */ 2441 xhci->ir_set = &xhci->run_regs->ir_set[0]; 2442 2443 /* 2444 * Event ring setup: Allocate a normal ring, but also setup 2445 * the event ring segment table (ERST). Section 4.9.3. 2446 */ 2447 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Allocating event ring"); 2448 xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, 1, TYPE_EVENT, 2449 flags); 2450 if (!xhci->event_ring) 2451 goto fail; 2452 if (xhci_check_trb_in_td_math(xhci, flags) < 0) 2453 goto fail; 2454 2455 xhci->erst.entries = dma_alloc_coherent(dev, 2456 sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS, &dma, 2457 GFP_KERNEL); 2458 if (!xhci->erst.entries) 2459 goto fail; 2460 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2461 "// Allocated event ring segment table at 0x%llx", 2462 (unsigned long long)dma); 2463 2464 memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS); 2465 xhci->erst.num_entries = ERST_NUM_SEGS; 2466 xhci->erst.erst_dma_addr = dma; 2467 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2468 "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx", 2469 xhci->erst.num_entries, 2470 xhci->erst.entries, 2471 (unsigned long long)xhci->erst.erst_dma_addr); 2472 2473 /* set ring base address and size for each segment table entry */ 2474 for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) { 2475 struct xhci_erst_entry *entry = &xhci->erst.entries[val]; 2476 entry->seg_addr = cpu_to_le64(seg->dma); 2477 entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT); 2478 entry->rsvd = 0; 2479 seg = seg->next; 2480 } 2481 2482 /* set ERST count with the number of entries in the segment table */ 2483 val = readl(&xhci->ir_set->erst_size); 2484 val &= ERST_SIZE_MASK; 2485 val |= ERST_NUM_SEGS; 2486 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2487 "// Write ERST size = %i to ir_set 0 (some bits preserved)", 2488 val); 2489 writel(val, &xhci->ir_set->erst_size); 2490 2491 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2492 "// Set ERST entries to point to event ring."); 2493 /* set the segment table base address */ 2494 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2495 "// Set ERST base address for ir_set 0 = 0x%llx", 2496 (unsigned long long)xhci->erst.erst_dma_addr); 2497 val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base); 2498 val_64 &= ERST_PTR_MASK; 2499 val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK); 2500 xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base); 2501 2502 /* Set the event ring dequeue address */ 2503 xhci_set_hc_event_deq(xhci); 2504 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2505 "Wrote ERST address to ir_set 0."); 2506 xhci_print_ir_set(xhci, 0); 2507 2508 /* init command timeout timer */ 2509 init_timer(&xhci->cmd_timer); 2510 xhci->cmd_timer.data = (unsigned long) xhci; 2511 xhci->cmd_timer.function = xhci_handle_command_timeout; 2512 2513 /* 2514 * XXX: Might need to set the Interrupter Moderation Register to 2515 * something other than the default (~1ms minimum between interrupts). 2516 * See section 5.5.1.2. 2517 */ 2518 init_completion(&xhci->addr_dev); 2519 for (i = 0; i < MAX_HC_SLOTS; ++i) 2520 xhci->devs[i] = NULL; 2521 for (i = 0; i < USB_MAXCHILDREN; ++i) { 2522 xhci->bus_state[0].resume_done[i] = 0; 2523 xhci->bus_state[1].resume_done[i] = 0; 2524 /* Only the USB 2.0 completions will ever be used. */ 2525 init_completion(&xhci->bus_state[1].rexit_done[i]); 2526 } 2527 2528 if (scratchpad_alloc(xhci, flags)) 2529 goto fail; 2530 if (xhci_setup_port_arrays(xhci, flags)) 2531 goto fail; 2532 2533 /* Enable USB 3.0 device notifications for function remote wake, which 2534 * is necessary for allowing USB 3.0 devices to do remote wakeup from 2535 * U3 (device suspend). 2536 */ 2537 temp = readl(&xhci->op_regs->dev_notification); 2538 temp &= ~DEV_NOTE_MASK; 2539 temp |= DEV_NOTE_FWAKE; 2540 writel(temp, &xhci->op_regs->dev_notification); 2541 2542 return 0; 2543 2544 fail: 2545 xhci_warn(xhci, "Couldn't initialize memory\n"); 2546 xhci_halt(xhci); 2547 xhci_reset(xhci); 2548 xhci_mem_cleanup(xhci); 2549 return -ENOMEM; 2550 } 2551