1 /* 2 * xHCI host controller driver 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/gfp.h> 24 #include <asm/unaligned.h> 25 26 #include "xhci.h" 27 28 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) 29 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ 30 PORT_RC | PORT_PLC | PORT_PE) 31 32 /* usb 1.1 root hub device descriptor */ 33 static u8 usb_bos_descriptor [] = { 34 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */ 35 USB_DT_BOS, /* __u8 bDescriptorType */ 36 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */ 37 0x1, /* __u8 bNumDeviceCaps */ 38 /* First device capability */ 39 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */ 40 USB_DT_DEVICE_CAPABILITY, /* Device Capability */ 41 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */ 42 0x00, /* bmAttributes, LTM off by default */ 43 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */ 44 0x03, /* bFunctionalitySupport, 45 USB 3.0 speed only */ 46 0x00, /* bU1DevExitLat, set later. */ 47 0x00, 0x00 /* __le16 bU2DevExitLat, set later. */ 48 }; 49 50 51 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci, 52 struct usb_hub_descriptor *desc, int ports) 53 { 54 u16 temp; 55 56 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */ 57 desc->bHubContrCurrent = 0; 58 59 desc->bNbrPorts = ports; 60 temp = 0; 61 /* Bits 1:0 - support per-port power switching, or power always on */ 62 if (HCC_PPC(xhci->hcc_params)) 63 temp |= HUB_CHAR_INDV_PORT_LPSM; 64 else 65 temp |= HUB_CHAR_NO_LPSM; 66 /* Bit 2 - root hubs are not part of a compound device */ 67 /* Bits 4:3 - individual port over current protection */ 68 temp |= HUB_CHAR_INDV_PORT_OCPM; 69 /* Bits 6:5 - no TTs in root ports */ 70 /* Bit 7 - no port indicators */ 71 desc->wHubCharacteristics = cpu_to_le16(temp); 72 } 73 74 /* Fill in the USB 2.0 roothub descriptor */ 75 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 76 struct usb_hub_descriptor *desc) 77 { 78 int ports; 79 u16 temp; 80 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8]; 81 u32 portsc; 82 unsigned int i; 83 84 ports = xhci->num_usb2_ports; 85 86 xhci_common_hub_descriptor(xhci, desc, ports); 87 desc->bDescriptorType = USB_DT_HUB; 88 temp = 1 + (ports / 8); 89 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; 90 91 /* The Device Removable bits are reported on a byte granularity. 92 * If the port doesn't exist within that byte, the bit is set to 0. 93 */ 94 memset(port_removable, 0, sizeof(port_removable)); 95 for (i = 0; i < ports; i++) { 96 portsc = xhci_readl(xhci, xhci->usb2_ports[i]); 97 /* If a device is removable, PORTSC reports a 0, same as in the 98 * hub descriptor DeviceRemovable bits. 99 */ 100 if (portsc & PORT_DEV_REMOVE) 101 /* This math is hairy because bit 0 of DeviceRemovable 102 * is reserved, and bit 1 is for port 1, etc. 103 */ 104 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8); 105 } 106 107 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN 108 * ports on it. The USB 2.0 specification says that there are two 109 * variable length fields at the end of the hub descriptor: 110 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than 111 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array 112 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to 113 * 0xFF, so we initialize the both arrays (DeviceRemovable and 114 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each 115 * set of ports that actually exist. 116 */ 117 memset(desc->u.hs.DeviceRemovable, 0xff, 118 sizeof(desc->u.hs.DeviceRemovable)); 119 memset(desc->u.hs.PortPwrCtrlMask, 0xff, 120 sizeof(desc->u.hs.PortPwrCtrlMask)); 121 122 for (i = 0; i < (ports + 1 + 7) / 8; i++) 123 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i], 124 sizeof(__u8)); 125 } 126 127 /* Fill in the USB 3.0 roothub descriptor */ 128 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 129 struct usb_hub_descriptor *desc) 130 { 131 int ports; 132 u16 port_removable; 133 u32 portsc; 134 unsigned int i; 135 136 ports = xhci->num_usb3_ports; 137 xhci_common_hub_descriptor(xhci, desc, ports); 138 desc->bDescriptorType = USB_DT_SS_HUB; 139 desc->bDescLength = USB_DT_SS_HUB_SIZE; 140 141 /* header decode latency should be zero for roothubs, 142 * see section 4.23.5.2. 143 */ 144 desc->u.ss.bHubHdrDecLat = 0; 145 desc->u.ss.wHubDelay = 0; 146 147 port_removable = 0; 148 /* bit 0 is reserved, bit 1 is for port 1, etc. */ 149 for (i = 0; i < ports; i++) { 150 portsc = xhci_readl(xhci, xhci->usb3_ports[i]); 151 if (portsc & PORT_DEV_REMOVE) 152 port_removable |= 1 << (i + 1); 153 } 154 memset(&desc->u.ss.DeviceRemovable, 155 (__force __u16) cpu_to_le16(port_removable), 156 sizeof(__u16)); 157 } 158 159 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 160 struct usb_hub_descriptor *desc) 161 { 162 163 if (hcd->speed == HCD_USB3) 164 xhci_usb3_hub_descriptor(hcd, xhci, desc); 165 else 166 xhci_usb2_hub_descriptor(hcd, xhci, desc); 167 168 } 169 170 static unsigned int xhci_port_speed(unsigned int port_status) 171 { 172 if (DEV_LOWSPEED(port_status)) 173 return USB_PORT_STAT_LOW_SPEED; 174 if (DEV_HIGHSPEED(port_status)) 175 return USB_PORT_STAT_HIGH_SPEED; 176 /* 177 * FIXME: Yes, we should check for full speed, but the core uses that as 178 * a default in portspeed() in usb/core/hub.c (which is the only place 179 * USB_PORT_STAT_*_SPEED is used). 180 */ 181 return 0; 182 } 183 184 /* 185 * These bits are Read Only (RO) and should be saved and written to the 186 * registers: 0, 3, 10:13, 30 187 * connect status, over-current status, port speed, and device removable. 188 * connect status and port speed are also sticky - meaning they're in 189 * the AUX well and they aren't changed by a hot, warm, or cold reset. 190 */ 191 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30)) 192 /* 193 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: 194 * bits 5:8, 9, 14:15, 25:27 195 * link state, port power, port indicator state, "wake on" enable state 196 */ 197 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25)) 198 /* 199 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: 200 * bit 4 (port reset) 201 */ 202 #define XHCI_PORT_RW1S ((1<<4)) 203 /* 204 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: 205 * bits 1, 17, 18, 19, 20, 21, 22, 23 206 * port enable/disable, and 207 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports), 208 * over-current, reset, link state, and L1 change 209 */ 210 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17)) 211 /* 212 * Bit 16 is RW, and writing a '1' to it causes the link state control to be 213 * latched in 214 */ 215 #define XHCI_PORT_RW ((1<<16)) 216 /* 217 * These bits are Reserved Zero (RsvdZ) and zero should be written to them: 218 * bits 2, 24, 28:31 219 */ 220 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28)) 221 222 /* 223 * Given a port state, this function returns a value that would result in the 224 * port being in the same state, if the value was written to the port status 225 * control register. 226 * Save Read Only (RO) bits and save read/write bits where 227 * writing a 0 clears the bit and writing a 1 sets the bit (RWS). 228 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. 229 */ 230 u32 xhci_port_state_to_neutral(u32 state) 231 { 232 /* Save read-only status and port state */ 233 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS); 234 } 235 236 /* 237 * find slot id based on port number. 238 * @port: The one-based port number from one of the two split roothubs. 239 */ 240 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 241 u16 port) 242 { 243 int slot_id; 244 int i; 245 enum usb_device_speed speed; 246 247 slot_id = 0; 248 for (i = 0; i < MAX_HC_SLOTS; i++) { 249 if (!xhci->devs[i]) 250 continue; 251 speed = xhci->devs[i]->udev->speed; 252 if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3)) 253 && xhci->devs[i]->fake_port == port) { 254 slot_id = i; 255 break; 256 } 257 } 258 259 return slot_id; 260 } 261 262 /* 263 * Stop device 264 * It issues stop endpoint command for EP 0 to 30. And wait the last command 265 * to complete. 266 * suspend will set to 1, if suspend bit need to set in command. 267 */ 268 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend) 269 { 270 struct xhci_virt_device *virt_dev; 271 struct xhci_command *cmd; 272 unsigned long flags; 273 int timeleft; 274 int ret; 275 int i; 276 277 ret = 0; 278 virt_dev = xhci->devs[slot_id]; 279 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO); 280 if (!cmd) { 281 xhci_dbg(xhci, "Couldn't allocate command structure.\n"); 282 return -ENOMEM; 283 } 284 285 spin_lock_irqsave(&xhci->lock, flags); 286 for (i = LAST_EP_INDEX; i > 0; i--) { 287 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) 288 xhci_queue_stop_endpoint(xhci, slot_id, i, suspend); 289 } 290 cmd->command_trb = xhci->cmd_ring->enqueue; 291 list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list); 292 xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend); 293 xhci_ring_cmd_db(xhci); 294 spin_unlock_irqrestore(&xhci->lock, flags); 295 296 /* Wait for last stop endpoint command to finish */ 297 timeleft = wait_for_completion_interruptible_timeout( 298 cmd->completion, 299 USB_CTRL_SET_TIMEOUT); 300 if (timeleft <= 0) { 301 xhci_warn(xhci, "%s while waiting for stop endpoint command\n", 302 timeleft == 0 ? "Timeout" : "Signal"); 303 spin_lock_irqsave(&xhci->lock, flags); 304 /* The timeout might have raced with the event ring handler, so 305 * only delete from the list if the item isn't poisoned. 306 */ 307 if (cmd->cmd_list.next != LIST_POISON1) 308 list_del(&cmd->cmd_list); 309 spin_unlock_irqrestore(&xhci->lock, flags); 310 ret = -ETIME; 311 goto command_cleanup; 312 } 313 314 command_cleanup: 315 xhci_free_command(xhci, cmd); 316 return ret; 317 } 318 319 /* 320 * Ring device, it rings the all doorbells unconditionally. 321 */ 322 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id) 323 { 324 int i; 325 326 for (i = 0; i < LAST_EP_INDEX + 1; i++) 327 if (xhci->devs[slot_id]->eps[i].ring && 328 xhci->devs[slot_id]->eps[i].ring->dequeue) 329 xhci_ring_ep_doorbell(xhci, slot_id, i, 0); 330 331 return; 332 } 333 334 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 335 u16 wIndex, __le32 __iomem *addr, u32 port_status) 336 { 337 /* Don't allow the USB core to disable SuperSpeed ports. */ 338 if (hcd->speed == HCD_USB3) { 339 xhci_dbg(xhci, "Ignoring request to disable " 340 "SuperSpeed port.\n"); 341 return; 342 } 343 344 /* Write 1 to disable the port */ 345 xhci_writel(xhci, port_status | PORT_PE, addr); 346 port_status = xhci_readl(xhci, addr); 347 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n", 348 wIndex, port_status); 349 } 350 351 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, 352 u16 wIndex, __le32 __iomem *addr, u32 port_status) 353 { 354 char *port_change_bit; 355 u32 status; 356 357 switch (wValue) { 358 case USB_PORT_FEAT_C_RESET: 359 status = PORT_RC; 360 port_change_bit = "reset"; 361 break; 362 case USB_PORT_FEAT_C_BH_PORT_RESET: 363 status = PORT_WRC; 364 port_change_bit = "warm(BH) reset"; 365 break; 366 case USB_PORT_FEAT_C_CONNECTION: 367 status = PORT_CSC; 368 port_change_bit = "connect"; 369 break; 370 case USB_PORT_FEAT_C_OVER_CURRENT: 371 status = PORT_OCC; 372 port_change_bit = "over-current"; 373 break; 374 case USB_PORT_FEAT_C_ENABLE: 375 status = PORT_PEC; 376 port_change_bit = "enable/disable"; 377 break; 378 case USB_PORT_FEAT_C_SUSPEND: 379 status = PORT_PLC; 380 port_change_bit = "suspend/resume"; 381 break; 382 case USB_PORT_FEAT_C_PORT_LINK_STATE: 383 status = PORT_PLC; 384 port_change_bit = "link state"; 385 break; 386 default: 387 /* Should never happen */ 388 return; 389 } 390 /* Change bits are all write 1 to clear */ 391 xhci_writel(xhci, port_status | status, addr); 392 port_status = xhci_readl(xhci, addr); 393 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n", 394 port_change_bit, wIndex, port_status); 395 } 396 397 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array) 398 { 399 int max_ports; 400 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 401 402 if (hcd->speed == HCD_USB3) { 403 max_ports = xhci->num_usb3_ports; 404 *port_array = xhci->usb3_ports; 405 } else { 406 max_ports = xhci->num_usb2_ports; 407 *port_array = xhci->usb2_ports; 408 } 409 410 return max_ports; 411 } 412 413 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, 414 int port_id, u32 link_state) 415 { 416 u32 temp; 417 418 temp = xhci_readl(xhci, port_array[port_id]); 419 temp = xhci_port_state_to_neutral(temp); 420 temp &= ~PORT_PLS_MASK; 421 temp |= PORT_LINK_STROBE | link_state; 422 xhci_writel(xhci, temp, port_array[port_id]); 423 } 424 425 void xhci_set_remote_wake_mask(struct xhci_hcd *xhci, 426 __le32 __iomem **port_array, int port_id, u16 wake_mask) 427 { 428 u32 temp; 429 430 temp = xhci_readl(xhci, port_array[port_id]); 431 temp = xhci_port_state_to_neutral(temp); 432 433 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT) 434 temp |= PORT_WKCONN_E; 435 else 436 temp &= ~PORT_WKCONN_E; 437 438 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT) 439 temp |= PORT_WKDISC_E; 440 else 441 temp &= ~PORT_WKDISC_E; 442 443 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT) 444 temp |= PORT_WKOC_E; 445 else 446 temp &= ~PORT_WKOC_E; 447 448 xhci_writel(xhci, temp, port_array[port_id]); 449 } 450 451 /* Test and clear port RWC bit */ 452 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array, 453 int port_id, u32 port_bit) 454 { 455 u32 temp; 456 457 temp = xhci_readl(xhci, port_array[port_id]); 458 if (temp & port_bit) { 459 temp = xhci_port_state_to_neutral(temp); 460 temp |= port_bit; 461 xhci_writel(xhci, temp, port_array[port_id]); 462 } 463 } 464 465 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 466 u16 wIndex, char *buf, u16 wLength) 467 { 468 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 469 int max_ports; 470 unsigned long flags; 471 u32 temp, status; 472 int retval = 0; 473 __le32 __iomem **port_array; 474 int slot_id; 475 struct xhci_bus_state *bus_state; 476 u16 link_state = 0; 477 u16 wake_mask = 0; 478 479 max_ports = xhci_get_ports(hcd, &port_array); 480 bus_state = &xhci->bus_state[hcd_index(hcd)]; 481 482 spin_lock_irqsave(&xhci->lock, flags); 483 switch (typeReq) { 484 case GetHubStatus: 485 /* No power source, over-current reported per port */ 486 memset(buf, 0, 4); 487 break; 488 case GetHubDescriptor: 489 /* Check to make sure userspace is asking for the USB 3.0 hub 490 * descriptor for the USB 3.0 roothub. If not, we stall the 491 * endpoint, like external hubs do. 492 */ 493 if (hcd->speed == HCD_USB3 && 494 (wLength < USB_DT_SS_HUB_SIZE || 495 wValue != (USB_DT_SS_HUB << 8))) { 496 xhci_dbg(xhci, "Wrong hub descriptor type for " 497 "USB 3.0 roothub.\n"); 498 goto error; 499 } 500 xhci_hub_descriptor(hcd, xhci, 501 (struct usb_hub_descriptor *) buf); 502 break; 503 case DeviceRequest | USB_REQ_GET_DESCRIPTOR: 504 if ((wValue & 0xff00) != (USB_DT_BOS << 8)) 505 goto error; 506 507 if (hcd->speed != HCD_USB3) 508 goto error; 509 510 memcpy(buf, &usb_bos_descriptor, 511 USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE); 512 temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3); 513 buf[12] = HCS_U1_LATENCY(temp); 514 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]); 515 516 spin_unlock_irqrestore(&xhci->lock, flags); 517 return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE; 518 case GetPortStatus: 519 if (!wIndex || wIndex > max_ports) 520 goto error; 521 wIndex--; 522 status = 0; 523 temp = xhci_readl(xhci, port_array[wIndex]); 524 if (temp == 0xffffffff) { 525 retval = -ENODEV; 526 break; 527 } 528 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", wIndex, temp); 529 530 /* wPortChange bits */ 531 if (temp & PORT_CSC) 532 status |= USB_PORT_STAT_C_CONNECTION << 16; 533 if (temp & PORT_PEC) 534 status |= USB_PORT_STAT_C_ENABLE << 16; 535 if ((temp & PORT_OCC)) 536 status |= USB_PORT_STAT_C_OVERCURRENT << 16; 537 if ((temp & PORT_RC)) 538 status |= USB_PORT_STAT_C_RESET << 16; 539 /* USB3.0 only */ 540 if (hcd->speed == HCD_USB3) { 541 if ((temp & PORT_PLC)) 542 status |= USB_PORT_STAT_C_LINK_STATE << 16; 543 if ((temp & PORT_WRC)) 544 status |= USB_PORT_STAT_C_BH_RESET << 16; 545 } 546 547 if (hcd->speed != HCD_USB3) { 548 if ((temp & PORT_PLS_MASK) == XDEV_U3 549 && (temp & PORT_POWER)) 550 status |= USB_PORT_STAT_SUSPEND; 551 } 552 if ((temp & PORT_PLS_MASK) == XDEV_RESUME && 553 !DEV_SUPERSPEED(temp)) { 554 if ((temp & PORT_RESET) || !(temp & PORT_PE)) 555 goto error; 556 if (time_after_eq(jiffies, 557 bus_state->resume_done[wIndex])) { 558 xhci_dbg(xhci, "Resume USB2 port %d\n", 559 wIndex + 1); 560 bus_state->resume_done[wIndex] = 0; 561 xhci_set_link_state(xhci, port_array, wIndex, 562 XDEV_U0); 563 xhci_dbg(xhci, "set port %d resume\n", 564 wIndex + 1); 565 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 566 wIndex + 1); 567 if (!slot_id) { 568 xhci_dbg(xhci, "slot_id is zero\n"); 569 goto error; 570 } 571 xhci_ring_device(xhci, slot_id); 572 bus_state->port_c_suspend |= 1 << wIndex; 573 bus_state->suspended_ports &= ~(1 << wIndex); 574 } else { 575 /* 576 * The resume has been signaling for less than 577 * 20ms. Report the port status as SUSPEND, 578 * let the usbcore check port status again 579 * and clear resume signaling later. 580 */ 581 status |= USB_PORT_STAT_SUSPEND; 582 } 583 } 584 if ((temp & PORT_PLS_MASK) == XDEV_U0 585 && (temp & PORT_POWER) 586 && (bus_state->suspended_ports & (1 << wIndex))) { 587 bus_state->suspended_ports &= ~(1 << wIndex); 588 if (hcd->speed != HCD_USB3) 589 bus_state->port_c_suspend |= 1 << wIndex; 590 } 591 if (temp & PORT_CONNECT) { 592 status |= USB_PORT_STAT_CONNECTION; 593 status |= xhci_port_speed(temp); 594 } 595 if (temp & PORT_PE) 596 status |= USB_PORT_STAT_ENABLE; 597 if (temp & PORT_OC) 598 status |= USB_PORT_STAT_OVERCURRENT; 599 if (temp & PORT_RESET) 600 status |= USB_PORT_STAT_RESET; 601 if (temp & PORT_POWER) { 602 if (hcd->speed == HCD_USB3) 603 status |= USB_SS_PORT_STAT_POWER; 604 else 605 status |= USB_PORT_STAT_POWER; 606 } 607 /* Port Link State */ 608 if (hcd->speed == HCD_USB3) { 609 /* resume state is a xHCI internal state. 610 * Do not report it to usb core. 611 */ 612 if ((temp & PORT_PLS_MASK) != XDEV_RESUME) 613 status |= (temp & PORT_PLS_MASK); 614 } 615 if (bus_state->port_c_suspend & (1 << wIndex)) 616 status |= 1 << USB_PORT_FEAT_C_SUSPEND; 617 xhci_dbg(xhci, "Get port status returned 0x%x\n", status); 618 put_unaligned(cpu_to_le32(status), (__le32 *) buf); 619 break; 620 case SetPortFeature: 621 if (wValue == USB_PORT_FEAT_LINK_STATE) 622 link_state = (wIndex & 0xff00) >> 3; 623 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK) 624 wake_mask = wIndex & 0xff00; 625 wIndex &= 0xff; 626 if (!wIndex || wIndex > max_ports) 627 goto error; 628 wIndex--; 629 temp = xhci_readl(xhci, port_array[wIndex]); 630 if (temp == 0xffffffff) { 631 retval = -ENODEV; 632 break; 633 } 634 temp = xhci_port_state_to_neutral(temp); 635 /* FIXME: What new port features do we need to support? */ 636 switch (wValue) { 637 case USB_PORT_FEAT_SUSPEND: 638 temp = xhci_readl(xhci, port_array[wIndex]); 639 if ((temp & PORT_PLS_MASK) != XDEV_U0) { 640 /* Resume the port to U0 first */ 641 xhci_set_link_state(xhci, port_array, wIndex, 642 XDEV_U0); 643 spin_unlock_irqrestore(&xhci->lock, flags); 644 msleep(10); 645 spin_lock_irqsave(&xhci->lock, flags); 646 } 647 /* In spec software should not attempt to suspend 648 * a port unless the port reports that it is in the 649 * enabled (PED = ‘1’,PLS < ‘3’) state. 650 */ 651 temp = xhci_readl(xhci, port_array[wIndex]); 652 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) 653 || (temp & PORT_PLS_MASK) >= XDEV_U3) { 654 xhci_warn(xhci, "USB core suspending device " 655 "not in U0/U1/U2.\n"); 656 goto error; 657 } 658 659 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 660 wIndex + 1); 661 if (!slot_id) { 662 xhci_warn(xhci, "slot_id is zero\n"); 663 goto error; 664 } 665 /* unlock to execute stop endpoint commands */ 666 spin_unlock_irqrestore(&xhci->lock, flags); 667 xhci_stop_device(xhci, slot_id, 1); 668 spin_lock_irqsave(&xhci->lock, flags); 669 670 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3); 671 672 spin_unlock_irqrestore(&xhci->lock, flags); 673 msleep(10); /* wait device to enter */ 674 spin_lock_irqsave(&xhci->lock, flags); 675 676 temp = xhci_readl(xhci, port_array[wIndex]); 677 bus_state->suspended_ports |= 1 << wIndex; 678 break; 679 case USB_PORT_FEAT_LINK_STATE: 680 temp = xhci_readl(xhci, port_array[wIndex]); 681 /* Software should not attempt to set 682 * port link state above '5' (Rx.Detect) and the port 683 * must be enabled. 684 */ 685 if ((temp & PORT_PE) == 0 || 686 (link_state > USB_SS_PORT_LS_RX_DETECT)) { 687 xhci_warn(xhci, "Cannot set link state.\n"); 688 goto error; 689 } 690 691 if (link_state == USB_SS_PORT_LS_U3) { 692 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 693 wIndex + 1); 694 if (slot_id) { 695 /* unlock to execute stop endpoint 696 * commands */ 697 spin_unlock_irqrestore(&xhci->lock, 698 flags); 699 xhci_stop_device(xhci, slot_id, 1); 700 spin_lock_irqsave(&xhci->lock, flags); 701 } 702 } 703 704 xhci_set_link_state(xhci, port_array, wIndex, 705 link_state); 706 707 spin_unlock_irqrestore(&xhci->lock, flags); 708 msleep(20); /* wait device to enter */ 709 spin_lock_irqsave(&xhci->lock, flags); 710 711 temp = xhci_readl(xhci, port_array[wIndex]); 712 if (link_state == USB_SS_PORT_LS_U3) 713 bus_state->suspended_ports |= 1 << wIndex; 714 break; 715 case USB_PORT_FEAT_POWER: 716 /* 717 * Turn on ports, even if there isn't per-port switching. 718 * HC will report connect events even before this is set. 719 * However, khubd will ignore the roothub events until 720 * the roothub is registered. 721 */ 722 xhci_writel(xhci, temp | PORT_POWER, 723 port_array[wIndex]); 724 725 temp = xhci_readl(xhci, port_array[wIndex]); 726 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp); 727 break; 728 case USB_PORT_FEAT_RESET: 729 temp = (temp | PORT_RESET); 730 xhci_writel(xhci, temp, port_array[wIndex]); 731 732 temp = xhci_readl(xhci, port_array[wIndex]); 733 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp); 734 break; 735 case USB_PORT_FEAT_REMOTE_WAKE_MASK: 736 xhci_set_remote_wake_mask(xhci, port_array, 737 wIndex, wake_mask); 738 temp = xhci_readl(xhci, port_array[wIndex]); 739 xhci_dbg(xhci, "set port remote wake mask, " 740 "actual port %d status = 0x%x\n", 741 wIndex, temp); 742 break; 743 case USB_PORT_FEAT_BH_PORT_RESET: 744 temp |= PORT_WR; 745 xhci_writel(xhci, temp, port_array[wIndex]); 746 747 temp = xhci_readl(xhci, port_array[wIndex]); 748 break; 749 default: 750 goto error; 751 } 752 /* unblock any posted writes */ 753 temp = xhci_readl(xhci, port_array[wIndex]); 754 break; 755 case ClearPortFeature: 756 if (!wIndex || wIndex > max_ports) 757 goto error; 758 wIndex--; 759 temp = xhci_readl(xhci, port_array[wIndex]); 760 if (temp == 0xffffffff) { 761 retval = -ENODEV; 762 break; 763 } 764 /* FIXME: What new port features do we need to support? */ 765 temp = xhci_port_state_to_neutral(temp); 766 switch (wValue) { 767 case USB_PORT_FEAT_SUSPEND: 768 temp = xhci_readl(xhci, port_array[wIndex]); 769 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n"); 770 xhci_dbg(xhci, "PORTSC %04x\n", temp); 771 if (temp & PORT_RESET) 772 goto error; 773 if ((temp & PORT_PLS_MASK) == XDEV_U3) { 774 if ((temp & PORT_PE) == 0) 775 goto error; 776 777 xhci_set_link_state(xhci, port_array, wIndex, 778 XDEV_RESUME); 779 spin_unlock_irqrestore(&xhci->lock, flags); 780 msleep(20); 781 spin_lock_irqsave(&xhci->lock, flags); 782 xhci_set_link_state(xhci, port_array, wIndex, 783 XDEV_U0); 784 } 785 bus_state->port_c_suspend |= 1 << wIndex; 786 787 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 788 wIndex + 1); 789 if (!slot_id) { 790 xhci_dbg(xhci, "slot_id is zero\n"); 791 goto error; 792 } 793 xhci_ring_device(xhci, slot_id); 794 break; 795 case USB_PORT_FEAT_C_SUSPEND: 796 bus_state->port_c_suspend &= ~(1 << wIndex); 797 case USB_PORT_FEAT_C_RESET: 798 case USB_PORT_FEAT_C_BH_PORT_RESET: 799 case USB_PORT_FEAT_C_CONNECTION: 800 case USB_PORT_FEAT_C_OVER_CURRENT: 801 case USB_PORT_FEAT_C_ENABLE: 802 case USB_PORT_FEAT_C_PORT_LINK_STATE: 803 xhci_clear_port_change_bit(xhci, wValue, wIndex, 804 port_array[wIndex], temp); 805 break; 806 case USB_PORT_FEAT_ENABLE: 807 xhci_disable_port(hcd, xhci, wIndex, 808 port_array[wIndex], temp); 809 break; 810 default: 811 goto error; 812 } 813 break; 814 default: 815 error: 816 /* "stall" on error */ 817 retval = -EPIPE; 818 } 819 spin_unlock_irqrestore(&xhci->lock, flags); 820 return retval; 821 } 822 823 /* 824 * Returns 0 if the status hasn't changed, or the number of bytes in buf. 825 * Ports are 0-indexed from the HCD point of view, 826 * and 1-indexed from the USB core pointer of view. 827 * 828 * Note that the status change bits will be cleared as soon as a port status 829 * change event is generated, so we use the saved status from that event. 830 */ 831 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf) 832 { 833 unsigned long flags; 834 u32 temp, status; 835 u32 mask; 836 int i, retval; 837 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 838 int max_ports; 839 __le32 __iomem **port_array; 840 struct xhci_bus_state *bus_state; 841 842 max_ports = xhci_get_ports(hcd, &port_array); 843 bus_state = &xhci->bus_state[hcd_index(hcd)]; 844 845 /* Initial status is no changes */ 846 retval = (max_ports + 8) / 8; 847 memset(buf, 0, retval); 848 status = 0; 849 850 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC; 851 852 spin_lock_irqsave(&xhci->lock, flags); 853 /* For each port, did anything change? If so, set that bit in buf. */ 854 for (i = 0; i < max_ports; i++) { 855 temp = xhci_readl(xhci, port_array[i]); 856 if (temp == 0xffffffff) { 857 retval = -ENODEV; 858 break; 859 } 860 if ((temp & mask) != 0 || 861 (bus_state->port_c_suspend & 1 << i) || 862 (bus_state->resume_done[i] && time_after_eq( 863 jiffies, bus_state->resume_done[i]))) { 864 buf[(i + 1) / 8] |= 1 << (i + 1) % 8; 865 status = 1; 866 } 867 } 868 spin_unlock_irqrestore(&xhci->lock, flags); 869 return status ? retval : 0; 870 } 871 872 #ifdef CONFIG_PM 873 874 int xhci_bus_suspend(struct usb_hcd *hcd) 875 { 876 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 877 int max_ports, port_index; 878 __le32 __iomem **port_array; 879 struct xhci_bus_state *bus_state; 880 unsigned long flags; 881 882 max_ports = xhci_get_ports(hcd, &port_array); 883 bus_state = &xhci->bus_state[hcd_index(hcd)]; 884 885 spin_lock_irqsave(&xhci->lock, flags); 886 887 if (hcd->self.root_hub->do_remote_wakeup) { 888 port_index = max_ports; 889 while (port_index--) { 890 if (bus_state->resume_done[port_index] != 0) { 891 spin_unlock_irqrestore(&xhci->lock, flags); 892 xhci_dbg(xhci, "suspend failed because " 893 "port %d is resuming\n", 894 port_index + 1); 895 return -EBUSY; 896 } 897 } 898 } 899 900 port_index = max_ports; 901 bus_state->bus_suspended = 0; 902 while (port_index--) { 903 /* suspend the port if the port is not suspended */ 904 u32 t1, t2; 905 int slot_id; 906 907 t1 = xhci_readl(xhci, port_array[port_index]); 908 t2 = xhci_port_state_to_neutral(t1); 909 910 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) { 911 xhci_dbg(xhci, "port %d not suspended\n", port_index); 912 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 913 port_index + 1); 914 if (slot_id) { 915 spin_unlock_irqrestore(&xhci->lock, flags); 916 xhci_stop_device(xhci, slot_id, 1); 917 spin_lock_irqsave(&xhci->lock, flags); 918 } 919 t2 &= ~PORT_PLS_MASK; 920 t2 |= PORT_LINK_STROBE | XDEV_U3; 921 set_bit(port_index, &bus_state->bus_suspended); 922 } 923 /* USB core sets remote wake mask for USB 3.0 hubs, 924 * including the USB 3.0 roothub, but only if CONFIG_USB_SUSPEND 925 * is enabled, so also enable remote wake here. 926 */ 927 if (hcd->self.root_hub->do_remote_wakeup) { 928 if (t1 & PORT_CONNECT) { 929 t2 |= PORT_WKOC_E | PORT_WKDISC_E; 930 t2 &= ~PORT_WKCONN_E; 931 } else { 932 t2 |= PORT_WKOC_E | PORT_WKCONN_E; 933 t2 &= ~PORT_WKDISC_E; 934 } 935 } else 936 t2 &= ~PORT_WAKE_BITS; 937 938 t1 = xhci_port_state_to_neutral(t1); 939 if (t1 != t2) 940 xhci_writel(xhci, t2, port_array[port_index]); 941 942 if (hcd->speed != HCD_USB3) { 943 /* enable remote wake up for USB 2.0 */ 944 __le32 __iomem *addr; 945 u32 tmp; 946 947 /* Add one to the port status register address to get 948 * the port power control register address. 949 */ 950 addr = port_array[port_index] + 1; 951 tmp = xhci_readl(xhci, addr); 952 tmp |= PORT_RWE; 953 xhci_writel(xhci, tmp, addr); 954 } 955 } 956 hcd->state = HC_STATE_SUSPENDED; 957 bus_state->next_statechange = jiffies + msecs_to_jiffies(10); 958 spin_unlock_irqrestore(&xhci->lock, flags); 959 return 0; 960 } 961 962 int xhci_bus_resume(struct usb_hcd *hcd) 963 { 964 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 965 int max_ports, port_index; 966 __le32 __iomem **port_array; 967 struct xhci_bus_state *bus_state; 968 u32 temp; 969 unsigned long flags; 970 971 max_ports = xhci_get_ports(hcd, &port_array); 972 bus_state = &xhci->bus_state[hcd_index(hcd)]; 973 974 if (time_before(jiffies, bus_state->next_statechange)) 975 msleep(5); 976 977 spin_lock_irqsave(&xhci->lock, flags); 978 if (!HCD_HW_ACCESSIBLE(hcd)) { 979 spin_unlock_irqrestore(&xhci->lock, flags); 980 return -ESHUTDOWN; 981 } 982 983 /* delay the irqs */ 984 temp = xhci_readl(xhci, &xhci->op_regs->command); 985 temp &= ~CMD_EIE; 986 xhci_writel(xhci, temp, &xhci->op_regs->command); 987 988 port_index = max_ports; 989 while (port_index--) { 990 /* Check whether need resume ports. If needed 991 resume port and disable remote wakeup */ 992 u32 temp; 993 int slot_id; 994 995 temp = xhci_readl(xhci, port_array[port_index]); 996 if (DEV_SUPERSPEED(temp)) 997 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); 998 else 999 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); 1000 if (test_bit(port_index, &bus_state->bus_suspended) && 1001 (temp & PORT_PLS_MASK)) { 1002 if (DEV_SUPERSPEED(temp)) { 1003 xhci_set_link_state(xhci, port_array, 1004 port_index, XDEV_U0); 1005 } else { 1006 xhci_set_link_state(xhci, port_array, 1007 port_index, XDEV_RESUME); 1008 1009 spin_unlock_irqrestore(&xhci->lock, flags); 1010 msleep(20); 1011 spin_lock_irqsave(&xhci->lock, flags); 1012 1013 xhci_set_link_state(xhci, port_array, 1014 port_index, XDEV_U0); 1015 } 1016 /* wait for the port to enter U0 and report port link 1017 * state change. 1018 */ 1019 spin_unlock_irqrestore(&xhci->lock, flags); 1020 msleep(20); 1021 spin_lock_irqsave(&xhci->lock, flags); 1022 1023 /* Clear PLC */ 1024 xhci_test_and_clear_bit(xhci, port_array, port_index, 1025 PORT_PLC); 1026 1027 slot_id = xhci_find_slot_id_by_port(hcd, 1028 xhci, port_index + 1); 1029 if (slot_id) 1030 xhci_ring_device(xhci, slot_id); 1031 } else 1032 xhci_writel(xhci, temp, port_array[port_index]); 1033 1034 if (hcd->speed != HCD_USB3) { 1035 /* disable remote wake up for USB 2.0 */ 1036 __le32 __iomem *addr; 1037 u32 tmp; 1038 1039 /* Add one to the port status register address to get 1040 * the port power control register address. 1041 */ 1042 addr = port_array[port_index] + 1; 1043 tmp = xhci_readl(xhci, addr); 1044 tmp &= ~PORT_RWE; 1045 xhci_writel(xhci, tmp, addr); 1046 } 1047 } 1048 1049 (void) xhci_readl(xhci, &xhci->op_regs->command); 1050 1051 bus_state->next_statechange = jiffies + msecs_to_jiffies(5); 1052 /* re-enable irqs */ 1053 temp = xhci_readl(xhci, &xhci->op_regs->command); 1054 temp |= CMD_EIE; 1055 xhci_writel(xhci, temp, &xhci->op_regs->command); 1056 temp = xhci_readl(xhci, &xhci->op_regs->command); 1057 1058 spin_unlock_irqrestore(&xhci->lock, flags); 1059 return 0; 1060 } 1061 1062 #endif /* CONFIG_PM */ 1063