1 /* 2 * xHCI host controller driver 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 24 #include <linux/slab.h> 25 #include <linux/device.h> 26 #include <asm/unaligned.h> 27 28 #include "xhci.h" 29 #include "xhci-trace.h" 30 31 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) 32 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ 33 PORT_RC | PORT_PLC | PORT_PE) 34 35 /* USB 3.0 BOS descriptor and a capability descriptor, combined */ 36 static u8 usb_bos_descriptor [] = { 37 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */ 38 USB_DT_BOS, /* __u8 bDescriptorType */ 39 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */ 40 0x1, /* __u8 bNumDeviceCaps */ 41 /* First device capability */ 42 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */ 43 USB_DT_DEVICE_CAPABILITY, /* Device Capability */ 44 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */ 45 0x00, /* bmAttributes, LTM off by default */ 46 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */ 47 0x03, /* bFunctionalitySupport, 48 USB 3.0 speed only */ 49 0x00, /* bU1DevExitLat, set later. */ 50 0x00, 0x00 /* __le16 bU2DevExitLat, set later. */ 51 }; 52 53 54 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci, 55 struct usb_hub_descriptor *desc, int ports) 56 { 57 u16 temp; 58 59 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */ 60 desc->bHubContrCurrent = 0; 61 62 desc->bNbrPorts = ports; 63 temp = 0; 64 /* Bits 1:0 - support per-port power switching, or power always on */ 65 if (HCC_PPC(xhci->hcc_params)) 66 temp |= HUB_CHAR_INDV_PORT_LPSM; 67 else 68 temp |= HUB_CHAR_NO_LPSM; 69 /* Bit 2 - root hubs are not part of a compound device */ 70 /* Bits 4:3 - individual port over current protection */ 71 temp |= HUB_CHAR_INDV_PORT_OCPM; 72 /* Bits 6:5 - no TTs in root ports */ 73 /* Bit 7 - no port indicators */ 74 desc->wHubCharacteristics = cpu_to_le16(temp); 75 } 76 77 /* Fill in the USB 2.0 roothub descriptor */ 78 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 79 struct usb_hub_descriptor *desc) 80 { 81 int ports; 82 u16 temp; 83 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8]; 84 u32 portsc; 85 unsigned int i; 86 87 ports = xhci->num_usb2_ports; 88 89 xhci_common_hub_descriptor(xhci, desc, ports); 90 desc->bDescriptorType = USB_DT_HUB; 91 temp = 1 + (ports / 8); 92 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; 93 94 /* The Device Removable bits are reported on a byte granularity. 95 * If the port doesn't exist within that byte, the bit is set to 0. 96 */ 97 memset(port_removable, 0, sizeof(port_removable)); 98 for (i = 0; i < ports; i++) { 99 portsc = readl(xhci->usb2_ports[i]); 100 /* If a device is removable, PORTSC reports a 0, same as in the 101 * hub descriptor DeviceRemovable bits. 102 */ 103 if (portsc & PORT_DEV_REMOVE) 104 /* This math is hairy because bit 0 of DeviceRemovable 105 * is reserved, and bit 1 is for port 1, etc. 106 */ 107 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8); 108 } 109 110 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN 111 * ports on it. The USB 2.0 specification says that there are two 112 * variable length fields at the end of the hub descriptor: 113 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than 114 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array 115 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to 116 * 0xFF, so we initialize the both arrays (DeviceRemovable and 117 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each 118 * set of ports that actually exist. 119 */ 120 memset(desc->u.hs.DeviceRemovable, 0xff, 121 sizeof(desc->u.hs.DeviceRemovable)); 122 memset(desc->u.hs.PortPwrCtrlMask, 0xff, 123 sizeof(desc->u.hs.PortPwrCtrlMask)); 124 125 for (i = 0; i < (ports + 1 + 7) / 8; i++) 126 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i], 127 sizeof(__u8)); 128 } 129 130 /* Fill in the USB 3.0 roothub descriptor */ 131 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 132 struct usb_hub_descriptor *desc) 133 { 134 int ports; 135 u16 port_removable; 136 u32 portsc; 137 unsigned int i; 138 139 ports = xhci->num_usb3_ports; 140 xhci_common_hub_descriptor(xhci, desc, ports); 141 desc->bDescriptorType = USB_DT_SS_HUB; 142 desc->bDescLength = USB_DT_SS_HUB_SIZE; 143 144 /* header decode latency should be zero for roothubs, 145 * see section 4.23.5.2. 146 */ 147 desc->u.ss.bHubHdrDecLat = 0; 148 desc->u.ss.wHubDelay = 0; 149 150 port_removable = 0; 151 /* bit 0 is reserved, bit 1 is for port 1, etc. */ 152 for (i = 0; i < ports; i++) { 153 portsc = readl(xhci->usb3_ports[i]); 154 if (portsc & PORT_DEV_REMOVE) 155 port_removable |= 1 << (i + 1); 156 } 157 158 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable); 159 } 160 161 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 162 struct usb_hub_descriptor *desc) 163 { 164 165 if (hcd->speed == HCD_USB3) 166 xhci_usb3_hub_descriptor(hcd, xhci, desc); 167 else 168 xhci_usb2_hub_descriptor(hcd, xhci, desc); 169 170 } 171 172 static unsigned int xhci_port_speed(unsigned int port_status) 173 { 174 if (DEV_LOWSPEED(port_status)) 175 return USB_PORT_STAT_LOW_SPEED; 176 if (DEV_HIGHSPEED(port_status)) 177 return USB_PORT_STAT_HIGH_SPEED; 178 /* 179 * FIXME: Yes, we should check for full speed, but the core uses that as 180 * a default in portspeed() in usb/core/hub.c (which is the only place 181 * USB_PORT_STAT_*_SPEED is used). 182 */ 183 return 0; 184 } 185 186 /* 187 * These bits are Read Only (RO) and should be saved and written to the 188 * registers: 0, 3, 10:13, 30 189 * connect status, over-current status, port speed, and device removable. 190 * connect status and port speed are also sticky - meaning they're in 191 * the AUX well and they aren't changed by a hot, warm, or cold reset. 192 */ 193 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30)) 194 /* 195 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: 196 * bits 5:8, 9, 14:15, 25:27 197 * link state, port power, port indicator state, "wake on" enable state 198 */ 199 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25)) 200 /* 201 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: 202 * bit 4 (port reset) 203 */ 204 #define XHCI_PORT_RW1S ((1<<4)) 205 /* 206 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: 207 * bits 1, 17, 18, 19, 20, 21, 22, 23 208 * port enable/disable, and 209 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports), 210 * over-current, reset, link state, and L1 change 211 */ 212 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17)) 213 /* 214 * Bit 16 is RW, and writing a '1' to it causes the link state control to be 215 * latched in 216 */ 217 #define XHCI_PORT_RW ((1<<16)) 218 /* 219 * These bits are Reserved Zero (RsvdZ) and zero should be written to them: 220 * bits 2, 24, 28:31 221 */ 222 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28)) 223 224 /* 225 * Given a port state, this function returns a value that would result in the 226 * port being in the same state, if the value was written to the port status 227 * control register. 228 * Save Read Only (RO) bits and save read/write bits where 229 * writing a 0 clears the bit and writing a 1 sets the bit (RWS). 230 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. 231 */ 232 u32 xhci_port_state_to_neutral(u32 state) 233 { 234 /* Save read-only status and port state */ 235 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS); 236 } 237 238 /* 239 * find slot id based on port number. 240 * @port: The one-based port number from one of the two split roothubs. 241 */ 242 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 243 u16 port) 244 { 245 int slot_id; 246 int i; 247 enum usb_device_speed speed; 248 249 slot_id = 0; 250 for (i = 0; i < MAX_HC_SLOTS; i++) { 251 if (!xhci->devs[i]) 252 continue; 253 speed = xhci->devs[i]->udev->speed; 254 if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3)) 255 && xhci->devs[i]->fake_port == port) { 256 slot_id = i; 257 break; 258 } 259 } 260 261 return slot_id; 262 } 263 264 /* 265 * Stop device 266 * It issues stop endpoint command for EP 0 to 30. And wait the last command 267 * to complete. 268 * suspend will set to 1, if suspend bit need to set in command. 269 */ 270 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend) 271 { 272 struct xhci_virt_device *virt_dev; 273 struct xhci_command *cmd; 274 unsigned long flags; 275 int ret; 276 int i; 277 278 ret = 0; 279 virt_dev = xhci->devs[slot_id]; 280 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO); 281 if (!cmd) { 282 xhci_dbg(xhci, "Couldn't allocate command structure.\n"); 283 return -ENOMEM; 284 } 285 286 spin_lock_irqsave(&xhci->lock, flags); 287 for (i = LAST_EP_INDEX; i > 0; i--) { 288 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) { 289 struct xhci_command *command; 290 command = xhci_alloc_command(xhci, false, false, 291 GFP_NOWAIT); 292 if (!command) { 293 spin_unlock_irqrestore(&xhci->lock, flags); 294 xhci_free_command(xhci, cmd); 295 return -ENOMEM; 296 297 } 298 xhci_queue_stop_endpoint(xhci, command, slot_id, i, 299 suspend); 300 } 301 } 302 xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend); 303 xhci_ring_cmd_db(xhci); 304 spin_unlock_irqrestore(&xhci->lock, flags); 305 306 /* Wait for last stop endpoint command to finish */ 307 wait_for_completion(cmd->completion); 308 309 if (cmd->status == COMP_CMD_ABORT || cmd->status == COMP_CMD_STOP) { 310 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n"); 311 ret = -ETIME; 312 } 313 xhci_free_command(xhci, cmd); 314 return ret; 315 } 316 317 /* 318 * Ring device, it rings the all doorbells unconditionally. 319 */ 320 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id) 321 { 322 int i; 323 324 for (i = 0; i < LAST_EP_INDEX + 1; i++) 325 if (xhci->devs[slot_id]->eps[i].ring && 326 xhci->devs[slot_id]->eps[i].ring->dequeue) 327 xhci_ring_ep_doorbell(xhci, slot_id, i, 0); 328 329 return; 330 } 331 332 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 333 u16 wIndex, __le32 __iomem *addr, u32 port_status) 334 { 335 /* Don't allow the USB core to disable SuperSpeed ports. */ 336 if (hcd->speed == HCD_USB3) { 337 xhci_dbg(xhci, "Ignoring request to disable " 338 "SuperSpeed port.\n"); 339 return; 340 } 341 342 /* Write 1 to disable the port */ 343 writel(port_status | PORT_PE, addr); 344 port_status = readl(addr); 345 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n", 346 wIndex, port_status); 347 } 348 349 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, 350 u16 wIndex, __le32 __iomem *addr, u32 port_status) 351 { 352 char *port_change_bit; 353 u32 status; 354 355 switch (wValue) { 356 case USB_PORT_FEAT_C_RESET: 357 status = PORT_RC; 358 port_change_bit = "reset"; 359 break; 360 case USB_PORT_FEAT_C_BH_PORT_RESET: 361 status = PORT_WRC; 362 port_change_bit = "warm(BH) reset"; 363 break; 364 case USB_PORT_FEAT_C_CONNECTION: 365 status = PORT_CSC; 366 port_change_bit = "connect"; 367 break; 368 case USB_PORT_FEAT_C_OVER_CURRENT: 369 status = PORT_OCC; 370 port_change_bit = "over-current"; 371 break; 372 case USB_PORT_FEAT_C_ENABLE: 373 status = PORT_PEC; 374 port_change_bit = "enable/disable"; 375 break; 376 case USB_PORT_FEAT_C_SUSPEND: 377 status = PORT_PLC; 378 port_change_bit = "suspend/resume"; 379 break; 380 case USB_PORT_FEAT_C_PORT_LINK_STATE: 381 status = PORT_PLC; 382 port_change_bit = "link state"; 383 break; 384 default: 385 /* Should never happen */ 386 return; 387 } 388 /* Change bits are all write 1 to clear */ 389 writel(port_status | status, addr); 390 port_status = readl(addr); 391 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n", 392 port_change_bit, wIndex, port_status); 393 } 394 395 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array) 396 { 397 int max_ports; 398 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 399 400 if (hcd->speed == HCD_USB3) { 401 max_ports = xhci->num_usb3_ports; 402 *port_array = xhci->usb3_ports; 403 } else { 404 max_ports = xhci->num_usb2_ports; 405 *port_array = xhci->usb2_ports; 406 } 407 408 return max_ports; 409 } 410 411 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, 412 int port_id, u32 link_state) 413 { 414 u32 temp; 415 416 temp = readl(port_array[port_id]); 417 temp = xhci_port_state_to_neutral(temp); 418 temp &= ~PORT_PLS_MASK; 419 temp |= PORT_LINK_STROBE | link_state; 420 writel(temp, port_array[port_id]); 421 } 422 423 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci, 424 __le32 __iomem **port_array, int port_id, u16 wake_mask) 425 { 426 u32 temp; 427 428 temp = readl(port_array[port_id]); 429 temp = xhci_port_state_to_neutral(temp); 430 431 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT) 432 temp |= PORT_WKCONN_E; 433 else 434 temp &= ~PORT_WKCONN_E; 435 436 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT) 437 temp |= PORT_WKDISC_E; 438 else 439 temp &= ~PORT_WKDISC_E; 440 441 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT) 442 temp |= PORT_WKOC_E; 443 else 444 temp &= ~PORT_WKOC_E; 445 446 writel(temp, port_array[port_id]); 447 } 448 449 /* Test and clear port RWC bit */ 450 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array, 451 int port_id, u32 port_bit) 452 { 453 u32 temp; 454 455 temp = readl(port_array[port_id]); 456 if (temp & port_bit) { 457 temp = xhci_port_state_to_neutral(temp); 458 temp |= port_bit; 459 writel(temp, port_array[port_id]); 460 } 461 } 462 463 /* Updates Link Status for USB 2.1 port */ 464 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg) 465 { 466 if ((status_reg & PORT_PLS_MASK) == XDEV_U2) 467 *status |= USB_PORT_STAT_L1; 468 } 469 470 /* Updates Link Status for super Speed port */ 471 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci, 472 u32 *status, u32 status_reg) 473 { 474 u32 pls = status_reg & PORT_PLS_MASK; 475 476 /* resume state is a xHCI internal state. 477 * Do not report it to usb core. 478 */ 479 if (pls == XDEV_RESUME) 480 return; 481 482 /* When the CAS bit is set then warm reset 483 * should be performed on port 484 */ 485 if (status_reg & PORT_CAS) { 486 /* The CAS bit can be set while the port is 487 * in any link state. 488 * Only roothubs have CAS bit, so we 489 * pretend to be in compliance mode 490 * unless we're already in compliance 491 * or the inactive state. 492 */ 493 if (pls != USB_SS_PORT_LS_COMP_MOD && 494 pls != USB_SS_PORT_LS_SS_INACTIVE) { 495 pls = USB_SS_PORT_LS_COMP_MOD; 496 } 497 /* Return also connection bit - 498 * hub state machine resets port 499 * when this bit is set. 500 */ 501 pls |= USB_PORT_STAT_CONNECTION; 502 } else { 503 /* 504 * If CAS bit isn't set but the Port is already at 505 * Compliance Mode, fake a connection so the USB core 506 * notices the Compliance state and resets the port. 507 * This resolves an issue generated by the SN65LVPE502CP 508 * in which sometimes the port enters compliance mode 509 * caused by a delay on the host-device negotiation. 510 */ 511 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && 512 (pls == USB_SS_PORT_LS_COMP_MOD)) 513 pls |= USB_PORT_STAT_CONNECTION; 514 } 515 516 /* update status field */ 517 *status |= pls; 518 } 519 520 /* 521 * Function for Compliance Mode Quirk. 522 * 523 * This Function verifies if all xhc USB3 ports have entered U0, if so, 524 * the compliance mode timer is deleted. A port won't enter 525 * compliance mode if it has previously entered U0. 526 */ 527 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, 528 u16 wIndex) 529 { 530 u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1); 531 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0); 532 533 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK)) 534 return; 535 536 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) { 537 xhci->port_status_u0 |= 1 << wIndex; 538 if (xhci->port_status_u0 == all_ports_seen_u0) { 539 del_timer_sync(&xhci->comp_mode_recovery_timer); 540 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 541 "All USB3 ports have entered U0 already!"); 542 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 543 "Compliance Mode Recovery Timer Deleted."); 544 } 545 } 546 } 547 548 /* 549 * Converts a raw xHCI port status into the format that external USB 2.0 or USB 550 * 3.0 hubs use. 551 * 552 * Possible side effects: 553 * - Mark a port as being done with device resume, 554 * and ring the endpoint doorbells. 555 * - Stop the Synopsys redriver Compliance Mode polling. 556 * - Drop and reacquire the xHCI lock, in order to wait for port resume. 557 */ 558 static u32 xhci_get_port_status(struct usb_hcd *hcd, 559 struct xhci_bus_state *bus_state, 560 __le32 __iomem **port_array, 561 u16 wIndex, u32 raw_port_status, 562 unsigned long flags) 563 __releases(&xhci->lock) 564 __acquires(&xhci->lock) 565 { 566 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 567 u32 status = 0; 568 int slot_id; 569 570 /* wPortChange bits */ 571 if (raw_port_status & PORT_CSC) 572 status |= USB_PORT_STAT_C_CONNECTION << 16; 573 if (raw_port_status & PORT_PEC) 574 status |= USB_PORT_STAT_C_ENABLE << 16; 575 if ((raw_port_status & PORT_OCC)) 576 status |= USB_PORT_STAT_C_OVERCURRENT << 16; 577 if ((raw_port_status & PORT_RC)) 578 status |= USB_PORT_STAT_C_RESET << 16; 579 /* USB3.0 only */ 580 if (hcd->speed == HCD_USB3) { 581 if ((raw_port_status & PORT_PLC)) 582 status |= USB_PORT_STAT_C_LINK_STATE << 16; 583 if ((raw_port_status & PORT_WRC)) 584 status |= USB_PORT_STAT_C_BH_RESET << 16; 585 } 586 587 if (hcd->speed != HCD_USB3) { 588 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3 589 && (raw_port_status & PORT_POWER)) 590 status |= USB_PORT_STAT_SUSPEND; 591 } 592 if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME && 593 !DEV_SUPERSPEED(raw_port_status)) { 594 if ((raw_port_status & PORT_RESET) || 595 !(raw_port_status & PORT_PE)) 596 return 0xffffffff; 597 if (time_after_eq(jiffies, 598 bus_state->resume_done[wIndex])) { 599 int time_left; 600 601 xhci_dbg(xhci, "Resume USB2 port %d\n", 602 wIndex + 1); 603 bus_state->resume_done[wIndex] = 0; 604 clear_bit(wIndex, &bus_state->resuming_ports); 605 606 set_bit(wIndex, &bus_state->rexit_ports); 607 xhci_set_link_state(xhci, port_array, wIndex, 608 XDEV_U0); 609 610 spin_unlock_irqrestore(&xhci->lock, flags); 611 time_left = wait_for_completion_timeout( 612 &bus_state->rexit_done[wIndex], 613 msecs_to_jiffies( 614 XHCI_MAX_REXIT_TIMEOUT)); 615 spin_lock_irqsave(&xhci->lock, flags); 616 617 if (time_left) { 618 slot_id = xhci_find_slot_id_by_port(hcd, 619 xhci, wIndex + 1); 620 if (!slot_id) { 621 xhci_dbg(xhci, "slot_id is zero\n"); 622 return 0xffffffff; 623 } 624 xhci_ring_device(xhci, slot_id); 625 } else { 626 int port_status = readl(port_array[wIndex]); 627 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n", 628 XHCI_MAX_REXIT_TIMEOUT, 629 port_status); 630 status |= USB_PORT_STAT_SUSPEND; 631 clear_bit(wIndex, &bus_state->rexit_ports); 632 } 633 634 bus_state->port_c_suspend |= 1 << wIndex; 635 bus_state->suspended_ports &= ~(1 << wIndex); 636 } else { 637 /* 638 * The resume has been signaling for less than 639 * 20ms. Report the port status as SUSPEND, 640 * let the usbcore check port status again 641 * and clear resume signaling later. 642 */ 643 status |= USB_PORT_STAT_SUSPEND; 644 } 645 } 646 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 647 && (raw_port_status & PORT_POWER) 648 && (bus_state->suspended_ports & (1 << wIndex))) { 649 bus_state->suspended_ports &= ~(1 << wIndex); 650 if (hcd->speed != HCD_USB3) 651 bus_state->port_c_suspend |= 1 << wIndex; 652 } 653 if (raw_port_status & PORT_CONNECT) { 654 status |= USB_PORT_STAT_CONNECTION; 655 status |= xhci_port_speed(raw_port_status); 656 } 657 if (raw_port_status & PORT_PE) 658 status |= USB_PORT_STAT_ENABLE; 659 if (raw_port_status & PORT_OC) 660 status |= USB_PORT_STAT_OVERCURRENT; 661 if (raw_port_status & PORT_RESET) 662 status |= USB_PORT_STAT_RESET; 663 if (raw_port_status & PORT_POWER) { 664 if (hcd->speed == HCD_USB3) 665 status |= USB_SS_PORT_STAT_POWER; 666 else 667 status |= USB_PORT_STAT_POWER; 668 } 669 /* Update Port Link State */ 670 if (hcd->speed == HCD_USB3) { 671 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status); 672 /* 673 * Verify if all USB3 Ports Have entered U0 already. 674 * Delete Compliance Mode Timer if so. 675 */ 676 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex); 677 } else { 678 xhci_hub_report_usb2_link_state(&status, raw_port_status); 679 } 680 if (bus_state->port_c_suspend & (1 << wIndex)) 681 status |= 1 << USB_PORT_FEAT_C_SUSPEND; 682 683 return status; 684 } 685 686 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 687 u16 wIndex, char *buf, u16 wLength) 688 { 689 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 690 int max_ports; 691 unsigned long flags; 692 u32 temp, status; 693 int retval = 0; 694 __le32 __iomem **port_array; 695 int slot_id; 696 struct xhci_bus_state *bus_state; 697 u16 link_state = 0; 698 u16 wake_mask = 0; 699 u16 timeout = 0; 700 701 max_ports = xhci_get_ports(hcd, &port_array); 702 bus_state = &xhci->bus_state[hcd_index(hcd)]; 703 704 spin_lock_irqsave(&xhci->lock, flags); 705 switch (typeReq) { 706 case GetHubStatus: 707 /* No power source, over-current reported per port */ 708 memset(buf, 0, 4); 709 break; 710 case GetHubDescriptor: 711 /* Check to make sure userspace is asking for the USB 3.0 hub 712 * descriptor for the USB 3.0 roothub. If not, we stall the 713 * endpoint, like external hubs do. 714 */ 715 if (hcd->speed == HCD_USB3 && 716 (wLength < USB_DT_SS_HUB_SIZE || 717 wValue != (USB_DT_SS_HUB << 8))) { 718 xhci_dbg(xhci, "Wrong hub descriptor type for " 719 "USB 3.0 roothub.\n"); 720 goto error; 721 } 722 xhci_hub_descriptor(hcd, xhci, 723 (struct usb_hub_descriptor *) buf); 724 break; 725 case DeviceRequest | USB_REQ_GET_DESCRIPTOR: 726 if ((wValue & 0xff00) != (USB_DT_BOS << 8)) 727 goto error; 728 729 if (hcd->speed != HCD_USB3) 730 goto error; 731 732 /* Set the U1 and U2 exit latencies. */ 733 memcpy(buf, &usb_bos_descriptor, 734 USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE); 735 if ((xhci->quirks & XHCI_LPM_SUPPORT)) { 736 temp = readl(&xhci->cap_regs->hcs_params3); 737 buf[12] = HCS_U1_LATENCY(temp); 738 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]); 739 } 740 741 /* Indicate whether the host has LTM support. */ 742 temp = readl(&xhci->cap_regs->hcc_params); 743 if (HCC_LTC(temp)) 744 buf[8] |= USB_LTM_SUPPORT; 745 746 spin_unlock_irqrestore(&xhci->lock, flags); 747 return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE; 748 case GetPortStatus: 749 if (!wIndex || wIndex > max_ports) 750 goto error; 751 wIndex--; 752 temp = readl(port_array[wIndex]); 753 if (temp == 0xffffffff) { 754 retval = -ENODEV; 755 break; 756 } 757 status = xhci_get_port_status(hcd, bus_state, port_array, 758 wIndex, temp, flags); 759 if (status == 0xffffffff) 760 goto error; 761 762 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", 763 wIndex, temp); 764 xhci_dbg(xhci, "Get port status returned 0x%x\n", status); 765 766 put_unaligned(cpu_to_le32(status), (__le32 *) buf); 767 break; 768 case SetPortFeature: 769 if (wValue == USB_PORT_FEAT_LINK_STATE) 770 link_state = (wIndex & 0xff00) >> 3; 771 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK) 772 wake_mask = wIndex & 0xff00; 773 /* The MSB of wIndex is the U1/U2 timeout */ 774 timeout = (wIndex & 0xff00) >> 8; 775 wIndex &= 0xff; 776 if (!wIndex || wIndex > max_ports) 777 goto error; 778 wIndex--; 779 temp = readl(port_array[wIndex]); 780 if (temp == 0xffffffff) { 781 retval = -ENODEV; 782 break; 783 } 784 temp = xhci_port_state_to_neutral(temp); 785 /* FIXME: What new port features do we need to support? */ 786 switch (wValue) { 787 case USB_PORT_FEAT_SUSPEND: 788 temp = readl(port_array[wIndex]); 789 if ((temp & PORT_PLS_MASK) != XDEV_U0) { 790 /* Resume the port to U0 first */ 791 xhci_set_link_state(xhci, port_array, wIndex, 792 XDEV_U0); 793 spin_unlock_irqrestore(&xhci->lock, flags); 794 msleep(10); 795 spin_lock_irqsave(&xhci->lock, flags); 796 } 797 /* In spec software should not attempt to suspend 798 * a port unless the port reports that it is in the 799 * enabled (PED = ‘1’,PLS < ‘3’) state. 800 */ 801 temp = readl(port_array[wIndex]); 802 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) 803 || (temp & PORT_PLS_MASK) >= XDEV_U3) { 804 xhci_warn(xhci, "USB core suspending device " 805 "not in U0/U1/U2.\n"); 806 goto error; 807 } 808 809 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 810 wIndex + 1); 811 if (!slot_id) { 812 xhci_warn(xhci, "slot_id is zero\n"); 813 goto error; 814 } 815 /* unlock to execute stop endpoint commands */ 816 spin_unlock_irqrestore(&xhci->lock, flags); 817 xhci_stop_device(xhci, slot_id, 1); 818 spin_lock_irqsave(&xhci->lock, flags); 819 820 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3); 821 822 spin_unlock_irqrestore(&xhci->lock, flags); 823 msleep(10); /* wait device to enter */ 824 spin_lock_irqsave(&xhci->lock, flags); 825 826 temp = readl(port_array[wIndex]); 827 bus_state->suspended_ports |= 1 << wIndex; 828 break; 829 case USB_PORT_FEAT_LINK_STATE: 830 temp = readl(port_array[wIndex]); 831 832 /* Disable port */ 833 if (link_state == USB_SS_PORT_LS_SS_DISABLED) { 834 xhci_dbg(xhci, "Disable port %d\n", wIndex); 835 temp = xhci_port_state_to_neutral(temp); 836 /* 837 * Clear all change bits, so that we get a new 838 * connection event. 839 */ 840 temp |= PORT_CSC | PORT_PEC | PORT_WRC | 841 PORT_OCC | PORT_RC | PORT_PLC | 842 PORT_CEC; 843 writel(temp | PORT_PE, port_array[wIndex]); 844 temp = readl(port_array[wIndex]); 845 break; 846 } 847 848 /* Put link in RxDetect (enable port) */ 849 if (link_state == USB_SS_PORT_LS_RX_DETECT) { 850 xhci_dbg(xhci, "Enable port %d\n", wIndex); 851 xhci_set_link_state(xhci, port_array, wIndex, 852 link_state); 853 temp = readl(port_array[wIndex]); 854 break; 855 } 856 857 /* Software should not attempt to set 858 * port link state above '3' (U3) and the port 859 * must be enabled. 860 */ 861 if ((temp & PORT_PE) == 0 || 862 (link_state > USB_SS_PORT_LS_U3)) { 863 xhci_warn(xhci, "Cannot set link state.\n"); 864 goto error; 865 } 866 867 if (link_state == USB_SS_PORT_LS_U3) { 868 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 869 wIndex + 1); 870 if (slot_id) { 871 /* unlock to execute stop endpoint 872 * commands */ 873 spin_unlock_irqrestore(&xhci->lock, 874 flags); 875 xhci_stop_device(xhci, slot_id, 1); 876 spin_lock_irqsave(&xhci->lock, flags); 877 } 878 } 879 880 xhci_set_link_state(xhci, port_array, wIndex, 881 link_state); 882 883 spin_unlock_irqrestore(&xhci->lock, flags); 884 msleep(20); /* wait device to enter */ 885 spin_lock_irqsave(&xhci->lock, flags); 886 887 temp = readl(port_array[wIndex]); 888 if (link_state == USB_SS_PORT_LS_U3) 889 bus_state->suspended_ports |= 1 << wIndex; 890 break; 891 case USB_PORT_FEAT_POWER: 892 /* 893 * Turn on ports, even if there isn't per-port switching. 894 * HC will report connect events even before this is set. 895 * However, khubd will ignore the roothub events until 896 * the roothub is registered. 897 */ 898 writel(temp | PORT_POWER, port_array[wIndex]); 899 900 temp = readl(port_array[wIndex]); 901 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp); 902 903 spin_unlock_irqrestore(&xhci->lock, flags); 904 temp = usb_acpi_power_manageable(hcd->self.root_hub, 905 wIndex); 906 if (temp) 907 usb_acpi_set_power_state(hcd->self.root_hub, 908 wIndex, true); 909 spin_lock_irqsave(&xhci->lock, flags); 910 break; 911 case USB_PORT_FEAT_RESET: 912 temp = (temp | PORT_RESET); 913 writel(temp, port_array[wIndex]); 914 915 temp = readl(port_array[wIndex]); 916 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp); 917 break; 918 case USB_PORT_FEAT_REMOTE_WAKE_MASK: 919 xhci_set_remote_wake_mask(xhci, port_array, 920 wIndex, wake_mask); 921 temp = readl(port_array[wIndex]); 922 xhci_dbg(xhci, "set port remote wake mask, " 923 "actual port %d status = 0x%x\n", 924 wIndex, temp); 925 break; 926 case USB_PORT_FEAT_BH_PORT_RESET: 927 temp |= PORT_WR; 928 writel(temp, port_array[wIndex]); 929 930 temp = readl(port_array[wIndex]); 931 break; 932 case USB_PORT_FEAT_U1_TIMEOUT: 933 if (hcd->speed != HCD_USB3) 934 goto error; 935 temp = readl(port_array[wIndex] + PORTPMSC); 936 temp &= ~PORT_U1_TIMEOUT_MASK; 937 temp |= PORT_U1_TIMEOUT(timeout); 938 writel(temp, port_array[wIndex] + PORTPMSC); 939 break; 940 case USB_PORT_FEAT_U2_TIMEOUT: 941 if (hcd->speed != HCD_USB3) 942 goto error; 943 temp = readl(port_array[wIndex] + PORTPMSC); 944 temp &= ~PORT_U2_TIMEOUT_MASK; 945 temp |= PORT_U2_TIMEOUT(timeout); 946 writel(temp, port_array[wIndex] + PORTPMSC); 947 break; 948 default: 949 goto error; 950 } 951 /* unblock any posted writes */ 952 temp = readl(port_array[wIndex]); 953 break; 954 case ClearPortFeature: 955 if (!wIndex || wIndex > max_ports) 956 goto error; 957 wIndex--; 958 temp = readl(port_array[wIndex]); 959 if (temp == 0xffffffff) { 960 retval = -ENODEV; 961 break; 962 } 963 /* FIXME: What new port features do we need to support? */ 964 temp = xhci_port_state_to_neutral(temp); 965 switch (wValue) { 966 case USB_PORT_FEAT_SUSPEND: 967 temp = readl(port_array[wIndex]); 968 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n"); 969 xhci_dbg(xhci, "PORTSC %04x\n", temp); 970 if (temp & PORT_RESET) 971 goto error; 972 if ((temp & PORT_PLS_MASK) == XDEV_U3) { 973 if ((temp & PORT_PE) == 0) 974 goto error; 975 976 xhci_set_link_state(xhci, port_array, wIndex, 977 XDEV_RESUME); 978 spin_unlock_irqrestore(&xhci->lock, flags); 979 msleep(20); 980 spin_lock_irqsave(&xhci->lock, flags); 981 xhci_set_link_state(xhci, port_array, wIndex, 982 XDEV_U0); 983 } 984 bus_state->port_c_suspend |= 1 << wIndex; 985 986 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 987 wIndex + 1); 988 if (!slot_id) { 989 xhci_dbg(xhci, "slot_id is zero\n"); 990 goto error; 991 } 992 xhci_ring_device(xhci, slot_id); 993 break; 994 case USB_PORT_FEAT_C_SUSPEND: 995 bus_state->port_c_suspend &= ~(1 << wIndex); 996 case USB_PORT_FEAT_C_RESET: 997 case USB_PORT_FEAT_C_BH_PORT_RESET: 998 case USB_PORT_FEAT_C_CONNECTION: 999 case USB_PORT_FEAT_C_OVER_CURRENT: 1000 case USB_PORT_FEAT_C_ENABLE: 1001 case USB_PORT_FEAT_C_PORT_LINK_STATE: 1002 xhci_clear_port_change_bit(xhci, wValue, wIndex, 1003 port_array[wIndex], temp); 1004 break; 1005 case USB_PORT_FEAT_ENABLE: 1006 xhci_disable_port(hcd, xhci, wIndex, 1007 port_array[wIndex], temp); 1008 break; 1009 case USB_PORT_FEAT_POWER: 1010 writel(temp & ~PORT_POWER, port_array[wIndex]); 1011 1012 spin_unlock_irqrestore(&xhci->lock, flags); 1013 temp = usb_acpi_power_manageable(hcd->self.root_hub, 1014 wIndex); 1015 if (temp) 1016 usb_acpi_set_power_state(hcd->self.root_hub, 1017 wIndex, false); 1018 spin_lock_irqsave(&xhci->lock, flags); 1019 break; 1020 default: 1021 goto error; 1022 } 1023 break; 1024 default: 1025 error: 1026 /* "stall" on error */ 1027 retval = -EPIPE; 1028 } 1029 spin_unlock_irqrestore(&xhci->lock, flags); 1030 return retval; 1031 } 1032 1033 /* 1034 * Returns 0 if the status hasn't changed, or the number of bytes in buf. 1035 * Ports are 0-indexed from the HCD point of view, 1036 * and 1-indexed from the USB core pointer of view. 1037 * 1038 * Note that the status change bits will be cleared as soon as a port status 1039 * change event is generated, so we use the saved status from that event. 1040 */ 1041 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf) 1042 { 1043 unsigned long flags; 1044 u32 temp, status; 1045 u32 mask; 1046 int i, retval; 1047 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1048 int max_ports; 1049 __le32 __iomem **port_array; 1050 struct xhci_bus_state *bus_state; 1051 bool reset_change = false; 1052 1053 max_ports = xhci_get_ports(hcd, &port_array); 1054 bus_state = &xhci->bus_state[hcd_index(hcd)]; 1055 1056 /* Initial status is no changes */ 1057 retval = (max_ports + 8) / 8; 1058 memset(buf, 0, retval); 1059 1060 /* 1061 * Inform the usbcore about resume-in-progress by returning 1062 * a non-zero value even if there are no status changes. 1063 */ 1064 status = bus_state->resuming_ports; 1065 1066 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC; 1067 1068 spin_lock_irqsave(&xhci->lock, flags); 1069 /* For each port, did anything change? If so, set that bit in buf. */ 1070 for (i = 0; i < max_ports; i++) { 1071 temp = readl(port_array[i]); 1072 if (temp == 0xffffffff) { 1073 retval = -ENODEV; 1074 break; 1075 } 1076 if ((temp & mask) != 0 || 1077 (bus_state->port_c_suspend & 1 << i) || 1078 (bus_state->resume_done[i] && time_after_eq( 1079 jiffies, bus_state->resume_done[i]))) { 1080 buf[(i + 1) / 8] |= 1 << (i + 1) % 8; 1081 status = 1; 1082 } 1083 if ((temp & PORT_RC)) 1084 reset_change = true; 1085 } 1086 if (!status && !reset_change) { 1087 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__); 1088 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); 1089 } 1090 spin_unlock_irqrestore(&xhci->lock, flags); 1091 return status ? retval : 0; 1092 } 1093 1094 #ifdef CONFIG_PM 1095 1096 int xhci_bus_suspend(struct usb_hcd *hcd) 1097 { 1098 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1099 int max_ports, port_index; 1100 __le32 __iomem **port_array; 1101 struct xhci_bus_state *bus_state; 1102 unsigned long flags; 1103 1104 max_ports = xhci_get_ports(hcd, &port_array); 1105 bus_state = &xhci->bus_state[hcd_index(hcd)]; 1106 1107 spin_lock_irqsave(&xhci->lock, flags); 1108 1109 if (hcd->self.root_hub->do_remote_wakeup) { 1110 if (bus_state->resuming_ports) { 1111 spin_unlock_irqrestore(&xhci->lock, flags); 1112 xhci_dbg(xhci, "suspend failed because " 1113 "a port is resuming\n"); 1114 return -EBUSY; 1115 } 1116 } 1117 1118 port_index = max_ports; 1119 bus_state->bus_suspended = 0; 1120 while (port_index--) { 1121 /* suspend the port if the port is not suspended */ 1122 u32 t1, t2; 1123 int slot_id; 1124 1125 t1 = readl(port_array[port_index]); 1126 t2 = xhci_port_state_to_neutral(t1); 1127 1128 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) { 1129 xhci_dbg(xhci, "port %d not suspended\n", port_index); 1130 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 1131 port_index + 1); 1132 if (slot_id) { 1133 spin_unlock_irqrestore(&xhci->lock, flags); 1134 xhci_stop_device(xhci, slot_id, 1); 1135 spin_lock_irqsave(&xhci->lock, flags); 1136 } 1137 t2 &= ~PORT_PLS_MASK; 1138 t2 |= PORT_LINK_STROBE | XDEV_U3; 1139 set_bit(port_index, &bus_state->bus_suspended); 1140 } 1141 /* USB core sets remote wake mask for USB 3.0 hubs, 1142 * including the USB 3.0 roothub, but only if CONFIG_PM_RUNTIME 1143 * is enabled, so also enable remote wake here. 1144 */ 1145 if (hcd->self.root_hub->do_remote_wakeup 1146 && device_may_wakeup(hcd->self.controller)) { 1147 1148 if (t1 & PORT_CONNECT) { 1149 t2 |= PORT_WKOC_E | PORT_WKDISC_E; 1150 t2 &= ~PORT_WKCONN_E; 1151 } else { 1152 t2 |= PORT_WKOC_E | PORT_WKCONN_E; 1153 t2 &= ~PORT_WKDISC_E; 1154 } 1155 } else 1156 t2 &= ~PORT_WAKE_BITS; 1157 1158 t1 = xhci_port_state_to_neutral(t1); 1159 if (t1 != t2) 1160 writel(t2, port_array[port_index]); 1161 } 1162 hcd->state = HC_STATE_SUSPENDED; 1163 bus_state->next_statechange = jiffies + msecs_to_jiffies(10); 1164 spin_unlock_irqrestore(&xhci->lock, flags); 1165 return 0; 1166 } 1167 1168 int xhci_bus_resume(struct usb_hcd *hcd) 1169 { 1170 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1171 int max_ports, port_index; 1172 __le32 __iomem **port_array; 1173 struct xhci_bus_state *bus_state; 1174 u32 temp; 1175 unsigned long flags; 1176 1177 max_ports = xhci_get_ports(hcd, &port_array); 1178 bus_state = &xhci->bus_state[hcd_index(hcd)]; 1179 1180 if (time_before(jiffies, bus_state->next_statechange)) 1181 msleep(5); 1182 1183 spin_lock_irqsave(&xhci->lock, flags); 1184 if (!HCD_HW_ACCESSIBLE(hcd)) { 1185 spin_unlock_irqrestore(&xhci->lock, flags); 1186 return -ESHUTDOWN; 1187 } 1188 1189 /* delay the irqs */ 1190 temp = readl(&xhci->op_regs->command); 1191 temp &= ~CMD_EIE; 1192 writel(temp, &xhci->op_regs->command); 1193 1194 port_index = max_ports; 1195 while (port_index--) { 1196 /* Check whether need resume ports. If needed 1197 resume port and disable remote wakeup */ 1198 u32 temp; 1199 int slot_id; 1200 1201 temp = readl(port_array[port_index]); 1202 if (DEV_SUPERSPEED(temp)) 1203 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); 1204 else 1205 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); 1206 if (test_bit(port_index, &bus_state->bus_suspended) && 1207 (temp & PORT_PLS_MASK)) { 1208 if (DEV_SUPERSPEED(temp)) { 1209 xhci_set_link_state(xhci, port_array, 1210 port_index, XDEV_U0); 1211 } else { 1212 xhci_set_link_state(xhci, port_array, 1213 port_index, XDEV_RESUME); 1214 1215 spin_unlock_irqrestore(&xhci->lock, flags); 1216 msleep(20); 1217 spin_lock_irqsave(&xhci->lock, flags); 1218 1219 xhci_set_link_state(xhci, port_array, 1220 port_index, XDEV_U0); 1221 } 1222 /* wait for the port to enter U0 and report port link 1223 * state change. 1224 */ 1225 spin_unlock_irqrestore(&xhci->lock, flags); 1226 msleep(20); 1227 spin_lock_irqsave(&xhci->lock, flags); 1228 1229 /* Clear PLC */ 1230 xhci_test_and_clear_bit(xhci, port_array, port_index, 1231 PORT_PLC); 1232 1233 slot_id = xhci_find_slot_id_by_port(hcd, 1234 xhci, port_index + 1); 1235 if (slot_id) 1236 xhci_ring_device(xhci, slot_id); 1237 } else 1238 writel(temp, port_array[port_index]); 1239 } 1240 1241 (void) readl(&xhci->op_regs->command); 1242 1243 bus_state->next_statechange = jiffies + msecs_to_jiffies(5); 1244 /* re-enable irqs */ 1245 temp = readl(&xhci->op_regs->command); 1246 temp |= CMD_EIE; 1247 writel(temp, &xhci->op_regs->command); 1248 temp = readl(&xhci->op_regs->command); 1249 1250 spin_unlock_irqrestore(&xhci->lock, flags); 1251 return 0; 1252 } 1253 1254 #endif /* CONFIG_PM */ 1255