1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 12 #include <linux/slab.h> 13 #include <asm/unaligned.h> 14 #include <linux/bitfield.h> 15 16 #include "xhci.h" 17 #include "xhci-trace.h" 18 19 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) 20 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ 21 PORT_RC | PORT_PLC | PORT_PE) 22 23 /* Default sublink speed attribute of each lane */ 24 static u32 ssp_cap_default_ssa[] = { 25 0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */ 26 0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */ 27 0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */ 28 0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */ 29 0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */ 30 0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */ 31 0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */ 32 0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */ 33 }; 34 35 static int xhci_create_usb3x_bos_desc(struct xhci_hcd *xhci, char *buf, 36 u16 wLength) 37 { 38 struct usb_bos_descriptor *bos; 39 struct usb_ss_cap_descriptor *ss_cap; 40 struct usb_ssp_cap_descriptor *ssp_cap; 41 struct xhci_port_cap *port_cap = NULL; 42 u16 bcdUSB; 43 u32 reg; 44 u32 min_rate = 0; 45 u8 min_ssid; 46 u8 ssac; 47 u8 ssic; 48 int offset; 49 int i; 50 51 /* BOS descriptor */ 52 bos = (struct usb_bos_descriptor *)buf; 53 bos->bLength = USB_DT_BOS_SIZE; 54 bos->bDescriptorType = USB_DT_BOS; 55 bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE + 56 USB_DT_USB_SS_CAP_SIZE); 57 bos->bNumDeviceCaps = 1; 58 59 /* Create the descriptor for port with the highest revision */ 60 for (i = 0; i < xhci->num_port_caps; i++) { 61 u8 major = xhci->port_caps[i].maj_rev; 62 u8 minor = xhci->port_caps[i].min_rev; 63 u16 rev = (major << 8) | minor; 64 65 if (i == 0 || bcdUSB < rev) { 66 bcdUSB = rev; 67 port_cap = &xhci->port_caps[i]; 68 } 69 } 70 71 if (bcdUSB >= 0x0310) { 72 if (port_cap->psi_count) { 73 u8 num_sym_ssa = 0; 74 75 for (i = 0; i < port_cap->psi_count; i++) { 76 if ((port_cap->psi[i] & PLT_MASK) == PLT_SYM) 77 num_sym_ssa++; 78 } 79 80 ssac = port_cap->psi_count + num_sym_ssa - 1; 81 ssic = port_cap->psi_uid_count - 1; 82 } else { 83 if (bcdUSB >= 0x0320) 84 ssac = 7; 85 else 86 ssac = 3; 87 88 ssic = (ssac + 1) / 2 - 1; 89 } 90 91 bos->bNumDeviceCaps++; 92 bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE + 93 USB_DT_USB_SS_CAP_SIZE + 94 USB_DT_USB_SSP_CAP_SIZE(ssac)); 95 } 96 97 if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE) 98 return wLength; 99 100 /* SuperSpeed USB Device Capability */ 101 ss_cap = (struct usb_ss_cap_descriptor *)&buf[USB_DT_BOS_SIZE]; 102 ss_cap->bLength = USB_DT_USB_SS_CAP_SIZE; 103 ss_cap->bDescriptorType = USB_DT_DEVICE_CAPABILITY; 104 ss_cap->bDevCapabilityType = USB_SS_CAP_TYPE; 105 ss_cap->bmAttributes = 0; /* set later */ 106 ss_cap->wSpeedSupported = cpu_to_le16(USB_5GBPS_OPERATION); 107 ss_cap->bFunctionalitySupport = USB_LOW_SPEED_OPERATION; 108 ss_cap->bU1devExitLat = 0; /* set later */ 109 ss_cap->bU2DevExitLat = 0; /* set later */ 110 111 reg = readl(&xhci->cap_regs->hcc_params); 112 if (HCC_LTC(reg)) 113 ss_cap->bmAttributes |= USB_LTM_SUPPORT; 114 115 if ((xhci->quirks & XHCI_LPM_SUPPORT)) { 116 reg = readl(&xhci->cap_regs->hcs_params3); 117 ss_cap->bU1devExitLat = HCS_U1_LATENCY(reg); 118 ss_cap->bU2DevExitLat = cpu_to_le16(HCS_U2_LATENCY(reg)); 119 } 120 121 if (wLength < le16_to_cpu(bos->wTotalLength)) 122 return wLength; 123 124 if (bcdUSB < 0x0310) 125 return le16_to_cpu(bos->wTotalLength); 126 127 ssp_cap = (struct usb_ssp_cap_descriptor *)&buf[USB_DT_BOS_SIZE + 128 USB_DT_USB_SS_CAP_SIZE]; 129 ssp_cap->bLength = USB_DT_USB_SSP_CAP_SIZE(ssac); 130 ssp_cap->bDescriptorType = USB_DT_DEVICE_CAPABILITY; 131 ssp_cap->bDevCapabilityType = USB_SSP_CAP_TYPE; 132 ssp_cap->bReserved = 0; 133 ssp_cap->wReserved = 0; 134 ssp_cap->bmAttributes = 135 cpu_to_le32(FIELD_PREP(USB_SSP_SUBLINK_SPEED_ATTRIBS, ssac) | 136 FIELD_PREP(USB_SSP_SUBLINK_SPEED_IDS, ssic)); 137 138 if (!port_cap->psi_count) { 139 for (i = 0; i < ssac + 1; i++) 140 ssp_cap->bmSublinkSpeedAttr[i] = 141 cpu_to_le32(ssp_cap_default_ssa[i]); 142 143 min_ssid = 4; 144 goto out; 145 } 146 147 offset = 0; 148 for (i = 0; i < port_cap->psi_count; i++) { 149 u32 psi; 150 u32 attr; 151 u8 ssid; 152 u8 lp; 153 u8 lse; 154 u8 psie; 155 u16 lane_mantissa; 156 u16 psim; 157 u16 plt; 158 159 psi = port_cap->psi[i]; 160 ssid = XHCI_EXT_PORT_PSIV(psi); 161 lp = XHCI_EXT_PORT_LP(psi); 162 psie = XHCI_EXT_PORT_PSIE(psi); 163 psim = XHCI_EXT_PORT_PSIM(psi); 164 plt = psi & PLT_MASK; 165 166 lse = psie; 167 lane_mantissa = psim; 168 169 /* Shift to Gbps and set SSP Link Protocol if 10Gpbs */ 170 for (; psie < USB_SSP_SUBLINK_SPEED_LSE_GBPS; psie++) 171 psim /= 1000; 172 173 if (!min_rate || psim < min_rate) { 174 min_ssid = ssid; 175 min_rate = psim; 176 } 177 178 /* Some host controllers don't set the link protocol for SSP */ 179 if (psim >= 10) 180 lp = USB_SSP_SUBLINK_SPEED_LP_SSP; 181 182 /* 183 * PSIM and PSIE represent the total speed of PSI. The BOS 184 * descriptor SSP sublink speed attribute lane mantissa 185 * describes the lane speed. E.g. PSIM and PSIE for gen2x2 186 * is 20Gbps, but the BOS descriptor lane speed mantissa is 187 * 10Gbps. Check and modify the mantissa value to match the 188 * lane speed. 189 */ 190 if (bcdUSB == 0x0320 && plt == PLT_SYM) { 191 /* 192 * The PSI dword for gen1x2 and gen2x1 share the same 193 * values. But the lane speed for gen1x2 is 5Gbps while 194 * gen2x1 is 10Gbps. If the previous PSI dword SSID is 195 * 5 and the PSIE and PSIM match with SSID 6, let's 196 * assume that the controller follows the default speed 197 * id with SSID 6 for gen1x2. 198 */ 199 if (ssid == 6 && psie == 3 && psim == 10 && i) { 200 u32 prev = port_cap->psi[i - 1]; 201 202 if ((prev & PLT_MASK) == PLT_SYM && 203 XHCI_EXT_PORT_PSIV(prev) == 5 && 204 XHCI_EXT_PORT_PSIE(prev) == 3 && 205 XHCI_EXT_PORT_PSIM(prev) == 10) { 206 lse = USB_SSP_SUBLINK_SPEED_LSE_GBPS; 207 lane_mantissa = 5; 208 } 209 } 210 211 if (psie == 3 && psim > 10) { 212 lse = USB_SSP_SUBLINK_SPEED_LSE_GBPS; 213 lane_mantissa = 10; 214 } 215 } 216 217 attr = (FIELD_PREP(USB_SSP_SUBLINK_SPEED_SSID, ssid) | 218 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LP, lp) | 219 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSE, lse) | 220 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSM, lane_mantissa)); 221 222 switch (plt) { 223 case PLT_SYM: 224 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST, 225 USB_SSP_SUBLINK_SPEED_ST_SYM_RX); 226 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr); 227 228 attr &= ~USB_SSP_SUBLINK_SPEED_ST; 229 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST, 230 USB_SSP_SUBLINK_SPEED_ST_SYM_TX); 231 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr); 232 break; 233 case PLT_ASYM_RX: 234 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST, 235 USB_SSP_SUBLINK_SPEED_ST_ASYM_RX); 236 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr); 237 break; 238 case PLT_ASYM_TX: 239 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST, 240 USB_SSP_SUBLINK_SPEED_ST_ASYM_TX); 241 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr); 242 break; 243 } 244 } 245 out: 246 ssp_cap->wFunctionalitySupport = 247 cpu_to_le16(FIELD_PREP(USB_SSP_MIN_SUBLINK_SPEED_ATTRIBUTE_ID, 248 min_ssid) | 249 FIELD_PREP(USB_SSP_MIN_RX_LANE_COUNT, 1) | 250 FIELD_PREP(USB_SSP_MIN_TX_LANE_COUNT, 1)); 251 252 return le16_to_cpu(bos->wTotalLength); 253 } 254 255 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci, 256 struct usb_hub_descriptor *desc, int ports) 257 { 258 u16 temp; 259 260 desc->bHubContrCurrent = 0; 261 262 desc->bNbrPorts = ports; 263 temp = 0; 264 /* Bits 1:0 - support per-port power switching, or power always on */ 265 if (HCC_PPC(xhci->hcc_params)) 266 temp |= HUB_CHAR_INDV_PORT_LPSM; 267 else 268 temp |= HUB_CHAR_NO_LPSM; 269 /* Bit 2 - root hubs are not part of a compound device */ 270 /* Bits 4:3 - individual port over current protection */ 271 temp |= HUB_CHAR_INDV_PORT_OCPM; 272 /* Bits 6:5 - no TTs in root ports */ 273 /* Bit 7 - no port indicators */ 274 desc->wHubCharacteristics = cpu_to_le16(temp); 275 } 276 277 /* Fill in the USB 2.0 roothub descriptor */ 278 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 279 struct usb_hub_descriptor *desc) 280 { 281 int ports; 282 u16 temp; 283 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8]; 284 u32 portsc; 285 unsigned int i; 286 struct xhci_hub *rhub; 287 288 rhub = &xhci->usb2_rhub; 289 ports = rhub->num_ports; 290 xhci_common_hub_descriptor(xhci, desc, ports); 291 desc->bDescriptorType = USB_DT_HUB; 292 temp = 1 + (ports / 8); 293 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; 294 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.8 says 20ms */ 295 296 /* The Device Removable bits are reported on a byte granularity. 297 * If the port doesn't exist within that byte, the bit is set to 0. 298 */ 299 memset(port_removable, 0, sizeof(port_removable)); 300 for (i = 0; i < ports; i++) { 301 portsc = readl(rhub->ports[i]->addr); 302 /* If a device is removable, PORTSC reports a 0, same as in the 303 * hub descriptor DeviceRemovable bits. 304 */ 305 if (portsc & PORT_DEV_REMOVE) 306 /* This math is hairy because bit 0 of DeviceRemovable 307 * is reserved, and bit 1 is for port 1, etc. 308 */ 309 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8); 310 } 311 312 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN 313 * ports on it. The USB 2.0 specification says that there are two 314 * variable length fields at the end of the hub descriptor: 315 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than 316 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array 317 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to 318 * 0xFF, so we initialize the both arrays (DeviceRemovable and 319 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each 320 * set of ports that actually exist. 321 */ 322 memset(desc->u.hs.DeviceRemovable, 0xff, 323 sizeof(desc->u.hs.DeviceRemovable)); 324 memset(desc->u.hs.PortPwrCtrlMask, 0xff, 325 sizeof(desc->u.hs.PortPwrCtrlMask)); 326 327 for (i = 0; i < (ports + 1 + 7) / 8; i++) 328 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i], 329 sizeof(__u8)); 330 } 331 332 /* Fill in the USB 3.0 roothub descriptor */ 333 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 334 struct usb_hub_descriptor *desc) 335 { 336 int ports; 337 u16 port_removable; 338 u32 portsc; 339 unsigned int i; 340 struct xhci_hub *rhub; 341 342 rhub = &xhci->usb3_rhub; 343 ports = rhub->num_ports; 344 xhci_common_hub_descriptor(xhci, desc, ports); 345 desc->bDescriptorType = USB_DT_SS_HUB; 346 desc->bDescLength = USB_DT_SS_HUB_SIZE; 347 desc->bPwrOn2PwrGood = 50; /* usb 3.1 may fail if less than 100ms */ 348 349 /* header decode latency should be zero for roothubs, 350 * see section 4.23.5.2. 351 */ 352 desc->u.ss.bHubHdrDecLat = 0; 353 desc->u.ss.wHubDelay = 0; 354 355 port_removable = 0; 356 /* bit 0 is reserved, bit 1 is for port 1, etc. */ 357 for (i = 0; i < ports; i++) { 358 portsc = readl(rhub->ports[i]->addr); 359 if (portsc & PORT_DEV_REMOVE) 360 port_removable |= 1 << (i + 1); 361 } 362 363 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable); 364 } 365 366 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 367 struct usb_hub_descriptor *desc) 368 { 369 370 if (hcd->speed >= HCD_USB3) 371 xhci_usb3_hub_descriptor(hcd, xhci, desc); 372 else 373 xhci_usb2_hub_descriptor(hcd, xhci, desc); 374 375 } 376 377 static unsigned int xhci_port_speed(unsigned int port_status) 378 { 379 if (DEV_LOWSPEED(port_status)) 380 return USB_PORT_STAT_LOW_SPEED; 381 if (DEV_HIGHSPEED(port_status)) 382 return USB_PORT_STAT_HIGH_SPEED; 383 /* 384 * FIXME: Yes, we should check for full speed, but the core uses that as 385 * a default in portspeed() in usb/core/hub.c (which is the only place 386 * USB_PORT_STAT_*_SPEED is used). 387 */ 388 return 0; 389 } 390 391 /* 392 * These bits are Read Only (RO) and should be saved and written to the 393 * registers: 0, 3, 10:13, 30 394 * connect status, over-current status, port speed, and device removable. 395 * connect status and port speed are also sticky - meaning they're in 396 * the AUX well and they aren't changed by a hot, warm, or cold reset. 397 */ 398 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30)) 399 /* 400 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: 401 * bits 5:8, 9, 14:15, 25:27 402 * link state, port power, port indicator state, "wake on" enable state 403 */ 404 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25)) 405 /* 406 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: 407 * bit 4 (port reset) 408 */ 409 #define XHCI_PORT_RW1S ((1<<4)) 410 /* 411 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: 412 * bits 1, 17, 18, 19, 20, 21, 22, 23 413 * port enable/disable, and 414 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports), 415 * over-current, reset, link state, and L1 change 416 */ 417 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17)) 418 /* 419 * Bit 16 is RW, and writing a '1' to it causes the link state control to be 420 * latched in 421 */ 422 #define XHCI_PORT_RW ((1<<16)) 423 /* 424 * These bits are Reserved Zero (RsvdZ) and zero should be written to them: 425 * bits 2, 24, 28:31 426 */ 427 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28)) 428 429 /* 430 * Given a port state, this function returns a value that would result in the 431 * port being in the same state, if the value was written to the port status 432 * control register. 433 * Save Read Only (RO) bits and save read/write bits where 434 * writing a 0 clears the bit and writing a 1 sets the bit (RWS). 435 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. 436 */ 437 u32 xhci_port_state_to_neutral(u32 state) 438 { 439 /* Save read-only status and port state */ 440 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS); 441 } 442 443 /* 444 * find slot id based on port number. 445 * @port: The one-based port number from one of the two split roothubs. 446 */ 447 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 448 u16 port) 449 { 450 int slot_id; 451 int i; 452 enum usb_device_speed speed; 453 454 slot_id = 0; 455 for (i = 0; i < MAX_HC_SLOTS; i++) { 456 if (!xhci->devs[i] || !xhci->devs[i]->udev) 457 continue; 458 speed = xhci->devs[i]->udev->speed; 459 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3)) 460 && xhci->devs[i]->fake_port == port) { 461 slot_id = i; 462 break; 463 } 464 } 465 466 return slot_id; 467 } 468 469 /* 470 * Stop device 471 * It issues stop endpoint command for EP 0 to 30. And wait the last command 472 * to complete. 473 * suspend will set to 1, if suspend bit need to set in command. 474 */ 475 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend) 476 { 477 struct xhci_virt_device *virt_dev; 478 struct xhci_command *cmd; 479 unsigned long flags; 480 int ret; 481 int i; 482 483 ret = 0; 484 virt_dev = xhci->devs[slot_id]; 485 if (!virt_dev) 486 return -ENODEV; 487 488 trace_xhci_stop_device(virt_dev); 489 490 cmd = xhci_alloc_command(xhci, true, GFP_NOIO); 491 if (!cmd) 492 return -ENOMEM; 493 494 spin_lock_irqsave(&xhci->lock, flags); 495 for (i = LAST_EP_INDEX; i > 0; i--) { 496 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) { 497 struct xhci_ep_ctx *ep_ctx; 498 struct xhci_command *command; 499 500 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i); 501 502 /* Check ep is running, required by AMD SNPS 3.1 xHC */ 503 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING) 504 continue; 505 506 command = xhci_alloc_command(xhci, false, GFP_NOWAIT); 507 if (!command) { 508 spin_unlock_irqrestore(&xhci->lock, flags); 509 ret = -ENOMEM; 510 goto cmd_cleanup; 511 } 512 513 ret = xhci_queue_stop_endpoint(xhci, command, slot_id, 514 i, suspend); 515 if (ret) { 516 spin_unlock_irqrestore(&xhci->lock, flags); 517 xhci_free_command(xhci, command); 518 goto cmd_cleanup; 519 } 520 } 521 } 522 ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend); 523 if (ret) { 524 spin_unlock_irqrestore(&xhci->lock, flags); 525 goto cmd_cleanup; 526 } 527 528 xhci_ring_cmd_db(xhci); 529 spin_unlock_irqrestore(&xhci->lock, flags); 530 531 /* Wait for last stop endpoint command to finish */ 532 wait_for_completion(cmd->completion); 533 534 if (cmd->status == COMP_COMMAND_ABORTED || 535 cmd->status == COMP_COMMAND_RING_STOPPED) { 536 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n"); 537 ret = -ETIME; 538 } 539 540 cmd_cleanup: 541 xhci_free_command(xhci, cmd); 542 return ret; 543 } 544 545 /* 546 * Ring device, it rings the all doorbells unconditionally. 547 */ 548 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id) 549 { 550 int i, s; 551 struct xhci_virt_ep *ep; 552 553 for (i = 0; i < LAST_EP_INDEX + 1; i++) { 554 ep = &xhci->devs[slot_id]->eps[i]; 555 556 if (ep->ep_state & EP_HAS_STREAMS) { 557 for (s = 1; s < ep->stream_info->num_streams; s++) 558 xhci_ring_ep_doorbell(xhci, slot_id, i, s); 559 } else if (ep->ring && ep->ring->dequeue) { 560 xhci_ring_ep_doorbell(xhci, slot_id, i, 0); 561 } 562 } 563 564 return; 565 } 566 567 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 568 u16 wIndex, __le32 __iomem *addr, u32 port_status) 569 { 570 /* Don't allow the USB core to disable SuperSpeed ports. */ 571 if (hcd->speed >= HCD_USB3) { 572 xhci_dbg(xhci, "Ignoring request to disable " 573 "SuperSpeed port.\n"); 574 return; 575 } 576 577 if (xhci->quirks & XHCI_BROKEN_PORT_PED) { 578 xhci_dbg(xhci, 579 "Broken Port Enabled/Disabled, ignoring port disable request.\n"); 580 return; 581 } 582 583 /* Write 1 to disable the port */ 584 writel(port_status | PORT_PE, addr); 585 port_status = readl(addr); 586 xhci_dbg(xhci, "disable port %d-%d, portsc: 0x%x\n", 587 hcd->self.busnum, wIndex + 1, port_status); 588 } 589 590 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, 591 u16 wIndex, __le32 __iomem *addr, u32 port_status) 592 { 593 char *port_change_bit; 594 u32 status; 595 596 switch (wValue) { 597 case USB_PORT_FEAT_C_RESET: 598 status = PORT_RC; 599 port_change_bit = "reset"; 600 break; 601 case USB_PORT_FEAT_C_BH_PORT_RESET: 602 status = PORT_WRC; 603 port_change_bit = "warm(BH) reset"; 604 break; 605 case USB_PORT_FEAT_C_CONNECTION: 606 status = PORT_CSC; 607 port_change_bit = "connect"; 608 break; 609 case USB_PORT_FEAT_C_OVER_CURRENT: 610 status = PORT_OCC; 611 port_change_bit = "over-current"; 612 break; 613 case USB_PORT_FEAT_C_ENABLE: 614 status = PORT_PEC; 615 port_change_bit = "enable/disable"; 616 break; 617 case USB_PORT_FEAT_C_SUSPEND: 618 status = PORT_PLC; 619 port_change_bit = "suspend/resume"; 620 break; 621 case USB_PORT_FEAT_C_PORT_LINK_STATE: 622 status = PORT_PLC; 623 port_change_bit = "link state"; 624 break; 625 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR: 626 status = PORT_CEC; 627 port_change_bit = "config error"; 628 break; 629 default: 630 /* Should never happen */ 631 return; 632 } 633 /* Change bits are all write 1 to clear */ 634 writel(port_status | status, addr); 635 port_status = readl(addr); 636 637 xhci_dbg(xhci, "clear port%d %s change, portsc: 0x%x\n", 638 wIndex + 1, port_change_bit, port_status); 639 } 640 641 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd) 642 { 643 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 644 645 if (hcd->speed >= HCD_USB3) 646 return &xhci->usb3_rhub; 647 return &xhci->usb2_rhub; 648 } 649 650 /* 651 * xhci_set_port_power() must be called with xhci->lock held. 652 * It will release and re-aquire the lock while calling ACPI 653 * method. 654 */ 655 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd, 656 u16 index, bool on, unsigned long *flags) 657 __must_hold(&xhci->lock) 658 { 659 struct xhci_hub *rhub; 660 struct xhci_port *port; 661 u32 temp; 662 663 rhub = xhci_get_rhub(hcd); 664 port = rhub->ports[index]; 665 temp = readl(port->addr); 666 667 xhci_dbg(xhci, "set port power %d-%d %s, portsc: 0x%x\n", 668 hcd->self.busnum, index + 1, on ? "ON" : "OFF", temp); 669 670 temp = xhci_port_state_to_neutral(temp); 671 672 if (on) { 673 /* Power on */ 674 writel(temp | PORT_POWER, port->addr); 675 readl(port->addr); 676 } else { 677 /* Power off */ 678 writel(temp & ~PORT_POWER, port->addr); 679 } 680 681 spin_unlock_irqrestore(&xhci->lock, *flags); 682 temp = usb_acpi_power_manageable(hcd->self.root_hub, 683 index); 684 if (temp) 685 usb_acpi_set_power_state(hcd->self.root_hub, 686 index, on); 687 spin_lock_irqsave(&xhci->lock, *flags); 688 } 689 690 static void xhci_port_set_test_mode(struct xhci_hcd *xhci, 691 u16 test_mode, u16 wIndex) 692 { 693 u32 temp; 694 struct xhci_port *port; 695 696 /* xhci only supports test mode for usb2 ports */ 697 port = xhci->usb2_rhub.ports[wIndex]; 698 temp = readl(port->addr + PORTPMSC); 699 temp |= test_mode << PORT_TEST_MODE_SHIFT; 700 writel(temp, port->addr + PORTPMSC); 701 xhci->test_mode = test_mode; 702 if (test_mode == USB_TEST_FORCE_ENABLE) 703 xhci_start(xhci); 704 } 705 706 static int xhci_enter_test_mode(struct xhci_hcd *xhci, 707 u16 test_mode, u16 wIndex, unsigned long *flags) 708 __must_hold(&xhci->lock) 709 { 710 int i, retval; 711 712 /* Disable all Device Slots */ 713 xhci_dbg(xhci, "Disable all slots\n"); 714 spin_unlock_irqrestore(&xhci->lock, *flags); 715 for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) { 716 if (!xhci->devs[i]) 717 continue; 718 719 retval = xhci_disable_slot(xhci, i); 720 if (retval) 721 xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n", 722 i, retval); 723 } 724 spin_lock_irqsave(&xhci->lock, *flags); 725 /* Put all ports to the Disable state by clear PP */ 726 xhci_dbg(xhci, "Disable all port (PP = 0)\n"); 727 /* Power off USB3 ports*/ 728 for (i = 0; i < xhci->usb3_rhub.num_ports; i++) 729 xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags); 730 /* Power off USB2 ports*/ 731 for (i = 0; i < xhci->usb2_rhub.num_ports; i++) 732 xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags); 733 /* Stop the controller */ 734 xhci_dbg(xhci, "Stop controller\n"); 735 retval = xhci_halt(xhci); 736 if (retval) 737 return retval; 738 /* Disable runtime PM for test mode */ 739 pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller); 740 /* Set PORTPMSC.PTC field to enter selected test mode */ 741 /* Port is selected by wIndex. port_id = wIndex + 1 */ 742 xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n", 743 test_mode, wIndex + 1); 744 xhci_port_set_test_mode(xhci, test_mode, wIndex); 745 return retval; 746 } 747 748 static int xhci_exit_test_mode(struct xhci_hcd *xhci) 749 { 750 int retval; 751 752 if (!xhci->test_mode) { 753 xhci_err(xhci, "Not in test mode, do nothing.\n"); 754 return 0; 755 } 756 if (xhci->test_mode == USB_TEST_FORCE_ENABLE && 757 !(xhci->xhc_state & XHCI_STATE_HALTED)) { 758 retval = xhci_halt(xhci); 759 if (retval) 760 return retval; 761 } 762 pm_runtime_allow(xhci_to_hcd(xhci)->self.controller); 763 xhci->test_mode = 0; 764 return xhci_reset(xhci); 765 } 766 767 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port, 768 u32 link_state) 769 { 770 u32 temp; 771 u32 portsc; 772 773 portsc = readl(port->addr); 774 temp = xhci_port_state_to_neutral(portsc); 775 temp &= ~PORT_PLS_MASK; 776 temp |= PORT_LINK_STROBE | link_state; 777 writel(temp, port->addr); 778 779 xhci_dbg(xhci, "Set port %d-%d link state, portsc: 0x%x, write 0x%x", 780 port->rhub->hcd->self.busnum, port->hcd_portnum + 1, 781 portsc, temp); 782 } 783 784 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci, 785 struct xhci_port *port, u16 wake_mask) 786 { 787 u32 temp; 788 789 temp = readl(port->addr); 790 temp = xhci_port_state_to_neutral(temp); 791 792 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT) 793 temp |= PORT_WKCONN_E; 794 else 795 temp &= ~PORT_WKCONN_E; 796 797 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT) 798 temp |= PORT_WKDISC_E; 799 else 800 temp &= ~PORT_WKDISC_E; 801 802 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT) 803 temp |= PORT_WKOC_E; 804 else 805 temp &= ~PORT_WKOC_E; 806 807 writel(temp, port->addr); 808 } 809 810 /* Test and clear port RWC bit */ 811 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port, 812 u32 port_bit) 813 { 814 u32 temp; 815 816 temp = readl(port->addr); 817 if (temp & port_bit) { 818 temp = xhci_port_state_to_neutral(temp); 819 temp |= port_bit; 820 writel(temp, port->addr); 821 } 822 } 823 824 /* Updates Link Status for super Speed port */ 825 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci, 826 u32 *status, u32 status_reg) 827 { 828 u32 pls = status_reg & PORT_PLS_MASK; 829 830 /* When the CAS bit is set then warm reset 831 * should be performed on port 832 */ 833 if (status_reg & PORT_CAS) { 834 /* The CAS bit can be set while the port is 835 * in any link state. 836 * Only roothubs have CAS bit, so we 837 * pretend to be in compliance mode 838 * unless we're already in compliance 839 * or the inactive state. 840 */ 841 if (pls != USB_SS_PORT_LS_COMP_MOD && 842 pls != USB_SS_PORT_LS_SS_INACTIVE) { 843 pls = USB_SS_PORT_LS_COMP_MOD; 844 } 845 /* Return also connection bit - 846 * hub state machine resets port 847 * when this bit is set. 848 */ 849 pls |= USB_PORT_STAT_CONNECTION; 850 } else { 851 /* 852 * Resume state is an xHCI internal state. Do not report it to 853 * usb core, instead, pretend to be U3, thus usb core knows 854 * it's not ready for transfer. 855 */ 856 if (pls == XDEV_RESUME) { 857 *status |= USB_SS_PORT_LS_U3; 858 return; 859 } 860 861 /* 862 * If CAS bit isn't set but the Port is already at 863 * Compliance Mode, fake a connection so the USB core 864 * notices the Compliance state and resets the port. 865 * This resolves an issue generated by the SN65LVPE502CP 866 * in which sometimes the port enters compliance mode 867 * caused by a delay on the host-device negotiation. 868 */ 869 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && 870 (pls == USB_SS_PORT_LS_COMP_MOD)) 871 pls |= USB_PORT_STAT_CONNECTION; 872 } 873 874 /* update status field */ 875 *status |= pls; 876 } 877 878 /* 879 * Function for Compliance Mode Quirk. 880 * 881 * This Function verifies if all xhc USB3 ports have entered U0, if so, 882 * the compliance mode timer is deleted. A port won't enter 883 * compliance mode if it has previously entered U0. 884 */ 885 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, 886 u16 wIndex) 887 { 888 u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1); 889 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0); 890 891 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK)) 892 return; 893 894 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) { 895 xhci->port_status_u0 |= 1 << wIndex; 896 if (xhci->port_status_u0 == all_ports_seen_u0) { 897 del_timer_sync(&xhci->comp_mode_recovery_timer); 898 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 899 "All USB3 ports have entered U0 already!"); 900 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 901 "Compliance Mode Recovery Timer Deleted."); 902 } 903 } 904 } 905 906 static int xhci_handle_usb2_port_link_resume(struct xhci_port *port, 907 u32 *status, u32 portsc, 908 unsigned long *flags) 909 { 910 struct xhci_bus_state *bus_state; 911 struct xhci_hcd *xhci; 912 struct usb_hcd *hcd; 913 int slot_id; 914 u32 wIndex; 915 916 hcd = port->rhub->hcd; 917 bus_state = &port->rhub->bus_state; 918 xhci = hcd_to_xhci(hcd); 919 wIndex = port->hcd_portnum; 920 921 if ((portsc & PORT_RESET) || !(portsc & PORT_PE)) { 922 *status = 0xffffffff; 923 return -EINVAL; 924 } 925 /* did port event handler already start resume timing? */ 926 if (!bus_state->resume_done[wIndex]) { 927 /* If not, maybe we are in a host initated resume? */ 928 if (test_bit(wIndex, &bus_state->resuming_ports)) { 929 /* Host initated resume doesn't time the resume 930 * signalling using resume_done[]. 931 * It manually sets RESUME state, sleeps 20ms 932 * and sets U0 state. This should probably be 933 * changed, but not right now. 934 */ 935 } else { 936 /* port resume was discovered now and here, 937 * start resume timing 938 */ 939 unsigned long timeout = jiffies + 940 msecs_to_jiffies(USB_RESUME_TIMEOUT); 941 942 set_bit(wIndex, &bus_state->resuming_ports); 943 bus_state->resume_done[wIndex] = timeout; 944 mod_timer(&hcd->rh_timer, timeout); 945 usb_hcd_start_port_resume(&hcd->self, wIndex); 946 } 947 /* Has resume been signalled for USB_RESUME_TIME yet? */ 948 } else if (time_after_eq(jiffies, bus_state->resume_done[wIndex])) { 949 int time_left; 950 951 xhci_dbg(xhci, "resume USB2 port %d-%d\n", 952 hcd->self.busnum, wIndex + 1); 953 954 bus_state->resume_done[wIndex] = 0; 955 clear_bit(wIndex, &bus_state->resuming_ports); 956 957 set_bit(wIndex, &bus_state->rexit_ports); 958 959 xhci_test_and_clear_bit(xhci, port, PORT_PLC); 960 xhci_set_link_state(xhci, port, XDEV_U0); 961 962 spin_unlock_irqrestore(&xhci->lock, *flags); 963 time_left = wait_for_completion_timeout( 964 &bus_state->rexit_done[wIndex], 965 msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS)); 966 spin_lock_irqsave(&xhci->lock, *flags); 967 968 if (time_left) { 969 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 970 wIndex + 1); 971 if (!slot_id) { 972 xhci_dbg(xhci, "slot_id is zero\n"); 973 *status = 0xffffffff; 974 return -ENODEV; 975 } 976 xhci_ring_device(xhci, slot_id); 977 } else { 978 int port_status = readl(port->addr); 979 980 xhci_warn(xhci, "Port resume timed out, port %d-%d: 0x%x\n", 981 hcd->self.busnum, wIndex + 1, port_status); 982 *status |= USB_PORT_STAT_SUSPEND; 983 clear_bit(wIndex, &bus_state->rexit_ports); 984 } 985 986 usb_hcd_end_port_resume(&hcd->self, wIndex); 987 bus_state->port_c_suspend |= 1 << wIndex; 988 bus_state->suspended_ports &= ~(1 << wIndex); 989 } else { 990 /* 991 * The resume has been signaling for less than 992 * USB_RESUME_TIME. Report the port status as SUSPEND, 993 * let the usbcore check port status again and clear 994 * resume signaling later. 995 */ 996 *status |= USB_PORT_STAT_SUSPEND; 997 } 998 return 0; 999 } 1000 1001 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li) 1002 { 1003 u32 ext_stat = 0; 1004 int speed_id; 1005 1006 /* only support rx and tx lane counts of 1 in usb3.1 spec */ 1007 speed_id = DEV_PORT_SPEED(raw_port_status); 1008 ext_stat |= speed_id; /* bits 3:0, RX speed id */ 1009 ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */ 1010 1011 ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */ 1012 ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */ 1013 1014 return ext_stat; 1015 } 1016 1017 static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status, 1018 u32 portsc) 1019 { 1020 struct xhci_bus_state *bus_state; 1021 struct xhci_hcd *xhci; 1022 struct usb_hcd *hcd; 1023 u32 link_state; 1024 u32 portnum; 1025 1026 bus_state = &port->rhub->bus_state; 1027 xhci = hcd_to_xhci(port->rhub->hcd); 1028 hcd = port->rhub->hcd; 1029 link_state = portsc & PORT_PLS_MASK; 1030 portnum = port->hcd_portnum; 1031 1032 /* USB3 specific wPortChange bits 1033 * 1034 * Port link change with port in resume state should not be 1035 * reported to usbcore, as this is an internal state to be 1036 * handled by xhci driver. Reporting PLC to usbcore may 1037 * cause usbcore clearing PLC first and port change event 1038 * irq won't be generated. 1039 */ 1040 1041 if (portsc & PORT_PLC && (link_state != XDEV_RESUME)) 1042 *status |= USB_PORT_STAT_C_LINK_STATE << 16; 1043 if (portsc & PORT_WRC) 1044 *status |= USB_PORT_STAT_C_BH_RESET << 16; 1045 if (portsc & PORT_CEC) 1046 *status |= USB_PORT_STAT_C_CONFIG_ERROR << 16; 1047 1048 /* USB3 specific wPortStatus bits */ 1049 if (portsc & PORT_POWER) { 1050 *status |= USB_SS_PORT_STAT_POWER; 1051 /* link state handling */ 1052 if (link_state == XDEV_U0) 1053 bus_state->suspended_ports &= ~(1 << portnum); 1054 } 1055 1056 /* remote wake resume signaling complete */ 1057 if (bus_state->port_remote_wakeup & (1 << portnum) && 1058 link_state != XDEV_RESUME && 1059 link_state != XDEV_RECOVERY) { 1060 bus_state->port_remote_wakeup &= ~(1 << portnum); 1061 usb_hcd_end_port_resume(&hcd->self, portnum); 1062 } 1063 1064 xhci_hub_report_usb3_link_state(xhci, status, portsc); 1065 xhci_del_comp_mod_timer(xhci, portsc, portnum); 1066 } 1067 1068 static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status, 1069 u32 portsc, unsigned long *flags) 1070 { 1071 struct xhci_bus_state *bus_state; 1072 u32 link_state; 1073 u32 portnum; 1074 int ret; 1075 1076 bus_state = &port->rhub->bus_state; 1077 link_state = portsc & PORT_PLS_MASK; 1078 portnum = port->hcd_portnum; 1079 1080 /* USB2 wPortStatus bits */ 1081 if (portsc & PORT_POWER) { 1082 *status |= USB_PORT_STAT_POWER; 1083 1084 /* link state is only valid if port is powered */ 1085 if (link_state == XDEV_U3) 1086 *status |= USB_PORT_STAT_SUSPEND; 1087 if (link_state == XDEV_U2) 1088 *status |= USB_PORT_STAT_L1; 1089 if (link_state == XDEV_U0) { 1090 bus_state->resume_done[portnum] = 0; 1091 clear_bit(portnum, &bus_state->resuming_ports); 1092 if (bus_state->suspended_ports & (1 << portnum)) { 1093 bus_state->suspended_ports &= ~(1 << portnum); 1094 bus_state->port_c_suspend |= 1 << portnum; 1095 } 1096 } 1097 if (link_state == XDEV_RESUME) { 1098 ret = xhci_handle_usb2_port_link_resume(port, status, 1099 portsc, flags); 1100 if (ret) 1101 return; 1102 } 1103 } 1104 } 1105 1106 /* 1107 * Converts a raw xHCI port status into the format that external USB 2.0 or USB 1108 * 3.0 hubs use. 1109 * 1110 * Possible side effects: 1111 * - Mark a port as being done with device resume, 1112 * and ring the endpoint doorbells. 1113 * - Stop the Synopsys redriver Compliance Mode polling. 1114 * - Drop and reacquire the xHCI lock, in order to wait for port resume. 1115 */ 1116 static u32 xhci_get_port_status(struct usb_hcd *hcd, 1117 struct xhci_bus_state *bus_state, 1118 u16 wIndex, u32 raw_port_status, 1119 unsigned long *flags) 1120 __releases(&xhci->lock) 1121 __acquires(&xhci->lock) 1122 { 1123 u32 status = 0; 1124 struct xhci_hub *rhub; 1125 struct xhci_port *port; 1126 1127 rhub = xhci_get_rhub(hcd); 1128 port = rhub->ports[wIndex]; 1129 1130 /* common wPortChange bits */ 1131 if (raw_port_status & PORT_CSC) 1132 status |= USB_PORT_STAT_C_CONNECTION << 16; 1133 if (raw_port_status & PORT_PEC) 1134 status |= USB_PORT_STAT_C_ENABLE << 16; 1135 if ((raw_port_status & PORT_OCC)) 1136 status |= USB_PORT_STAT_C_OVERCURRENT << 16; 1137 if ((raw_port_status & PORT_RC)) 1138 status |= USB_PORT_STAT_C_RESET << 16; 1139 1140 /* common wPortStatus bits */ 1141 if (raw_port_status & PORT_CONNECT) { 1142 status |= USB_PORT_STAT_CONNECTION; 1143 status |= xhci_port_speed(raw_port_status); 1144 } 1145 if (raw_port_status & PORT_PE) 1146 status |= USB_PORT_STAT_ENABLE; 1147 if (raw_port_status & PORT_OC) 1148 status |= USB_PORT_STAT_OVERCURRENT; 1149 if (raw_port_status & PORT_RESET) 1150 status |= USB_PORT_STAT_RESET; 1151 1152 /* USB2 and USB3 specific bits, including Port Link State */ 1153 if (hcd->speed >= HCD_USB3) 1154 xhci_get_usb3_port_status(port, &status, raw_port_status); 1155 else 1156 xhci_get_usb2_port_status(port, &status, raw_port_status, 1157 flags); 1158 /* 1159 * Clear stale usb2 resume signalling variables in case port changed 1160 * state during resume signalling. For example on error 1161 */ 1162 if ((bus_state->resume_done[wIndex] || 1163 test_bit(wIndex, &bus_state->resuming_ports)) && 1164 (raw_port_status & PORT_PLS_MASK) != XDEV_U3 && 1165 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) { 1166 bus_state->resume_done[wIndex] = 0; 1167 clear_bit(wIndex, &bus_state->resuming_ports); 1168 usb_hcd_end_port_resume(&hcd->self, wIndex); 1169 } 1170 1171 if (bus_state->port_c_suspend & (1 << wIndex)) 1172 status |= USB_PORT_STAT_C_SUSPEND << 16; 1173 1174 return status; 1175 } 1176 1177 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 1178 u16 wIndex, char *buf, u16 wLength) 1179 { 1180 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1181 int max_ports; 1182 unsigned long flags; 1183 u32 temp, status; 1184 int retval = 0; 1185 int slot_id; 1186 struct xhci_bus_state *bus_state; 1187 u16 link_state = 0; 1188 u16 wake_mask = 0; 1189 u16 timeout = 0; 1190 u16 test_mode = 0; 1191 struct xhci_hub *rhub; 1192 struct xhci_port **ports; 1193 1194 rhub = xhci_get_rhub(hcd); 1195 ports = rhub->ports; 1196 max_ports = rhub->num_ports; 1197 bus_state = &rhub->bus_state; 1198 1199 spin_lock_irqsave(&xhci->lock, flags); 1200 switch (typeReq) { 1201 case GetHubStatus: 1202 /* No power source, over-current reported per port */ 1203 memset(buf, 0, 4); 1204 break; 1205 case GetHubDescriptor: 1206 /* Check to make sure userspace is asking for the USB 3.0 hub 1207 * descriptor for the USB 3.0 roothub. If not, we stall the 1208 * endpoint, like external hubs do. 1209 */ 1210 if (hcd->speed >= HCD_USB3 && 1211 (wLength < USB_DT_SS_HUB_SIZE || 1212 wValue != (USB_DT_SS_HUB << 8))) { 1213 xhci_dbg(xhci, "Wrong hub descriptor type for " 1214 "USB 3.0 roothub.\n"); 1215 goto error; 1216 } 1217 xhci_hub_descriptor(hcd, xhci, 1218 (struct usb_hub_descriptor *) buf); 1219 break; 1220 case DeviceRequest | USB_REQ_GET_DESCRIPTOR: 1221 if ((wValue & 0xff00) != (USB_DT_BOS << 8)) 1222 goto error; 1223 1224 if (hcd->speed < HCD_USB3) 1225 goto error; 1226 1227 retval = xhci_create_usb3x_bos_desc(xhci, buf, wLength); 1228 spin_unlock_irqrestore(&xhci->lock, flags); 1229 return retval; 1230 case GetPortStatus: 1231 if (!wIndex || wIndex > max_ports) 1232 goto error; 1233 wIndex--; 1234 temp = readl(ports[wIndex]->addr); 1235 if (temp == ~(u32)0) { 1236 xhci_hc_died(xhci); 1237 retval = -ENODEV; 1238 break; 1239 } 1240 trace_xhci_get_port_status(wIndex, temp); 1241 status = xhci_get_port_status(hcd, bus_state, wIndex, temp, 1242 &flags); 1243 if (status == 0xffffffff) 1244 goto error; 1245 1246 xhci_dbg(xhci, "Get port status %d-%d read: 0x%x, return 0x%x", 1247 hcd->self.busnum, wIndex + 1, temp, status); 1248 1249 put_unaligned(cpu_to_le32(status), (__le32 *) buf); 1250 /* if USB 3.1 extended port status return additional 4 bytes */ 1251 if (wValue == 0x02) { 1252 u32 port_li; 1253 1254 if (hcd->speed < HCD_USB31 || wLength != 8) { 1255 xhci_err(xhci, "get ext port status invalid parameter\n"); 1256 retval = -EINVAL; 1257 break; 1258 } 1259 port_li = readl(ports[wIndex]->addr + PORTLI); 1260 status = xhci_get_ext_port_status(temp, port_li); 1261 put_unaligned_le32(status, &buf[4]); 1262 } 1263 break; 1264 case SetPortFeature: 1265 if (wValue == USB_PORT_FEAT_LINK_STATE) 1266 link_state = (wIndex & 0xff00) >> 3; 1267 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK) 1268 wake_mask = wIndex & 0xff00; 1269 if (wValue == USB_PORT_FEAT_TEST) 1270 test_mode = (wIndex & 0xff00) >> 8; 1271 /* The MSB of wIndex is the U1/U2 timeout */ 1272 timeout = (wIndex & 0xff00) >> 8; 1273 wIndex &= 0xff; 1274 if (!wIndex || wIndex > max_ports) 1275 goto error; 1276 wIndex--; 1277 temp = readl(ports[wIndex]->addr); 1278 if (temp == ~(u32)0) { 1279 xhci_hc_died(xhci); 1280 retval = -ENODEV; 1281 break; 1282 } 1283 temp = xhci_port_state_to_neutral(temp); 1284 /* FIXME: What new port features do we need to support? */ 1285 switch (wValue) { 1286 case USB_PORT_FEAT_SUSPEND: 1287 temp = readl(ports[wIndex]->addr); 1288 if ((temp & PORT_PLS_MASK) != XDEV_U0) { 1289 /* Resume the port to U0 first */ 1290 xhci_set_link_state(xhci, ports[wIndex], 1291 XDEV_U0); 1292 spin_unlock_irqrestore(&xhci->lock, flags); 1293 msleep(10); 1294 spin_lock_irqsave(&xhci->lock, flags); 1295 } 1296 /* In spec software should not attempt to suspend 1297 * a port unless the port reports that it is in the 1298 * enabled (PED = ‘1’,PLS < ‘3’) state. 1299 */ 1300 temp = readl(ports[wIndex]->addr); 1301 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) 1302 || (temp & PORT_PLS_MASK) >= XDEV_U3) { 1303 xhci_warn(xhci, "USB core suspending port %d-%d not in U0/U1/U2\n", 1304 hcd->self.busnum, wIndex + 1); 1305 goto error; 1306 } 1307 1308 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 1309 wIndex + 1); 1310 if (!slot_id) { 1311 xhci_warn(xhci, "slot_id is zero\n"); 1312 goto error; 1313 } 1314 /* unlock to execute stop endpoint commands */ 1315 spin_unlock_irqrestore(&xhci->lock, flags); 1316 xhci_stop_device(xhci, slot_id, 1); 1317 spin_lock_irqsave(&xhci->lock, flags); 1318 1319 xhci_set_link_state(xhci, ports[wIndex], XDEV_U3); 1320 1321 spin_unlock_irqrestore(&xhci->lock, flags); 1322 msleep(10); /* wait device to enter */ 1323 spin_lock_irqsave(&xhci->lock, flags); 1324 1325 temp = readl(ports[wIndex]->addr); 1326 bus_state->suspended_ports |= 1 << wIndex; 1327 break; 1328 case USB_PORT_FEAT_LINK_STATE: 1329 temp = readl(ports[wIndex]->addr); 1330 /* Disable port */ 1331 if (link_state == USB_SS_PORT_LS_SS_DISABLED) { 1332 xhci_dbg(xhci, "Disable port %d-%d\n", 1333 hcd->self.busnum, wIndex + 1); 1334 temp = xhci_port_state_to_neutral(temp); 1335 /* 1336 * Clear all change bits, so that we get a new 1337 * connection event. 1338 */ 1339 temp |= PORT_CSC | PORT_PEC | PORT_WRC | 1340 PORT_OCC | PORT_RC | PORT_PLC | 1341 PORT_CEC; 1342 writel(temp | PORT_PE, ports[wIndex]->addr); 1343 temp = readl(ports[wIndex]->addr); 1344 break; 1345 } 1346 1347 /* Put link in RxDetect (enable port) */ 1348 if (link_state == USB_SS_PORT_LS_RX_DETECT) { 1349 xhci_dbg(xhci, "Enable port %d-%d\n", 1350 hcd->self.busnum, wIndex + 1); 1351 xhci_set_link_state(xhci, ports[wIndex], 1352 link_state); 1353 temp = readl(ports[wIndex]->addr); 1354 break; 1355 } 1356 1357 /* 1358 * For xHCI 1.1 according to section 4.19.1.2.4.1 a 1359 * root hub port's transition to compliance mode upon 1360 * detecting LFPS timeout may be controlled by an 1361 * Compliance Transition Enabled (CTE) flag (not 1362 * software visible). This flag is set by writing 0xA 1363 * to PORTSC PLS field which will allow transition to 1364 * compliance mode the next time LFPS timeout is 1365 * encountered. A warm reset will clear it. 1366 * 1367 * The CTE flag is only supported if the HCCPARAMS2 CTC 1368 * flag is set, otherwise, the compliance substate is 1369 * automatically entered as on 1.0 and prior. 1370 */ 1371 if (link_state == USB_SS_PORT_LS_COMP_MOD) { 1372 if (!HCC2_CTC(xhci->hcc_params2)) { 1373 xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n"); 1374 break; 1375 } 1376 1377 if ((temp & PORT_CONNECT)) { 1378 xhci_warn(xhci, "Can't set compliance mode when port is connected\n"); 1379 goto error; 1380 } 1381 1382 xhci_dbg(xhci, "Enable compliance mode transition for port %d-%d\n", 1383 hcd->self.busnum, wIndex + 1); 1384 xhci_set_link_state(xhci, ports[wIndex], 1385 link_state); 1386 1387 temp = readl(ports[wIndex]->addr); 1388 break; 1389 } 1390 /* Port must be enabled */ 1391 if (!(temp & PORT_PE)) { 1392 retval = -ENODEV; 1393 break; 1394 } 1395 /* Can't set port link state above '3' (U3) */ 1396 if (link_state > USB_SS_PORT_LS_U3) { 1397 xhci_warn(xhci, "Cannot set port %d-%d link state %d\n", 1398 hcd->self.busnum, wIndex + 1, 1399 link_state); 1400 goto error; 1401 } 1402 1403 /* 1404 * set link to U0, steps depend on current link state. 1405 * U3: set link to U0 and wait for u3exit completion. 1406 * U1/U2: no PLC complete event, only set link to U0. 1407 * Resume/Recovery: device initiated U0, only wait for 1408 * completion 1409 */ 1410 if (link_state == USB_SS_PORT_LS_U0) { 1411 u32 pls = temp & PORT_PLS_MASK; 1412 bool wait_u0 = false; 1413 1414 /* already in U0 */ 1415 if (pls == XDEV_U0) 1416 break; 1417 if (pls == XDEV_U3 || 1418 pls == XDEV_RESUME || 1419 pls == XDEV_RECOVERY) { 1420 wait_u0 = true; 1421 reinit_completion(&bus_state->u3exit_done[wIndex]); 1422 } 1423 if (pls <= XDEV_U3) /* U1, U2, U3 */ 1424 xhci_set_link_state(xhci, ports[wIndex], 1425 USB_SS_PORT_LS_U0); 1426 if (!wait_u0) { 1427 if (pls > XDEV_U3) 1428 goto error; 1429 break; 1430 } 1431 spin_unlock_irqrestore(&xhci->lock, flags); 1432 if (!wait_for_completion_timeout(&bus_state->u3exit_done[wIndex], 1433 msecs_to_jiffies(100))) 1434 xhci_dbg(xhci, "missing U0 port change event for port %d-%d\n", 1435 hcd->self.busnum, wIndex + 1); 1436 spin_lock_irqsave(&xhci->lock, flags); 1437 temp = readl(ports[wIndex]->addr); 1438 break; 1439 } 1440 1441 if (link_state == USB_SS_PORT_LS_U3) { 1442 int retries = 16; 1443 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 1444 wIndex + 1); 1445 if (slot_id) { 1446 /* unlock to execute stop endpoint 1447 * commands */ 1448 spin_unlock_irqrestore(&xhci->lock, 1449 flags); 1450 xhci_stop_device(xhci, slot_id, 1); 1451 spin_lock_irqsave(&xhci->lock, flags); 1452 } 1453 xhci_set_link_state(xhci, ports[wIndex], USB_SS_PORT_LS_U3); 1454 spin_unlock_irqrestore(&xhci->lock, flags); 1455 while (retries--) { 1456 usleep_range(4000, 8000); 1457 temp = readl(ports[wIndex]->addr); 1458 if ((temp & PORT_PLS_MASK) == XDEV_U3) 1459 break; 1460 } 1461 spin_lock_irqsave(&xhci->lock, flags); 1462 temp = readl(ports[wIndex]->addr); 1463 bus_state->suspended_ports |= 1 << wIndex; 1464 } 1465 break; 1466 case USB_PORT_FEAT_POWER: 1467 /* 1468 * Turn on ports, even if there isn't per-port switching. 1469 * HC will report connect events even before this is set. 1470 * However, hub_wq will ignore the roothub events until 1471 * the roothub is registered. 1472 */ 1473 xhci_set_port_power(xhci, hcd, wIndex, true, &flags); 1474 break; 1475 case USB_PORT_FEAT_RESET: 1476 temp = (temp | PORT_RESET); 1477 writel(temp, ports[wIndex]->addr); 1478 1479 temp = readl(ports[wIndex]->addr); 1480 xhci_dbg(xhci, "set port reset, actual port %d-%d status = 0x%x\n", 1481 hcd->self.busnum, wIndex + 1, temp); 1482 break; 1483 case USB_PORT_FEAT_REMOTE_WAKE_MASK: 1484 xhci_set_remote_wake_mask(xhci, ports[wIndex], 1485 wake_mask); 1486 temp = readl(ports[wIndex]->addr); 1487 xhci_dbg(xhci, "set port remote wake mask, actual port %d-%d status = 0x%x\n", 1488 hcd->self.busnum, wIndex + 1, temp); 1489 break; 1490 case USB_PORT_FEAT_BH_PORT_RESET: 1491 temp |= PORT_WR; 1492 writel(temp, ports[wIndex]->addr); 1493 temp = readl(ports[wIndex]->addr); 1494 break; 1495 case USB_PORT_FEAT_U1_TIMEOUT: 1496 if (hcd->speed < HCD_USB3) 1497 goto error; 1498 temp = readl(ports[wIndex]->addr + PORTPMSC); 1499 temp &= ~PORT_U1_TIMEOUT_MASK; 1500 temp |= PORT_U1_TIMEOUT(timeout); 1501 writel(temp, ports[wIndex]->addr + PORTPMSC); 1502 break; 1503 case USB_PORT_FEAT_U2_TIMEOUT: 1504 if (hcd->speed < HCD_USB3) 1505 goto error; 1506 temp = readl(ports[wIndex]->addr + PORTPMSC); 1507 temp &= ~PORT_U2_TIMEOUT_MASK; 1508 temp |= PORT_U2_TIMEOUT(timeout); 1509 writel(temp, ports[wIndex]->addr + PORTPMSC); 1510 break; 1511 case USB_PORT_FEAT_TEST: 1512 /* 4.19.6 Port Test Modes (USB2 Test Mode) */ 1513 if (hcd->speed != HCD_USB2) 1514 goto error; 1515 if (test_mode > USB_TEST_FORCE_ENABLE || 1516 test_mode < USB_TEST_J) 1517 goto error; 1518 retval = xhci_enter_test_mode(xhci, test_mode, wIndex, 1519 &flags); 1520 break; 1521 default: 1522 goto error; 1523 } 1524 /* unblock any posted writes */ 1525 temp = readl(ports[wIndex]->addr); 1526 break; 1527 case ClearPortFeature: 1528 if (!wIndex || wIndex > max_ports) 1529 goto error; 1530 wIndex--; 1531 temp = readl(ports[wIndex]->addr); 1532 if (temp == ~(u32)0) { 1533 xhci_hc_died(xhci); 1534 retval = -ENODEV; 1535 break; 1536 } 1537 /* FIXME: What new port features do we need to support? */ 1538 temp = xhci_port_state_to_neutral(temp); 1539 switch (wValue) { 1540 case USB_PORT_FEAT_SUSPEND: 1541 temp = readl(ports[wIndex]->addr); 1542 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n"); 1543 xhci_dbg(xhci, "PORTSC %04x\n", temp); 1544 if (temp & PORT_RESET) 1545 goto error; 1546 if ((temp & PORT_PLS_MASK) == XDEV_U3) { 1547 if ((temp & PORT_PE) == 0) 1548 goto error; 1549 1550 set_bit(wIndex, &bus_state->resuming_ports); 1551 usb_hcd_start_port_resume(&hcd->self, wIndex); 1552 xhci_set_link_state(xhci, ports[wIndex], 1553 XDEV_RESUME); 1554 spin_unlock_irqrestore(&xhci->lock, flags); 1555 msleep(USB_RESUME_TIMEOUT); 1556 spin_lock_irqsave(&xhci->lock, flags); 1557 xhci_set_link_state(xhci, ports[wIndex], 1558 XDEV_U0); 1559 clear_bit(wIndex, &bus_state->resuming_ports); 1560 usb_hcd_end_port_resume(&hcd->self, wIndex); 1561 } 1562 bus_state->port_c_suspend |= 1 << wIndex; 1563 1564 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 1565 wIndex + 1); 1566 if (!slot_id) { 1567 xhci_dbg(xhci, "slot_id is zero\n"); 1568 goto error; 1569 } 1570 xhci_ring_device(xhci, slot_id); 1571 break; 1572 case USB_PORT_FEAT_C_SUSPEND: 1573 bus_state->port_c_suspend &= ~(1 << wIndex); 1574 fallthrough; 1575 case USB_PORT_FEAT_C_RESET: 1576 case USB_PORT_FEAT_C_BH_PORT_RESET: 1577 case USB_PORT_FEAT_C_CONNECTION: 1578 case USB_PORT_FEAT_C_OVER_CURRENT: 1579 case USB_PORT_FEAT_C_ENABLE: 1580 case USB_PORT_FEAT_C_PORT_LINK_STATE: 1581 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR: 1582 xhci_clear_port_change_bit(xhci, wValue, wIndex, 1583 ports[wIndex]->addr, temp); 1584 break; 1585 case USB_PORT_FEAT_ENABLE: 1586 xhci_disable_port(hcd, xhci, wIndex, 1587 ports[wIndex]->addr, temp); 1588 break; 1589 case USB_PORT_FEAT_POWER: 1590 xhci_set_port_power(xhci, hcd, wIndex, false, &flags); 1591 break; 1592 case USB_PORT_FEAT_TEST: 1593 retval = xhci_exit_test_mode(xhci); 1594 break; 1595 default: 1596 goto error; 1597 } 1598 break; 1599 default: 1600 error: 1601 /* "stall" on error */ 1602 retval = -EPIPE; 1603 } 1604 spin_unlock_irqrestore(&xhci->lock, flags); 1605 return retval; 1606 } 1607 1608 /* 1609 * Returns 0 if the status hasn't changed, or the number of bytes in buf. 1610 * Ports are 0-indexed from the HCD point of view, 1611 * and 1-indexed from the USB core pointer of view. 1612 * 1613 * Note that the status change bits will be cleared as soon as a port status 1614 * change event is generated, so we use the saved status from that event. 1615 */ 1616 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf) 1617 { 1618 unsigned long flags; 1619 u32 temp, status; 1620 u32 mask; 1621 int i, retval; 1622 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1623 int max_ports; 1624 struct xhci_bus_state *bus_state; 1625 bool reset_change = false; 1626 struct xhci_hub *rhub; 1627 struct xhci_port **ports; 1628 1629 rhub = xhci_get_rhub(hcd); 1630 ports = rhub->ports; 1631 max_ports = rhub->num_ports; 1632 bus_state = &rhub->bus_state; 1633 1634 /* Initial status is no changes */ 1635 retval = (max_ports + 8) / 8; 1636 memset(buf, 0, retval); 1637 1638 /* 1639 * Inform the usbcore about resume-in-progress by returning 1640 * a non-zero value even if there are no status changes. 1641 */ 1642 spin_lock_irqsave(&xhci->lock, flags); 1643 1644 status = bus_state->resuming_ports; 1645 1646 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC; 1647 1648 /* For each port, did anything change? If so, set that bit in buf. */ 1649 for (i = 0; i < max_ports; i++) { 1650 temp = readl(ports[i]->addr); 1651 if (temp == ~(u32)0) { 1652 xhci_hc_died(xhci); 1653 retval = -ENODEV; 1654 break; 1655 } 1656 trace_xhci_hub_status_data(i, temp); 1657 1658 if ((temp & mask) != 0 || 1659 (bus_state->port_c_suspend & 1 << i) || 1660 (bus_state->resume_done[i] && time_after_eq( 1661 jiffies, bus_state->resume_done[i]))) { 1662 buf[(i + 1) / 8] |= 1 << (i + 1) % 8; 1663 status = 1; 1664 } 1665 if ((temp & PORT_RC)) 1666 reset_change = true; 1667 if (temp & PORT_OC) 1668 status = 1; 1669 } 1670 if (!status && !reset_change) { 1671 xhci_dbg(xhci, "%s: stopping usb%d port polling\n", 1672 __func__, hcd->self.busnum); 1673 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); 1674 } 1675 spin_unlock_irqrestore(&xhci->lock, flags); 1676 return status ? retval : 0; 1677 } 1678 1679 #ifdef CONFIG_PM 1680 1681 int xhci_bus_suspend(struct usb_hcd *hcd) 1682 { 1683 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1684 int max_ports, port_index; 1685 struct xhci_bus_state *bus_state; 1686 unsigned long flags; 1687 struct xhci_hub *rhub; 1688 struct xhci_port **ports; 1689 u32 portsc_buf[USB_MAXCHILDREN]; 1690 bool wake_enabled; 1691 1692 rhub = xhci_get_rhub(hcd); 1693 ports = rhub->ports; 1694 max_ports = rhub->num_ports; 1695 bus_state = &rhub->bus_state; 1696 wake_enabled = hcd->self.root_hub->do_remote_wakeup; 1697 1698 spin_lock_irqsave(&xhci->lock, flags); 1699 1700 if (wake_enabled) { 1701 if (bus_state->resuming_ports || /* USB2 */ 1702 bus_state->port_remote_wakeup) { /* USB3 */ 1703 spin_unlock_irqrestore(&xhci->lock, flags); 1704 xhci_dbg(xhci, "usb%d bus suspend to fail because a port is resuming\n", 1705 hcd->self.busnum); 1706 return -EBUSY; 1707 } 1708 } 1709 /* 1710 * Prepare ports for suspend, but don't write anything before all ports 1711 * are checked and we know bus suspend can proceed 1712 */ 1713 bus_state->bus_suspended = 0; 1714 port_index = max_ports; 1715 while (port_index--) { 1716 u32 t1, t2; 1717 int retries = 10; 1718 retry: 1719 t1 = readl(ports[port_index]->addr); 1720 t2 = xhci_port_state_to_neutral(t1); 1721 portsc_buf[port_index] = 0; 1722 1723 /* 1724 * Give a USB3 port in link training time to finish, but don't 1725 * prevent suspend as port might be stuck 1726 */ 1727 if ((hcd->speed >= HCD_USB3) && retries-- && 1728 (t1 & PORT_PLS_MASK) == XDEV_POLLING) { 1729 spin_unlock_irqrestore(&xhci->lock, flags); 1730 msleep(XHCI_PORT_POLLING_LFPS_TIME); 1731 spin_lock_irqsave(&xhci->lock, flags); 1732 xhci_dbg(xhci, "port %d-%d polling in bus suspend, waiting\n", 1733 hcd->self.busnum, port_index + 1); 1734 goto retry; 1735 } 1736 /* bail out if port detected a over-current condition */ 1737 if (t1 & PORT_OC) { 1738 bus_state->bus_suspended = 0; 1739 spin_unlock_irqrestore(&xhci->lock, flags); 1740 xhci_dbg(xhci, "Bus suspend bailout, port over-current detected\n"); 1741 return -EBUSY; 1742 } 1743 /* suspend ports in U0, or bail out for new connect changes */ 1744 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) { 1745 if ((t1 & PORT_CSC) && wake_enabled) { 1746 bus_state->bus_suspended = 0; 1747 spin_unlock_irqrestore(&xhci->lock, flags); 1748 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n"); 1749 return -EBUSY; 1750 } 1751 xhci_dbg(xhci, "port %d-%d not suspended\n", 1752 hcd->self.busnum, port_index + 1); 1753 t2 &= ~PORT_PLS_MASK; 1754 t2 |= PORT_LINK_STROBE | XDEV_U3; 1755 set_bit(port_index, &bus_state->bus_suspended); 1756 } 1757 /* USB core sets remote wake mask for USB 3.0 hubs, 1758 * including the USB 3.0 roothub, but only if CONFIG_PM 1759 * is enabled, so also enable remote wake here. 1760 */ 1761 if (wake_enabled) { 1762 if (t1 & PORT_CONNECT) { 1763 t2 |= PORT_WKOC_E | PORT_WKDISC_E; 1764 t2 &= ~PORT_WKCONN_E; 1765 } else { 1766 t2 |= PORT_WKOC_E | PORT_WKCONN_E; 1767 t2 &= ~PORT_WKDISC_E; 1768 } 1769 1770 if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) && 1771 (hcd->speed < HCD_USB3)) { 1772 if (usb_amd_pt_check_port(hcd->self.controller, 1773 port_index)) 1774 t2 &= ~PORT_WAKE_BITS; 1775 } 1776 } else 1777 t2 &= ~PORT_WAKE_BITS; 1778 1779 t1 = xhci_port_state_to_neutral(t1); 1780 if (t1 != t2) 1781 portsc_buf[port_index] = t2; 1782 } 1783 1784 /* write port settings, stopping and suspending ports if needed */ 1785 port_index = max_ports; 1786 while (port_index--) { 1787 if (!portsc_buf[port_index]) 1788 continue; 1789 if (test_bit(port_index, &bus_state->bus_suspended)) { 1790 int slot_id; 1791 1792 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 1793 port_index + 1); 1794 if (slot_id) { 1795 spin_unlock_irqrestore(&xhci->lock, flags); 1796 xhci_stop_device(xhci, slot_id, 1); 1797 spin_lock_irqsave(&xhci->lock, flags); 1798 } 1799 } 1800 writel(portsc_buf[port_index], ports[port_index]->addr); 1801 } 1802 hcd->state = HC_STATE_SUSPENDED; 1803 bus_state->next_statechange = jiffies + msecs_to_jiffies(10); 1804 spin_unlock_irqrestore(&xhci->lock, flags); 1805 1806 if (bus_state->bus_suspended) 1807 usleep_range(5000, 10000); 1808 1809 return 0; 1810 } 1811 1812 /* 1813 * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3. 1814 * warm reset a USB3 device stuck in polling or compliance mode after resume. 1815 * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8 1816 */ 1817 static bool xhci_port_missing_cas_quirk(struct xhci_port *port) 1818 { 1819 u32 portsc; 1820 1821 portsc = readl(port->addr); 1822 1823 /* if any of these are set we are not stuck */ 1824 if (portsc & (PORT_CONNECT | PORT_CAS)) 1825 return false; 1826 1827 if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) && 1828 ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE)) 1829 return false; 1830 1831 /* clear wakeup/change bits, and do a warm port reset */ 1832 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); 1833 portsc |= PORT_WR; 1834 writel(portsc, port->addr); 1835 /* flush write */ 1836 readl(port->addr); 1837 return true; 1838 } 1839 1840 int xhci_bus_resume(struct usb_hcd *hcd) 1841 { 1842 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1843 struct xhci_bus_state *bus_state; 1844 unsigned long flags; 1845 int max_ports, port_index; 1846 int slot_id; 1847 int sret; 1848 u32 next_state; 1849 u32 temp, portsc; 1850 struct xhci_hub *rhub; 1851 struct xhci_port **ports; 1852 1853 rhub = xhci_get_rhub(hcd); 1854 ports = rhub->ports; 1855 max_ports = rhub->num_ports; 1856 bus_state = &rhub->bus_state; 1857 1858 if (time_before(jiffies, bus_state->next_statechange)) 1859 msleep(5); 1860 1861 spin_lock_irqsave(&xhci->lock, flags); 1862 if (!HCD_HW_ACCESSIBLE(hcd)) { 1863 spin_unlock_irqrestore(&xhci->lock, flags); 1864 return -ESHUTDOWN; 1865 } 1866 1867 /* delay the irqs */ 1868 temp = readl(&xhci->op_regs->command); 1869 temp &= ~CMD_EIE; 1870 writel(temp, &xhci->op_regs->command); 1871 1872 /* bus specific resume for ports we suspended at bus_suspend */ 1873 if (hcd->speed >= HCD_USB3) 1874 next_state = XDEV_U0; 1875 else 1876 next_state = XDEV_RESUME; 1877 1878 port_index = max_ports; 1879 while (port_index--) { 1880 portsc = readl(ports[port_index]->addr); 1881 1882 /* warm reset CAS limited ports stuck in polling/compliance */ 1883 if ((xhci->quirks & XHCI_MISSING_CAS) && 1884 (hcd->speed >= HCD_USB3) && 1885 xhci_port_missing_cas_quirk(ports[port_index])) { 1886 xhci_dbg(xhci, "reset stuck port %d-%d\n", 1887 hcd->self.busnum, port_index + 1); 1888 clear_bit(port_index, &bus_state->bus_suspended); 1889 continue; 1890 } 1891 /* resume if we suspended the link, and it is still suspended */ 1892 if (test_bit(port_index, &bus_state->bus_suspended)) 1893 switch (portsc & PORT_PLS_MASK) { 1894 case XDEV_U3: 1895 portsc = xhci_port_state_to_neutral(portsc); 1896 portsc &= ~PORT_PLS_MASK; 1897 portsc |= PORT_LINK_STROBE | next_state; 1898 break; 1899 case XDEV_RESUME: 1900 /* resume already initiated */ 1901 break; 1902 default: 1903 /* not in a resumeable state, ignore it */ 1904 clear_bit(port_index, 1905 &bus_state->bus_suspended); 1906 break; 1907 } 1908 /* disable wake for all ports, write new link state if needed */ 1909 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); 1910 writel(portsc, ports[port_index]->addr); 1911 } 1912 1913 /* USB2 specific resume signaling delay and U0 link state transition */ 1914 if (hcd->speed < HCD_USB3) { 1915 if (bus_state->bus_suspended) { 1916 spin_unlock_irqrestore(&xhci->lock, flags); 1917 msleep(USB_RESUME_TIMEOUT); 1918 spin_lock_irqsave(&xhci->lock, flags); 1919 } 1920 for_each_set_bit(port_index, &bus_state->bus_suspended, 1921 BITS_PER_LONG) { 1922 /* Clear PLC to poll it later for U0 transition */ 1923 xhci_test_and_clear_bit(xhci, ports[port_index], 1924 PORT_PLC); 1925 xhci_set_link_state(xhci, ports[port_index], XDEV_U0); 1926 } 1927 } 1928 1929 /* poll for U0 link state complete, both USB2 and USB3 */ 1930 for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) { 1931 sret = xhci_handshake(ports[port_index]->addr, PORT_PLC, 1932 PORT_PLC, 10 * 1000); 1933 if (sret) { 1934 xhci_warn(xhci, "port %d-%d resume PLC timeout\n", 1935 hcd->self.busnum, port_index + 1); 1936 continue; 1937 } 1938 xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC); 1939 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1); 1940 if (slot_id) 1941 xhci_ring_device(xhci, slot_id); 1942 } 1943 (void) readl(&xhci->op_regs->command); 1944 1945 bus_state->next_statechange = jiffies + msecs_to_jiffies(5); 1946 /* re-enable irqs */ 1947 temp = readl(&xhci->op_regs->command); 1948 temp |= CMD_EIE; 1949 writel(temp, &xhci->op_regs->command); 1950 temp = readl(&xhci->op_regs->command); 1951 1952 spin_unlock_irqrestore(&xhci->lock, flags); 1953 return 0; 1954 } 1955 1956 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd) 1957 { 1958 struct xhci_hub *rhub = xhci_get_rhub(hcd); 1959 1960 /* USB3 port wakeups are reported via usb_wakeup_notification() */ 1961 return rhub->bus_state.resuming_ports; /* USB2 ports only */ 1962 } 1963 1964 #endif /* CONFIG_PM */ 1965