1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 12 #include <linux/slab.h> 13 #include <asm/unaligned.h> 14 #include <linux/bitfield.h> 15 16 #include "xhci.h" 17 #include "xhci-trace.h" 18 19 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) 20 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ 21 PORT_RC | PORT_PLC | PORT_PE) 22 23 /* Default sublink speed attribute of each lane */ 24 static u32 ssp_cap_default_ssa[] = { 25 0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */ 26 0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */ 27 0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */ 28 0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */ 29 0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */ 30 0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */ 31 0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */ 32 0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */ 33 }; 34 35 static int xhci_create_usb3x_bos_desc(struct xhci_hcd *xhci, char *buf, 36 u16 wLength) 37 { 38 struct usb_bos_descriptor *bos; 39 struct usb_ss_cap_descriptor *ss_cap; 40 struct usb_ssp_cap_descriptor *ssp_cap; 41 struct xhci_port_cap *port_cap = NULL; 42 u16 bcdUSB; 43 u32 reg; 44 u32 min_rate = 0; 45 u8 min_ssid; 46 u8 ssac; 47 u8 ssic; 48 int offset; 49 int i; 50 51 /* BOS descriptor */ 52 bos = (struct usb_bos_descriptor *)buf; 53 bos->bLength = USB_DT_BOS_SIZE; 54 bos->bDescriptorType = USB_DT_BOS; 55 bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE + 56 USB_DT_USB_SS_CAP_SIZE); 57 bos->bNumDeviceCaps = 1; 58 59 /* Create the descriptor for port with the highest revision */ 60 for (i = 0; i < xhci->num_port_caps; i++) { 61 u8 major = xhci->port_caps[i].maj_rev; 62 u8 minor = xhci->port_caps[i].min_rev; 63 u16 rev = (major << 8) | minor; 64 65 if (i == 0 || bcdUSB < rev) { 66 bcdUSB = rev; 67 port_cap = &xhci->port_caps[i]; 68 } 69 } 70 71 if (bcdUSB >= 0x0310) { 72 if (port_cap->psi_count) { 73 u8 num_sym_ssa = 0; 74 75 for (i = 0; i < port_cap->psi_count; i++) { 76 if ((port_cap->psi[i] & PLT_MASK) == PLT_SYM) 77 num_sym_ssa++; 78 } 79 80 ssac = port_cap->psi_count + num_sym_ssa - 1; 81 ssic = port_cap->psi_uid_count - 1; 82 } else { 83 if (bcdUSB >= 0x0320) 84 ssac = 7; 85 else 86 ssac = 3; 87 88 ssic = (ssac + 1) / 2 - 1; 89 } 90 91 bos->bNumDeviceCaps++; 92 bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE + 93 USB_DT_USB_SS_CAP_SIZE + 94 USB_DT_USB_SSP_CAP_SIZE(ssac)); 95 } 96 97 if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE) 98 return wLength; 99 100 /* SuperSpeed USB Device Capability */ 101 ss_cap = (struct usb_ss_cap_descriptor *)&buf[USB_DT_BOS_SIZE]; 102 ss_cap->bLength = USB_DT_USB_SS_CAP_SIZE; 103 ss_cap->bDescriptorType = USB_DT_DEVICE_CAPABILITY; 104 ss_cap->bDevCapabilityType = USB_SS_CAP_TYPE; 105 ss_cap->bmAttributes = 0; /* set later */ 106 ss_cap->wSpeedSupported = cpu_to_le16(USB_5GBPS_OPERATION); 107 ss_cap->bFunctionalitySupport = USB_LOW_SPEED_OPERATION; 108 ss_cap->bU1devExitLat = 0; /* set later */ 109 ss_cap->bU2DevExitLat = 0; /* set later */ 110 111 reg = readl(&xhci->cap_regs->hcc_params); 112 if (HCC_LTC(reg)) 113 ss_cap->bmAttributes |= USB_LTM_SUPPORT; 114 115 if ((xhci->quirks & XHCI_LPM_SUPPORT)) { 116 reg = readl(&xhci->cap_regs->hcs_params3); 117 ss_cap->bU1devExitLat = HCS_U1_LATENCY(reg); 118 ss_cap->bU2DevExitLat = cpu_to_le16(HCS_U2_LATENCY(reg)); 119 } 120 121 if (wLength < le16_to_cpu(bos->wTotalLength)) 122 return wLength; 123 124 if (bcdUSB < 0x0310) 125 return le16_to_cpu(bos->wTotalLength); 126 127 ssp_cap = (struct usb_ssp_cap_descriptor *)&buf[USB_DT_BOS_SIZE + 128 USB_DT_USB_SS_CAP_SIZE]; 129 ssp_cap->bLength = USB_DT_USB_SSP_CAP_SIZE(ssac); 130 ssp_cap->bDescriptorType = USB_DT_DEVICE_CAPABILITY; 131 ssp_cap->bDevCapabilityType = USB_SSP_CAP_TYPE; 132 ssp_cap->bReserved = 0; 133 ssp_cap->wReserved = 0; 134 ssp_cap->bmAttributes = 135 cpu_to_le32(FIELD_PREP(USB_SSP_SUBLINK_SPEED_ATTRIBS, ssac) | 136 FIELD_PREP(USB_SSP_SUBLINK_SPEED_IDS, ssic)); 137 138 if (!port_cap->psi_count) { 139 for (i = 0; i < ssac + 1; i++) 140 ssp_cap->bmSublinkSpeedAttr[i] = 141 cpu_to_le32(ssp_cap_default_ssa[i]); 142 143 min_ssid = 4; 144 goto out; 145 } 146 147 offset = 0; 148 for (i = 0; i < port_cap->psi_count; i++) { 149 u32 psi; 150 u32 attr; 151 u8 ssid; 152 u8 lp; 153 u8 lse; 154 u8 psie; 155 u16 lane_mantissa; 156 u16 psim; 157 u16 plt; 158 159 psi = port_cap->psi[i]; 160 ssid = XHCI_EXT_PORT_PSIV(psi); 161 lp = XHCI_EXT_PORT_LP(psi); 162 psie = XHCI_EXT_PORT_PSIE(psi); 163 psim = XHCI_EXT_PORT_PSIM(psi); 164 plt = psi & PLT_MASK; 165 166 lse = psie; 167 lane_mantissa = psim; 168 169 /* Shift to Gbps and set SSP Link Protocol if 10Gpbs */ 170 for (; psie < USB_SSP_SUBLINK_SPEED_LSE_GBPS; psie++) 171 psim /= 1000; 172 173 if (!min_rate || psim < min_rate) { 174 min_ssid = ssid; 175 min_rate = psim; 176 } 177 178 /* Some host controllers don't set the link protocol for SSP */ 179 if (psim >= 10) 180 lp = USB_SSP_SUBLINK_SPEED_LP_SSP; 181 182 /* 183 * PSIM and PSIE represent the total speed of PSI. The BOS 184 * descriptor SSP sublink speed attribute lane mantissa 185 * describes the lane speed. E.g. PSIM and PSIE for gen2x2 186 * is 20Gbps, but the BOS descriptor lane speed mantissa is 187 * 10Gbps. Check and modify the mantissa value to match the 188 * lane speed. 189 */ 190 if (bcdUSB == 0x0320 && plt == PLT_SYM) { 191 /* 192 * The PSI dword for gen1x2 and gen2x1 share the same 193 * values. But the lane speed for gen1x2 is 5Gbps while 194 * gen2x1 is 10Gbps. If the previous PSI dword SSID is 195 * 5 and the PSIE and PSIM match with SSID 6, let's 196 * assume that the controller follows the default speed 197 * id with SSID 6 for gen1x2. 198 */ 199 if (ssid == 6 && psie == 3 && psim == 10 && i) { 200 u32 prev = port_cap->psi[i - 1]; 201 202 if ((prev & PLT_MASK) == PLT_SYM && 203 XHCI_EXT_PORT_PSIV(prev) == 5 && 204 XHCI_EXT_PORT_PSIE(prev) == 3 && 205 XHCI_EXT_PORT_PSIM(prev) == 10) { 206 lse = USB_SSP_SUBLINK_SPEED_LSE_GBPS; 207 lane_mantissa = 5; 208 } 209 } 210 211 if (psie == 3 && psim > 10) { 212 lse = USB_SSP_SUBLINK_SPEED_LSE_GBPS; 213 lane_mantissa = 10; 214 } 215 } 216 217 attr = (FIELD_PREP(USB_SSP_SUBLINK_SPEED_SSID, ssid) | 218 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LP, lp) | 219 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSE, lse) | 220 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSM, lane_mantissa)); 221 222 switch (plt) { 223 case PLT_SYM: 224 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST, 225 USB_SSP_SUBLINK_SPEED_ST_SYM_RX); 226 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr); 227 228 attr &= ~USB_SSP_SUBLINK_SPEED_ST; 229 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST, 230 USB_SSP_SUBLINK_SPEED_ST_SYM_TX); 231 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr); 232 break; 233 case PLT_ASYM_RX: 234 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST, 235 USB_SSP_SUBLINK_SPEED_ST_ASYM_RX); 236 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr); 237 break; 238 case PLT_ASYM_TX: 239 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST, 240 USB_SSP_SUBLINK_SPEED_ST_ASYM_TX); 241 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr); 242 break; 243 } 244 } 245 out: 246 ssp_cap->wFunctionalitySupport = 247 cpu_to_le16(FIELD_PREP(USB_SSP_MIN_SUBLINK_SPEED_ATTRIBUTE_ID, 248 min_ssid) | 249 FIELD_PREP(USB_SSP_MIN_RX_LANE_COUNT, 1) | 250 FIELD_PREP(USB_SSP_MIN_TX_LANE_COUNT, 1)); 251 252 return le16_to_cpu(bos->wTotalLength); 253 } 254 255 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci, 256 struct usb_hub_descriptor *desc, int ports) 257 { 258 u16 temp; 259 260 desc->bHubContrCurrent = 0; 261 262 desc->bNbrPorts = ports; 263 temp = 0; 264 /* Bits 1:0 - support per-port power switching, or power always on */ 265 if (HCC_PPC(xhci->hcc_params)) 266 temp |= HUB_CHAR_INDV_PORT_LPSM; 267 else 268 temp |= HUB_CHAR_NO_LPSM; 269 /* Bit 2 - root hubs are not part of a compound device */ 270 /* Bits 4:3 - individual port over current protection */ 271 temp |= HUB_CHAR_INDV_PORT_OCPM; 272 /* Bits 6:5 - no TTs in root ports */ 273 /* Bit 7 - no port indicators */ 274 desc->wHubCharacteristics = cpu_to_le16(temp); 275 } 276 277 /* Fill in the USB 2.0 roothub descriptor */ 278 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 279 struct usb_hub_descriptor *desc) 280 { 281 int ports; 282 u16 temp; 283 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8]; 284 u32 portsc; 285 unsigned int i; 286 struct xhci_hub *rhub; 287 288 rhub = &xhci->usb2_rhub; 289 ports = rhub->num_ports; 290 xhci_common_hub_descriptor(xhci, desc, ports); 291 desc->bDescriptorType = USB_DT_HUB; 292 temp = 1 + (ports / 8); 293 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; 294 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.8 says 20ms */ 295 296 /* The Device Removable bits are reported on a byte granularity. 297 * If the port doesn't exist within that byte, the bit is set to 0. 298 */ 299 memset(port_removable, 0, sizeof(port_removable)); 300 for (i = 0; i < ports; i++) { 301 portsc = readl(rhub->ports[i]->addr); 302 /* If a device is removable, PORTSC reports a 0, same as in the 303 * hub descriptor DeviceRemovable bits. 304 */ 305 if (portsc & PORT_DEV_REMOVE) 306 /* This math is hairy because bit 0 of DeviceRemovable 307 * is reserved, and bit 1 is for port 1, etc. 308 */ 309 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8); 310 } 311 312 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN 313 * ports on it. The USB 2.0 specification says that there are two 314 * variable length fields at the end of the hub descriptor: 315 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than 316 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array 317 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to 318 * 0xFF, so we initialize the both arrays (DeviceRemovable and 319 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each 320 * set of ports that actually exist. 321 */ 322 memset(desc->u.hs.DeviceRemovable, 0xff, 323 sizeof(desc->u.hs.DeviceRemovable)); 324 memset(desc->u.hs.PortPwrCtrlMask, 0xff, 325 sizeof(desc->u.hs.PortPwrCtrlMask)); 326 327 for (i = 0; i < (ports + 1 + 7) / 8; i++) 328 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i], 329 sizeof(__u8)); 330 } 331 332 /* Fill in the USB 3.0 roothub descriptor */ 333 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 334 struct usb_hub_descriptor *desc) 335 { 336 int ports; 337 u16 port_removable; 338 u32 portsc; 339 unsigned int i; 340 struct xhci_hub *rhub; 341 342 rhub = &xhci->usb3_rhub; 343 ports = rhub->num_ports; 344 xhci_common_hub_descriptor(xhci, desc, ports); 345 desc->bDescriptorType = USB_DT_SS_HUB; 346 desc->bDescLength = USB_DT_SS_HUB_SIZE; 347 desc->bPwrOn2PwrGood = 50; /* usb 3.1 may fail if less than 100ms */ 348 349 /* header decode latency should be zero for roothubs, 350 * see section 4.23.5.2. 351 */ 352 desc->u.ss.bHubHdrDecLat = 0; 353 desc->u.ss.wHubDelay = 0; 354 355 port_removable = 0; 356 /* bit 0 is reserved, bit 1 is for port 1, etc. */ 357 for (i = 0; i < ports; i++) { 358 portsc = readl(rhub->ports[i]->addr); 359 if (portsc & PORT_DEV_REMOVE) 360 port_removable |= 1 << (i + 1); 361 } 362 363 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable); 364 } 365 366 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 367 struct usb_hub_descriptor *desc) 368 { 369 370 if (hcd->speed >= HCD_USB3) 371 xhci_usb3_hub_descriptor(hcd, xhci, desc); 372 else 373 xhci_usb2_hub_descriptor(hcd, xhci, desc); 374 375 } 376 377 static unsigned int xhci_port_speed(unsigned int port_status) 378 { 379 if (DEV_LOWSPEED(port_status)) 380 return USB_PORT_STAT_LOW_SPEED; 381 if (DEV_HIGHSPEED(port_status)) 382 return USB_PORT_STAT_HIGH_SPEED; 383 /* 384 * FIXME: Yes, we should check for full speed, but the core uses that as 385 * a default in portspeed() in usb/core/hub.c (which is the only place 386 * USB_PORT_STAT_*_SPEED is used). 387 */ 388 return 0; 389 } 390 391 /* 392 * These bits are Read Only (RO) and should be saved and written to the 393 * registers: 0, 3, 10:13, 30 394 * connect status, over-current status, port speed, and device removable. 395 * connect status and port speed are also sticky - meaning they're in 396 * the AUX well and they aren't changed by a hot, warm, or cold reset. 397 */ 398 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30)) 399 /* 400 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: 401 * bits 5:8, 9, 14:15, 25:27 402 * link state, port power, port indicator state, "wake on" enable state 403 */ 404 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25)) 405 /* 406 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: 407 * bit 4 (port reset) 408 */ 409 #define XHCI_PORT_RW1S ((1<<4)) 410 /* 411 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: 412 * bits 1, 17, 18, 19, 20, 21, 22, 23 413 * port enable/disable, and 414 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports), 415 * over-current, reset, link state, and L1 change 416 */ 417 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17)) 418 /* 419 * Bit 16 is RW, and writing a '1' to it causes the link state control to be 420 * latched in 421 */ 422 #define XHCI_PORT_RW ((1<<16)) 423 /* 424 * These bits are Reserved Zero (RsvdZ) and zero should be written to them: 425 * bits 2, 24, 28:31 426 */ 427 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28)) 428 429 /** 430 * xhci_port_state_to_neutral() - Clean up read portsc value back into writeable 431 * @state: u32 port value read from portsc register to be cleanup up 432 * 433 * Given a port state, this function returns a value that would result in the 434 * port being in the same state, if the value was written to the port status 435 * control register. 436 * Save Read Only (RO) bits and save read/write bits where 437 * writing a 0 clears the bit and writing a 1 sets the bit (RWS). 438 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. 439 * 440 * Return: u32 value that can be written back to portsc register without 441 * changing port state. 442 */ 443 444 u32 xhci_port_state_to_neutral(u32 state) 445 { 446 /* Save read-only status and port state */ 447 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS); 448 } 449 EXPORT_SYMBOL_GPL(xhci_port_state_to_neutral); 450 451 /** 452 * xhci_find_slot_id_by_port() - Find slot id of a usb device on a roothub port 453 * @hcd: pointer to hcd of the roothub 454 * @xhci: pointer to xhci structure 455 * @port: one-based port number of the port in this roothub. 456 * 457 * Return: Slot id of the usb device connected to the root port, 0 if not found 458 */ 459 460 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 461 u16 port) 462 { 463 int slot_id; 464 int i; 465 enum usb_device_speed speed; 466 467 slot_id = 0; 468 for (i = 0; i < MAX_HC_SLOTS; i++) { 469 if (!xhci->devs[i] || !xhci->devs[i]->udev) 470 continue; 471 speed = xhci->devs[i]->udev->speed; 472 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3)) 473 && xhci->devs[i]->fake_port == port) { 474 slot_id = i; 475 break; 476 } 477 } 478 479 return slot_id; 480 } 481 EXPORT_SYMBOL_GPL(xhci_find_slot_id_by_port); 482 483 /* 484 * Stop device 485 * It issues stop endpoint command for EP 0 to 30. And wait the last command 486 * to complete. 487 * suspend will set to 1, if suspend bit need to set in command. 488 */ 489 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend) 490 { 491 struct xhci_virt_device *virt_dev; 492 struct xhci_command *cmd; 493 unsigned long flags; 494 int ret; 495 int i; 496 497 ret = 0; 498 virt_dev = xhci->devs[slot_id]; 499 if (!virt_dev) 500 return -ENODEV; 501 502 trace_xhci_stop_device(virt_dev); 503 504 cmd = xhci_alloc_command(xhci, true, GFP_NOIO); 505 if (!cmd) 506 return -ENOMEM; 507 508 spin_lock_irqsave(&xhci->lock, flags); 509 for (i = LAST_EP_INDEX; i > 0; i--) { 510 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) { 511 struct xhci_ep_ctx *ep_ctx; 512 struct xhci_command *command; 513 514 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i); 515 516 /* Check ep is running, required by AMD SNPS 3.1 xHC */ 517 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING) 518 continue; 519 520 command = xhci_alloc_command(xhci, false, GFP_NOWAIT); 521 if (!command) { 522 spin_unlock_irqrestore(&xhci->lock, flags); 523 ret = -ENOMEM; 524 goto cmd_cleanup; 525 } 526 527 ret = xhci_queue_stop_endpoint(xhci, command, slot_id, 528 i, suspend); 529 if (ret) { 530 spin_unlock_irqrestore(&xhci->lock, flags); 531 xhci_free_command(xhci, command); 532 goto cmd_cleanup; 533 } 534 } 535 } 536 ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend); 537 if (ret) { 538 spin_unlock_irqrestore(&xhci->lock, flags); 539 goto cmd_cleanup; 540 } 541 542 xhci_ring_cmd_db(xhci); 543 spin_unlock_irqrestore(&xhci->lock, flags); 544 545 /* Wait for last stop endpoint command to finish */ 546 wait_for_completion(cmd->completion); 547 548 if (cmd->status == COMP_COMMAND_ABORTED || 549 cmd->status == COMP_COMMAND_RING_STOPPED) { 550 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n"); 551 ret = -ETIME; 552 } 553 554 cmd_cleanup: 555 xhci_free_command(xhci, cmd); 556 return ret; 557 } 558 559 /* 560 * Ring device, it rings the all doorbells unconditionally. 561 */ 562 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id) 563 { 564 int i, s; 565 struct xhci_virt_ep *ep; 566 567 for (i = 0; i < LAST_EP_INDEX + 1; i++) { 568 ep = &xhci->devs[slot_id]->eps[i]; 569 570 if (ep->ep_state & EP_HAS_STREAMS) { 571 for (s = 1; s < ep->stream_info->num_streams; s++) 572 xhci_ring_ep_doorbell(xhci, slot_id, i, s); 573 } else if (ep->ring && ep->ring->dequeue) { 574 xhci_ring_ep_doorbell(xhci, slot_id, i, 0); 575 } 576 } 577 578 return; 579 } 580 581 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 582 u16 wIndex, __le32 __iomem *addr, u32 port_status) 583 { 584 /* Don't allow the USB core to disable SuperSpeed ports. */ 585 if (hcd->speed >= HCD_USB3) { 586 xhci_dbg(xhci, "Ignoring request to disable " 587 "SuperSpeed port.\n"); 588 return; 589 } 590 591 if (xhci->quirks & XHCI_BROKEN_PORT_PED) { 592 xhci_dbg(xhci, 593 "Broken Port Enabled/Disabled, ignoring port disable request.\n"); 594 return; 595 } 596 597 /* Write 1 to disable the port */ 598 writel(port_status | PORT_PE, addr); 599 port_status = readl(addr); 600 xhci_dbg(xhci, "disable port %d-%d, portsc: 0x%x\n", 601 hcd->self.busnum, wIndex + 1, port_status); 602 } 603 604 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, 605 u16 wIndex, __le32 __iomem *addr, u32 port_status) 606 { 607 char *port_change_bit; 608 u32 status; 609 610 switch (wValue) { 611 case USB_PORT_FEAT_C_RESET: 612 status = PORT_RC; 613 port_change_bit = "reset"; 614 break; 615 case USB_PORT_FEAT_C_BH_PORT_RESET: 616 status = PORT_WRC; 617 port_change_bit = "warm(BH) reset"; 618 break; 619 case USB_PORT_FEAT_C_CONNECTION: 620 status = PORT_CSC; 621 port_change_bit = "connect"; 622 break; 623 case USB_PORT_FEAT_C_OVER_CURRENT: 624 status = PORT_OCC; 625 port_change_bit = "over-current"; 626 break; 627 case USB_PORT_FEAT_C_ENABLE: 628 status = PORT_PEC; 629 port_change_bit = "enable/disable"; 630 break; 631 case USB_PORT_FEAT_C_SUSPEND: 632 status = PORT_PLC; 633 port_change_bit = "suspend/resume"; 634 break; 635 case USB_PORT_FEAT_C_PORT_LINK_STATE: 636 status = PORT_PLC; 637 port_change_bit = "link state"; 638 break; 639 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR: 640 status = PORT_CEC; 641 port_change_bit = "config error"; 642 break; 643 default: 644 /* Should never happen */ 645 return; 646 } 647 /* Change bits are all write 1 to clear */ 648 writel(port_status | status, addr); 649 port_status = readl(addr); 650 651 xhci_dbg(xhci, "clear port%d %s change, portsc: 0x%x\n", 652 wIndex + 1, port_change_bit, port_status); 653 } 654 655 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd) 656 { 657 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 658 659 if (hcd->speed >= HCD_USB3) 660 return &xhci->usb3_rhub; 661 return &xhci->usb2_rhub; 662 } 663 664 /* 665 * xhci_set_port_power() must be called with xhci->lock held. 666 * It will release and re-aquire the lock while calling ACPI 667 * method. 668 */ 669 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd, 670 u16 index, bool on, unsigned long *flags) 671 __must_hold(&xhci->lock) 672 { 673 struct xhci_hub *rhub; 674 struct xhci_port *port; 675 u32 temp; 676 677 rhub = xhci_get_rhub(hcd); 678 port = rhub->ports[index]; 679 temp = readl(port->addr); 680 681 xhci_dbg(xhci, "set port power %d-%d %s, portsc: 0x%x\n", 682 hcd->self.busnum, index + 1, on ? "ON" : "OFF", temp); 683 684 temp = xhci_port_state_to_neutral(temp); 685 686 if (on) { 687 /* Power on */ 688 writel(temp | PORT_POWER, port->addr); 689 readl(port->addr); 690 } else { 691 /* Power off */ 692 writel(temp & ~PORT_POWER, port->addr); 693 } 694 695 spin_unlock_irqrestore(&xhci->lock, *flags); 696 temp = usb_acpi_power_manageable(hcd->self.root_hub, 697 index); 698 if (temp) 699 usb_acpi_set_power_state(hcd->self.root_hub, 700 index, on); 701 spin_lock_irqsave(&xhci->lock, *flags); 702 } 703 704 static void xhci_port_set_test_mode(struct xhci_hcd *xhci, 705 u16 test_mode, u16 wIndex) 706 { 707 u32 temp; 708 struct xhci_port *port; 709 710 /* xhci only supports test mode for usb2 ports */ 711 port = xhci->usb2_rhub.ports[wIndex]; 712 temp = readl(port->addr + PORTPMSC); 713 temp |= test_mode << PORT_TEST_MODE_SHIFT; 714 writel(temp, port->addr + PORTPMSC); 715 xhci->test_mode = test_mode; 716 if (test_mode == USB_TEST_FORCE_ENABLE) 717 xhci_start(xhci); 718 } 719 720 static int xhci_enter_test_mode(struct xhci_hcd *xhci, 721 u16 test_mode, u16 wIndex, unsigned long *flags) 722 __must_hold(&xhci->lock) 723 { 724 struct usb_hcd *usb3_hcd = xhci_get_usb3_hcd(xhci); 725 int i, retval; 726 727 /* Disable all Device Slots */ 728 xhci_dbg(xhci, "Disable all slots\n"); 729 spin_unlock_irqrestore(&xhci->lock, *flags); 730 for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) { 731 if (!xhci->devs[i]) 732 continue; 733 734 retval = xhci_disable_slot(xhci, i); 735 xhci_free_virt_device(xhci, i); 736 if (retval) 737 xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n", 738 i, retval); 739 } 740 spin_lock_irqsave(&xhci->lock, *flags); 741 /* Put all ports to the Disable state by clear PP */ 742 xhci_dbg(xhci, "Disable all port (PP = 0)\n"); 743 /* Power off USB3 ports*/ 744 for (i = 0; i < xhci->usb3_rhub.num_ports; i++) 745 xhci_set_port_power(xhci, usb3_hcd, i, false, flags); 746 /* Power off USB2 ports*/ 747 for (i = 0; i < xhci->usb2_rhub.num_ports; i++) 748 xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags); 749 /* Stop the controller */ 750 xhci_dbg(xhci, "Stop controller\n"); 751 retval = xhci_halt(xhci); 752 if (retval) 753 return retval; 754 /* Disable runtime PM for test mode */ 755 pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller); 756 /* Set PORTPMSC.PTC field to enter selected test mode */ 757 /* Port is selected by wIndex. port_id = wIndex + 1 */ 758 xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n", 759 test_mode, wIndex + 1); 760 xhci_port_set_test_mode(xhci, test_mode, wIndex); 761 return retval; 762 } 763 764 static int xhci_exit_test_mode(struct xhci_hcd *xhci) 765 { 766 int retval; 767 768 if (!xhci->test_mode) { 769 xhci_err(xhci, "Not in test mode, do nothing.\n"); 770 return 0; 771 } 772 if (xhci->test_mode == USB_TEST_FORCE_ENABLE && 773 !(xhci->xhc_state & XHCI_STATE_HALTED)) { 774 retval = xhci_halt(xhci); 775 if (retval) 776 return retval; 777 } 778 pm_runtime_allow(xhci_to_hcd(xhci)->self.controller); 779 xhci->test_mode = 0; 780 return xhci_reset(xhci, XHCI_RESET_SHORT_USEC); 781 } 782 783 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port, 784 u32 link_state) 785 { 786 u32 temp; 787 u32 portsc; 788 789 portsc = readl(port->addr); 790 temp = xhci_port_state_to_neutral(portsc); 791 temp &= ~PORT_PLS_MASK; 792 temp |= PORT_LINK_STROBE | link_state; 793 writel(temp, port->addr); 794 795 xhci_dbg(xhci, "Set port %d-%d link state, portsc: 0x%x, write 0x%x", 796 port->rhub->hcd->self.busnum, port->hcd_portnum + 1, 797 portsc, temp); 798 } 799 800 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci, 801 struct xhci_port *port, u16 wake_mask) 802 { 803 u32 temp; 804 805 temp = readl(port->addr); 806 temp = xhci_port_state_to_neutral(temp); 807 808 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT) 809 temp |= PORT_WKCONN_E; 810 else 811 temp &= ~PORT_WKCONN_E; 812 813 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT) 814 temp |= PORT_WKDISC_E; 815 else 816 temp &= ~PORT_WKDISC_E; 817 818 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT) 819 temp |= PORT_WKOC_E; 820 else 821 temp &= ~PORT_WKOC_E; 822 823 writel(temp, port->addr); 824 } 825 826 /* Test and clear port RWC bit */ 827 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port, 828 u32 port_bit) 829 { 830 u32 temp; 831 832 temp = readl(port->addr); 833 if (temp & port_bit) { 834 temp = xhci_port_state_to_neutral(temp); 835 temp |= port_bit; 836 writel(temp, port->addr); 837 } 838 } 839 840 /* Updates Link Status for super Speed port */ 841 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci, 842 u32 *status, u32 status_reg) 843 { 844 u32 pls = status_reg & PORT_PLS_MASK; 845 846 /* When the CAS bit is set then warm reset 847 * should be performed on port 848 */ 849 if (status_reg & PORT_CAS) { 850 /* The CAS bit can be set while the port is 851 * in any link state. 852 * Only roothubs have CAS bit, so we 853 * pretend to be in compliance mode 854 * unless we're already in compliance 855 * or the inactive state. 856 */ 857 if (pls != USB_SS_PORT_LS_COMP_MOD && 858 pls != USB_SS_PORT_LS_SS_INACTIVE) { 859 pls = USB_SS_PORT_LS_COMP_MOD; 860 } 861 /* Return also connection bit - 862 * hub state machine resets port 863 * when this bit is set. 864 */ 865 pls |= USB_PORT_STAT_CONNECTION; 866 } else { 867 /* 868 * Resume state is an xHCI internal state. Do not report it to 869 * usb core, instead, pretend to be U3, thus usb core knows 870 * it's not ready for transfer. 871 */ 872 if (pls == XDEV_RESUME) { 873 *status |= USB_SS_PORT_LS_U3; 874 return; 875 } 876 877 /* 878 * If CAS bit isn't set but the Port is already at 879 * Compliance Mode, fake a connection so the USB core 880 * notices the Compliance state and resets the port. 881 * This resolves an issue generated by the SN65LVPE502CP 882 * in which sometimes the port enters compliance mode 883 * caused by a delay on the host-device negotiation. 884 */ 885 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && 886 (pls == USB_SS_PORT_LS_COMP_MOD)) 887 pls |= USB_PORT_STAT_CONNECTION; 888 } 889 890 /* update status field */ 891 *status |= pls; 892 } 893 894 /* 895 * Function for Compliance Mode Quirk. 896 * 897 * This Function verifies if all xhc USB3 ports have entered U0, if so, 898 * the compliance mode timer is deleted. A port won't enter 899 * compliance mode if it has previously entered U0. 900 */ 901 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, 902 u16 wIndex) 903 { 904 u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1); 905 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0); 906 907 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK)) 908 return; 909 910 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) { 911 xhci->port_status_u0 |= 1 << wIndex; 912 if (xhci->port_status_u0 == all_ports_seen_u0) { 913 del_timer_sync(&xhci->comp_mode_recovery_timer); 914 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 915 "All USB3 ports have entered U0 already!"); 916 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 917 "Compliance Mode Recovery Timer Deleted."); 918 } 919 } 920 } 921 922 static int xhci_handle_usb2_port_link_resume(struct xhci_port *port, 923 u32 *status, u32 portsc, 924 unsigned long *flags) 925 { 926 struct xhci_bus_state *bus_state; 927 struct xhci_hcd *xhci; 928 struct usb_hcd *hcd; 929 int slot_id; 930 u32 wIndex; 931 932 hcd = port->rhub->hcd; 933 bus_state = &port->rhub->bus_state; 934 xhci = hcd_to_xhci(hcd); 935 wIndex = port->hcd_portnum; 936 937 if ((portsc & PORT_RESET) || !(portsc & PORT_PE)) { 938 *status = 0xffffffff; 939 return -EINVAL; 940 } 941 /* did port event handler already start resume timing? */ 942 if (!bus_state->resume_done[wIndex]) { 943 /* If not, maybe we are in a host initated resume? */ 944 if (test_bit(wIndex, &bus_state->resuming_ports)) { 945 /* Host initated resume doesn't time the resume 946 * signalling using resume_done[]. 947 * It manually sets RESUME state, sleeps 20ms 948 * and sets U0 state. This should probably be 949 * changed, but not right now. 950 */ 951 } else { 952 /* port resume was discovered now and here, 953 * start resume timing 954 */ 955 unsigned long timeout = jiffies + 956 msecs_to_jiffies(USB_RESUME_TIMEOUT); 957 958 set_bit(wIndex, &bus_state->resuming_ports); 959 bus_state->resume_done[wIndex] = timeout; 960 mod_timer(&hcd->rh_timer, timeout); 961 usb_hcd_start_port_resume(&hcd->self, wIndex); 962 } 963 /* Has resume been signalled for USB_RESUME_TIME yet? */ 964 } else if (time_after_eq(jiffies, bus_state->resume_done[wIndex])) { 965 int time_left; 966 967 xhci_dbg(xhci, "resume USB2 port %d-%d\n", 968 hcd->self.busnum, wIndex + 1); 969 970 bus_state->resume_done[wIndex] = 0; 971 clear_bit(wIndex, &bus_state->resuming_ports); 972 973 set_bit(wIndex, &bus_state->rexit_ports); 974 975 xhci_test_and_clear_bit(xhci, port, PORT_PLC); 976 xhci_set_link_state(xhci, port, XDEV_U0); 977 978 spin_unlock_irqrestore(&xhci->lock, *flags); 979 time_left = wait_for_completion_timeout( 980 &bus_state->rexit_done[wIndex], 981 msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS)); 982 spin_lock_irqsave(&xhci->lock, *flags); 983 984 if (time_left) { 985 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 986 wIndex + 1); 987 if (!slot_id) { 988 xhci_dbg(xhci, "slot_id is zero\n"); 989 *status = 0xffffffff; 990 return -ENODEV; 991 } 992 xhci_ring_device(xhci, slot_id); 993 } else { 994 int port_status = readl(port->addr); 995 996 xhci_warn(xhci, "Port resume timed out, port %d-%d: 0x%x\n", 997 hcd->self.busnum, wIndex + 1, port_status); 998 *status |= USB_PORT_STAT_SUSPEND; 999 clear_bit(wIndex, &bus_state->rexit_ports); 1000 } 1001 1002 usb_hcd_end_port_resume(&hcd->self, wIndex); 1003 bus_state->port_c_suspend |= 1 << wIndex; 1004 bus_state->suspended_ports &= ~(1 << wIndex); 1005 } else { 1006 /* 1007 * The resume has been signaling for less than 1008 * USB_RESUME_TIME. Report the port status as SUSPEND, 1009 * let the usbcore check port status again and clear 1010 * resume signaling later. 1011 */ 1012 *status |= USB_PORT_STAT_SUSPEND; 1013 } 1014 return 0; 1015 } 1016 1017 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li) 1018 { 1019 u32 ext_stat = 0; 1020 int speed_id; 1021 1022 /* only support rx and tx lane counts of 1 in usb3.1 spec */ 1023 speed_id = DEV_PORT_SPEED(raw_port_status); 1024 ext_stat |= speed_id; /* bits 3:0, RX speed id */ 1025 ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */ 1026 1027 ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */ 1028 ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */ 1029 1030 return ext_stat; 1031 } 1032 1033 static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status, 1034 u32 portsc) 1035 { 1036 struct xhci_bus_state *bus_state; 1037 struct xhci_hcd *xhci; 1038 struct usb_hcd *hcd; 1039 u32 link_state; 1040 u32 portnum; 1041 1042 bus_state = &port->rhub->bus_state; 1043 xhci = hcd_to_xhci(port->rhub->hcd); 1044 hcd = port->rhub->hcd; 1045 link_state = portsc & PORT_PLS_MASK; 1046 portnum = port->hcd_portnum; 1047 1048 /* USB3 specific wPortChange bits 1049 * 1050 * Port link change with port in resume state should not be 1051 * reported to usbcore, as this is an internal state to be 1052 * handled by xhci driver. Reporting PLC to usbcore may 1053 * cause usbcore clearing PLC first and port change event 1054 * irq won't be generated. 1055 */ 1056 1057 if (portsc & PORT_PLC && (link_state != XDEV_RESUME)) 1058 *status |= USB_PORT_STAT_C_LINK_STATE << 16; 1059 if (portsc & PORT_WRC) 1060 *status |= USB_PORT_STAT_C_BH_RESET << 16; 1061 if (portsc & PORT_CEC) 1062 *status |= USB_PORT_STAT_C_CONFIG_ERROR << 16; 1063 1064 /* USB3 specific wPortStatus bits */ 1065 if (portsc & PORT_POWER) { 1066 *status |= USB_SS_PORT_STAT_POWER; 1067 /* link state handling */ 1068 if (link_state == XDEV_U0) 1069 bus_state->suspended_ports &= ~(1 << portnum); 1070 } 1071 1072 /* remote wake resume signaling complete */ 1073 if (bus_state->port_remote_wakeup & (1 << portnum) && 1074 link_state != XDEV_RESUME && 1075 link_state != XDEV_RECOVERY) { 1076 bus_state->port_remote_wakeup &= ~(1 << portnum); 1077 usb_hcd_end_port_resume(&hcd->self, portnum); 1078 } 1079 1080 xhci_hub_report_usb3_link_state(xhci, status, portsc); 1081 xhci_del_comp_mod_timer(xhci, portsc, portnum); 1082 } 1083 1084 static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status, 1085 u32 portsc, unsigned long *flags) 1086 { 1087 struct xhci_bus_state *bus_state; 1088 u32 link_state; 1089 u32 portnum; 1090 int ret; 1091 1092 bus_state = &port->rhub->bus_state; 1093 link_state = portsc & PORT_PLS_MASK; 1094 portnum = port->hcd_portnum; 1095 1096 /* USB2 wPortStatus bits */ 1097 if (portsc & PORT_POWER) { 1098 *status |= USB_PORT_STAT_POWER; 1099 1100 /* link state is only valid if port is powered */ 1101 if (link_state == XDEV_U3) 1102 *status |= USB_PORT_STAT_SUSPEND; 1103 if (link_state == XDEV_U2) 1104 *status |= USB_PORT_STAT_L1; 1105 if (link_state == XDEV_U0) { 1106 if (bus_state->resume_done[portnum]) 1107 usb_hcd_end_port_resume(&port->rhub->hcd->self, 1108 portnum); 1109 bus_state->resume_done[portnum] = 0; 1110 clear_bit(portnum, &bus_state->resuming_ports); 1111 if (bus_state->suspended_ports & (1 << portnum)) { 1112 bus_state->suspended_ports &= ~(1 << portnum); 1113 bus_state->port_c_suspend |= 1 << portnum; 1114 } 1115 } 1116 if (link_state == XDEV_RESUME) { 1117 ret = xhci_handle_usb2_port_link_resume(port, status, 1118 portsc, flags); 1119 if (ret) 1120 return; 1121 } 1122 } 1123 } 1124 1125 /* 1126 * Converts a raw xHCI port status into the format that external USB 2.0 or USB 1127 * 3.0 hubs use. 1128 * 1129 * Possible side effects: 1130 * - Mark a port as being done with device resume, 1131 * and ring the endpoint doorbells. 1132 * - Stop the Synopsys redriver Compliance Mode polling. 1133 * - Drop and reacquire the xHCI lock, in order to wait for port resume. 1134 */ 1135 static u32 xhci_get_port_status(struct usb_hcd *hcd, 1136 struct xhci_bus_state *bus_state, 1137 u16 wIndex, u32 raw_port_status, 1138 unsigned long *flags) 1139 __releases(&xhci->lock) 1140 __acquires(&xhci->lock) 1141 { 1142 u32 status = 0; 1143 struct xhci_hub *rhub; 1144 struct xhci_port *port; 1145 1146 rhub = xhci_get_rhub(hcd); 1147 port = rhub->ports[wIndex]; 1148 1149 /* common wPortChange bits */ 1150 if (raw_port_status & PORT_CSC) 1151 status |= USB_PORT_STAT_C_CONNECTION << 16; 1152 if (raw_port_status & PORT_PEC) 1153 status |= USB_PORT_STAT_C_ENABLE << 16; 1154 if ((raw_port_status & PORT_OCC)) 1155 status |= USB_PORT_STAT_C_OVERCURRENT << 16; 1156 if ((raw_port_status & PORT_RC)) 1157 status |= USB_PORT_STAT_C_RESET << 16; 1158 1159 /* common wPortStatus bits */ 1160 if (raw_port_status & PORT_CONNECT) { 1161 status |= USB_PORT_STAT_CONNECTION; 1162 status |= xhci_port_speed(raw_port_status); 1163 } 1164 if (raw_port_status & PORT_PE) 1165 status |= USB_PORT_STAT_ENABLE; 1166 if (raw_port_status & PORT_OC) 1167 status |= USB_PORT_STAT_OVERCURRENT; 1168 if (raw_port_status & PORT_RESET) 1169 status |= USB_PORT_STAT_RESET; 1170 1171 /* USB2 and USB3 specific bits, including Port Link State */ 1172 if (hcd->speed >= HCD_USB3) 1173 xhci_get_usb3_port_status(port, &status, raw_port_status); 1174 else 1175 xhci_get_usb2_port_status(port, &status, raw_port_status, 1176 flags); 1177 /* 1178 * Clear stale usb2 resume signalling variables in case port changed 1179 * state during resume signalling. For example on error 1180 */ 1181 if ((bus_state->resume_done[wIndex] || 1182 test_bit(wIndex, &bus_state->resuming_ports)) && 1183 (raw_port_status & PORT_PLS_MASK) != XDEV_U3 && 1184 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) { 1185 bus_state->resume_done[wIndex] = 0; 1186 clear_bit(wIndex, &bus_state->resuming_ports); 1187 usb_hcd_end_port_resume(&hcd->self, wIndex); 1188 } 1189 1190 if (bus_state->port_c_suspend & (1 << wIndex)) 1191 status |= USB_PORT_STAT_C_SUSPEND << 16; 1192 1193 return status; 1194 } 1195 1196 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 1197 u16 wIndex, char *buf, u16 wLength) 1198 { 1199 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1200 int max_ports; 1201 unsigned long flags; 1202 u32 temp, status; 1203 int retval = 0; 1204 int slot_id; 1205 struct xhci_bus_state *bus_state; 1206 u16 link_state = 0; 1207 u16 wake_mask = 0; 1208 u16 timeout = 0; 1209 u16 test_mode = 0; 1210 struct xhci_hub *rhub; 1211 struct xhci_port **ports; 1212 1213 rhub = xhci_get_rhub(hcd); 1214 ports = rhub->ports; 1215 max_ports = rhub->num_ports; 1216 bus_state = &rhub->bus_state; 1217 1218 spin_lock_irqsave(&xhci->lock, flags); 1219 switch (typeReq) { 1220 case GetHubStatus: 1221 /* No power source, over-current reported per port */ 1222 memset(buf, 0, 4); 1223 break; 1224 case GetHubDescriptor: 1225 /* Check to make sure userspace is asking for the USB 3.0 hub 1226 * descriptor for the USB 3.0 roothub. If not, we stall the 1227 * endpoint, like external hubs do. 1228 */ 1229 if (hcd->speed >= HCD_USB3 && 1230 (wLength < USB_DT_SS_HUB_SIZE || 1231 wValue != (USB_DT_SS_HUB << 8))) { 1232 xhci_dbg(xhci, "Wrong hub descriptor type for " 1233 "USB 3.0 roothub.\n"); 1234 goto error; 1235 } 1236 xhci_hub_descriptor(hcd, xhci, 1237 (struct usb_hub_descriptor *) buf); 1238 break; 1239 case DeviceRequest | USB_REQ_GET_DESCRIPTOR: 1240 if ((wValue & 0xff00) != (USB_DT_BOS << 8)) 1241 goto error; 1242 1243 if (hcd->speed < HCD_USB3) 1244 goto error; 1245 1246 retval = xhci_create_usb3x_bos_desc(xhci, buf, wLength); 1247 spin_unlock_irqrestore(&xhci->lock, flags); 1248 return retval; 1249 case GetPortStatus: 1250 if (!wIndex || wIndex > max_ports) 1251 goto error; 1252 wIndex--; 1253 temp = readl(ports[wIndex]->addr); 1254 if (temp == ~(u32)0) { 1255 xhci_hc_died(xhci); 1256 retval = -ENODEV; 1257 break; 1258 } 1259 trace_xhci_get_port_status(wIndex, temp); 1260 status = xhci_get_port_status(hcd, bus_state, wIndex, temp, 1261 &flags); 1262 if (status == 0xffffffff) 1263 goto error; 1264 1265 xhci_dbg(xhci, "Get port status %d-%d read: 0x%x, return 0x%x", 1266 hcd->self.busnum, wIndex + 1, temp, status); 1267 1268 put_unaligned(cpu_to_le32(status), (__le32 *) buf); 1269 /* if USB 3.1 extended port status return additional 4 bytes */ 1270 if (wValue == 0x02) { 1271 u32 port_li; 1272 1273 if (hcd->speed < HCD_USB31 || wLength != 8) { 1274 xhci_err(xhci, "get ext port status invalid parameter\n"); 1275 retval = -EINVAL; 1276 break; 1277 } 1278 port_li = readl(ports[wIndex]->addr + PORTLI); 1279 status = xhci_get_ext_port_status(temp, port_li); 1280 put_unaligned_le32(status, &buf[4]); 1281 } 1282 break; 1283 case SetPortFeature: 1284 if (wValue == USB_PORT_FEAT_LINK_STATE) 1285 link_state = (wIndex & 0xff00) >> 3; 1286 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK) 1287 wake_mask = wIndex & 0xff00; 1288 if (wValue == USB_PORT_FEAT_TEST) 1289 test_mode = (wIndex & 0xff00) >> 8; 1290 /* The MSB of wIndex is the U1/U2 timeout */ 1291 timeout = (wIndex & 0xff00) >> 8; 1292 wIndex &= 0xff; 1293 if (!wIndex || wIndex > max_ports) 1294 goto error; 1295 wIndex--; 1296 temp = readl(ports[wIndex]->addr); 1297 if (temp == ~(u32)0) { 1298 xhci_hc_died(xhci); 1299 retval = -ENODEV; 1300 break; 1301 } 1302 temp = xhci_port_state_to_neutral(temp); 1303 /* FIXME: What new port features do we need to support? */ 1304 switch (wValue) { 1305 case USB_PORT_FEAT_SUSPEND: 1306 temp = readl(ports[wIndex]->addr); 1307 if ((temp & PORT_PLS_MASK) != XDEV_U0) { 1308 /* Resume the port to U0 first */ 1309 xhci_set_link_state(xhci, ports[wIndex], 1310 XDEV_U0); 1311 spin_unlock_irqrestore(&xhci->lock, flags); 1312 msleep(10); 1313 spin_lock_irqsave(&xhci->lock, flags); 1314 } 1315 /* In spec software should not attempt to suspend 1316 * a port unless the port reports that it is in the 1317 * enabled (PED = ‘1’,PLS < ‘3’) state. 1318 */ 1319 temp = readl(ports[wIndex]->addr); 1320 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) 1321 || (temp & PORT_PLS_MASK) >= XDEV_U3) { 1322 xhci_warn(xhci, "USB core suspending port %d-%d not in U0/U1/U2\n", 1323 hcd->self.busnum, wIndex + 1); 1324 goto error; 1325 } 1326 1327 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 1328 wIndex + 1); 1329 if (!slot_id) { 1330 xhci_warn(xhci, "slot_id is zero\n"); 1331 goto error; 1332 } 1333 /* unlock to execute stop endpoint commands */ 1334 spin_unlock_irqrestore(&xhci->lock, flags); 1335 xhci_stop_device(xhci, slot_id, 1); 1336 spin_lock_irqsave(&xhci->lock, flags); 1337 1338 xhci_set_link_state(xhci, ports[wIndex], XDEV_U3); 1339 1340 spin_unlock_irqrestore(&xhci->lock, flags); 1341 msleep(10); /* wait device to enter */ 1342 spin_lock_irqsave(&xhci->lock, flags); 1343 1344 temp = readl(ports[wIndex]->addr); 1345 bus_state->suspended_ports |= 1 << wIndex; 1346 break; 1347 case USB_PORT_FEAT_LINK_STATE: 1348 temp = readl(ports[wIndex]->addr); 1349 /* Disable port */ 1350 if (link_state == USB_SS_PORT_LS_SS_DISABLED) { 1351 xhci_dbg(xhci, "Disable port %d-%d\n", 1352 hcd->self.busnum, wIndex + 1); 1353 temp = xhci_port_state_to_neutral(temp); 1354 /* 1355 * Clear all change bits, so that we get a new 1356 * connection event. 1357 */ 1358 temp |= PORT_CSC | PORT_PEC | PORT_WRC | 1359 PORT_OCC | PORT_RC | PORT_PLC | 1360 PORT_CEC; 1361 writel(temp | PORT_PE, ports[wIndex]->addr); 1362 temp = readl(ports[wIndex]->addr); 1363 break; 1364 } 1365 1366 /* Put link in RxDetect (enable port) */ 1367 if (link_state == USB_SS_PORT_LS_RX_DETECT) { 1368 xhci_dbg(xhci, "Enable port %d-%d\n", 1369 hcd->self.busnum, wIndex + 1); 1370 xhci_set_link_state(xhci, ports[wIndex], 1371 link_state); 1372 temp = readl(ports[wIndex]->addr); 1373 break; 1374 } 1375 1376 /* 1377 * For xHCI 1.1 according to section 4.19.1.2.4.1 a 1378 * root hub port's transition to compliance mode upon 1379 * detecting LFPS timeout may be controlled by an 1380 * Compliance Transition Enabled (CTE) flag (not 1381 * software visible). This flag is set by writing 0xA 1382 * to PORTSC PLS field which will allow transition to 1383 * compliance mode the next time LFPS timeout is 1384 * encountered. A warm reset will clear it. 1385 * 1386 * The CTE flag is only supported if the HCCPARAMS2 CTC 1387 * flag is set, otherwise, the compliance substate is 1388 * automatically entered as on 1.0 and prior. 1389 */ 1390 if (link_state == USB_SS_PORT_LS_COMP_MOD) { 1391 if (!HCC2_CTC(xhci->hcc_params2)) { 1392 xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n"); 1393 break; 1394 } 1395 1396 if ((temp & PORT_CONNECT)) { 1397 xhci_warn(xhci, "Can't set compliance mode when port is connected\n"); 1398 goto error; 1399 } 1400 1401 xhci_dbg(xhci, "Enable compliance mode transition for port %d-%d\n", 1402 hcd->self.busnum, wIndex + 1); 1403 xhci_set_link_state(xhci, ports[wIndex], 1404 link_state); 1405 1406 temp = readl(ports[wIndex]->addr); 1407 break; 1408 } 1409 /* Port must be enabled */ 1410 if (!(temp & PORT_PE)) { 1411 retval = -ENODEV; 1412 break; 1413 } 1414 /* Can't set port link state above '3' (U3) */ 1415 if (link_state > USB_SS_PORT_LS_U3) { 1416 xhci_warn(xhci, "Cannot set port %d-%d link state %d\n", 1417 hcd->self.busnum, wIndex + 1, 1418 link_state); 1419 goto error; 1420 } 1421 1422 /* 1423 * set link to U0, steps depend on current link state. 1424 * U3: set link to U0 and wait for u3exit completion. 1425 * U1/U2: no PLC complete event, only set link to U0. 1426 * Resume/Recovery: device initiated U0, only wait for 1427 * completion 1428 */ 1429 if (link_state == USB_SS_PORT_LS_U0) { 1430 u32 pls = temp & PORT_PLS_MASK; 1431 bool wait_u0 = false; 1432 1433 /* already in U0 */ 1434 if (pls == XDEV_U0) 1435 break; 1436 if (pls == XDEV_U3 || 1437 pls == XDEV_RESUME || 1438 pls == XDEV_RECOVERY) { 1439 wait_u0 = true; 1440 reinit_completion(&bus_state->u3exit_done[wIndex]); 1441 } 1442 if (pls <= XDEV_U3) /* U1, U2, U3 */ 1443 xhci_set_link_state(xhci, ports[wIndex], 1444 USB_SS_PORT_LS_U0); 1445 if (!wait_u0) { 1446 if (pls > XDEV_U3) 1447 goto error; 1448 break; 1449 } 1450 spin_unlock_irqrestore(&xhci->lock, flags); 1451 if (!wait_for_completion_timeout(&bus_state->u3exit_done[wIndex], 1452 msecs_to_jiffies(500))) 1453 xhci_dbg(xhci, "missing U0 port change event for port %d-%d\n", 1454 hcd->self.busnum, wIndex + 1); 1455 spin_lock_irqsave(&xhci->lock, flags); 1456 temp = readl(ports[wIndex]->addr); 1457 break; 1458 } 1459 1460 if (link_state == USB_SS_PORT_LS_U3) { 1461 int retries = 16; 1462 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 1463 wIndex + 1); 1464 if (slot_id) { 1465 /* unlock to execute stop endpoint 1466 * commands */ 1467 spin_unlock_irqrestore(&xhci->lock, 1468 flags); 1469 xhci_stop_device(xhci, slot_id, 1); 1470 spin_lock_irqsave(&xhci->lock, flags); 1471 } 1472 xhci_set_link_state(xhci, ports[wIndex], USB_SS_PORT_LS_U3); 1473 spin_unlock_irqrestore(&xhci->lock, flags); 1474 while (retries--) { 1475 usleep_range(4000, 8000); 1476 temp = readl(ports[wIndex]->addr); 1477 if ((temp & PORT_PLS_MASK) == XDEV_U3) 1478 break; 1479 } 1480 spin_lock_irqsave(&xhci->lock, flags); 1481 temp = readl(ports[wIndex]->addr); 1482 bus_state->suspended_ports |= 1 << wIndex; 1483 } 1484 break; 1485 case USB_PORT_FEAT_POWER: 1486 /* 1487 * Turn on ports, even if there isn't per-port switching. 1488 * HC will report connect events even before this is set. 1489 * However, hub_wq will ignore the roothub events until 1490 * the roothub is registered. 1491 */ 1492 xhci_set_port_power(xhci, hcd, wIndex, true, &flags); 1493 break; 1494 case USB_PORT_FEAT_RESET: 1495 temp = (temp | PORT_RESET); 1496 writel(temp, ports[wIndex]->addr); 1497 1498 temp = readl(ports[wIndex]->addr); 1499 xhci_dbg(xhci, "set port reset, actual port %d-%d status = 0x%x\n", 1500 hcd->self.busnum, wIndex + 1, temp); 1501 break; 1502 case USB_PORT_FEAT_REMOTE_WAKE_MASK: 1503 xhci_set_remote_wake_mask(xhci, ports[wIndex], 1504 wake_mask); 1505 temp = readl(ports[wIndex]->addr); 1506 xhci_dbg(xhci, "set port remote wake mask, actual port %d-%d status = 0x%x\n", 1507 hcd->self.busnum, wIndex + 1, temp); 1508 break; 1509 case USB_PORT_FEAT_BH_PORT_RESET: 1510 temp |= PORT_WR; 1511 writel(temp, ports[wIndex]->addr); 1512 temp = readl(ports[wIndex]->addr); 1513 break; 1514 case USB_PORT_FEAT_U1_TIMEOUT: 1515 if (hcd->speed < HCD_USB3) 1516 goto error; 1517 temp = readl(ports[wIndex]->addr + PORTPMSC); 1518 temp &= ~PORT_U1_TIMEOUT_MASK; 1519 temp |= PORT_U1_TIMEOUT(timeout); 1520 writel(temp, ports[wIndex]->addr + PORTPMSC); 1521 break; 1522 case USB_PORT_FEAT_U2_TIMEOUT: 1523 if (hcd->speed < HCD_USB3) 1524 goto error; 1525 temp = readl(ports[wIndex]->addr + PORTPMSC); 1526 temp &= ~PORT_U2_TIMEOUT_MASK; 1527 temp |= PORT_U2_TIMEOUT(timeout); 1528 writel(temp, ports[wIndex]->addr + PORTPMSC); 1529 break; 1530 case USB_PORT_FEAT_TEST: 1531 /* 4.19.6 Port Test Modes (USB2 Test Mode) */ 1532 if (hcd->speed != HCD_USB2) 1533 goto error; 1534 if (test_mode > USB_TEST_FORCE_ENABLE || 1535 test_mode < USB_TEST_J) 1536 goto error; 1537 retval = xhci_enter_test_mode(xhci, test_mode, wIndex, 1538 &flags); 1539 break; 1540 default: 1541 goto error; 1542 } 1543 /* unblock any posted writes */ 1544 temp = readl(ports[wIndex]->addr); 1545 break; 1546 case ClearPortFeature: 1547 if (!wIndex || wIndex > max_ports) 1548 goto error; 1549 wIndex--; 1550 temp = readl(ports[wIndex]->addr); 1551 if (temp == ~(u32)0) { 1552 xhci_hc_died(xhci); 1553 retval = -ENODEV; 1554 break; 1555 } 1556 /* FIXME: What new port features do we need to support? */ 1557 temp = xhci_port_state_to_neutral(temp); 1558 switch (wValue) { 1559 case USB_PORT_FEAT_SUSPEND: 1560 temp = readl(ports[wIndex]->addr); 1561 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n"); 1562 xhci_dbg(xhci, "PORTSC %04x\n", temp); 1563 if (temp & PORT_RESET) 1564 goto error; 1565 if ((temp & PORT_PLS_MASK) == XDEV_U3) { 1566 if ((temp & PORT_PE) == 0) 1567 goto error; 1568 1569 set_bit(wIndex, &bus_state->resuming_ports); 1570 usb_hcd_start_port_resume(&hcd->self, wIndex); 1571 xhci_set_link_state(xhci, ports[wIndex], 1572 XDEV_RESUME); 1573 spin_unlock_irqrestore(&xhci->lock, flags); 1574 msleep(USB_RESUME_TIMEOUT); 1575 spin_lock_irqsave(&xhci->lock, flags); 1576 xhci_set_link_state(xhci, ports[wIndex], 1577 XDEV_U0); 1578 clear_bit(wIndex, &bus_state->resuming_ports); 1579 usb_hcd_end_port_resume(&hcd->self, wIndex); 1580 } 1581 bus_state->port_c_suspend |= 1 << wIndex; 1582 1583 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 1584 wIndex + 1); 1585 if (!slot_id) { 1586 xhci_dbg(xhci, "slot_id is zero\n"); 1587 goto error; 1588 } 1589 xhci_ring_device(xhci, slot_id); 1590 break; 1591 case USB_PORT_FEAT_C_SUSPEND: 1592 bus_state->port_c_suspend &= ~(1 << wIndex); 1593 fallthrough; 1594 case USB_PORT_FEAT_C_RESET: 1595 case USB_PORT_FEAT_C_BH_PORT_RESET: 1596 case USB_PORT_FEAT_C_CONNECTION: 1597 case USB_PORT_FEAT_C_OVER_CURRENT: 1598 case USB_PORT_FEAT_C_ENABLE: 1599 case USB_PORT_FEAT_C_PORT_LINK_STATE: 1600 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR: 1601 xhci_clear_port_change_bit(xhci, wValue, wIndex, 1602 ports[wIndex]->addr, temp); 1603 break; 1604 case USB_PORT_FEAT_ENABLE: 1605 xhci_disable_port(hcd, xhci, wIndex, 1606 ports[wIndex]->addr, temp); 1607 break; 1608 case USB_PORT_FEAT_POWER: 1609 xhci_set_port_power(xhci, hcd, wIndex, false, &flags); 1610 break; 1611 case USB_PORT_FEAT_TEST: 1612 retval = xhci_exit_test_mode(xhci); 1613 break; 1614 default: 1615 goto error; 1616 } 1617 break; 1618 default: 1619 error: 1620 /* "stall" on error */ 1621 retval = -EPIPE; 1622 } 1623 spin_unlock_irqrestore(&xhci->lock, flags); 1624 return retval; 1625 } 1626 1627 /* 1628 * Returns 0 if the status hasn't changed, or the number of bytes in buf. 1629 * Ports are 0-indexed from the HCD point of view, 1630 * and 1-indexed from the USB core pointer of view. 1631 * 1632 * Note that the status change bits will be cleared as soon as a port status 1633 * change event is generated, so we use the saved status from that event. 1634 */ 1635 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf) 1636 { 1637 unsigned long flags; 1638 u32 temp, status; 1639 u32 mask; 1640 int i, retval; 1641 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1642 int max_ports; 1643 struct xhci_bus_state *bus_state; 1644 bool reset_change = false; 1645 struct xhci_hub *rhub; 1646 struct xhci_port **ports; 1647 1648 rhub = xhci_get_rhub(hcd); 1649 ports = rhub->ports; 1650 max_ports = rhub->num_ports; 1651 bus_state = &rhub->bus_state; 1652 1653 /* Initial status is no changes */ 1654 retval = (max_ports + 8) / 8; 1655 memset(buf, 0, retval); 1656 1657 /* 1658 * Inform the usbcore about resume-in-progress by returning 1659 * a non-zero value even if there are no status changes. 1660 */ 1661 spin_lock_irqsave(&xhci->lock, flags); 1662 1663 status = bus_state->resuming_ports; 1664 1665 /* 1666 * SS devices are only visible to roothub after link training completes. 1667 * Keep polling roothubs for a grace period after xHC start 1668 */ 1669 if (xhci->run_graceperiod) { 1670 if (time_before(jiffies, xhci->run_graceperiod)) 1671 status = 1; 1672 else 1673 xhci->run_graceperiod = 0; 1674 } 1675 1676 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC; 1677 1678 /* For each port, did anything change? If so, set that bit in buf. */ 1679 for (i = 0; i < max_ports; i++) { 1680 temp = readl(ports[i]->addr); 1681 if (temp == ~(u32)0) { 1682 xhci_hc_died(xhci); 1683 retval = -ENODEV; 1684 break; 1685 } 1686 trace_xhci_hub_status_data(i, temp); 1687 1688 if ((temp & mask) != 0 || 1689 (bus_state->port_c_suspend & 1 << i) || 1690 (bus_state->resume_done[i] && time_after_eq( 1691 jiffies, bus_state->resume_done[i]))) { 1692 buf[(i + 1) / 8] |= 1 << (i + 1) % 8; 1693 status = 1; 1694 } 1695 if ((temp & PORT_RC)) 1696 reset_change = true; 1697 if (temp & PORT_OC) 1698 status = 1; 1699 } 1700 if (!status && !reset_change) { 1701 xhci_dbg(xhci, "%s: stopping usb%d port polling\n", 1702 __func__, hcd->self.busnum); 1703 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); 1704 } 1705 spin_unlock_irqrestore(&xhci->lock, flags); 1706 return status ? retval : 0; 1707 } 1708 1709 #ifdef CONFIG_PM 1710 1711 int xhci_bus_suspend(struct usb_hcd *hcd) 1712 { 1713 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1714 int max_ports, port_index; 1715 struct xhci_bus_state *bus_state; 1716 unsigned long flags; 1717 struct xhci_hub *rhub; 1718 struct xhci_port **ports; 1719 u32 portsc_buf[USB_MAXCHILDREN]; 1720 bool wake_enabled; 1721 1722 rhub = xhci_get_rhub(hcd); 1723 ports = rhub->ports; 1724 max_ports = rhub->num_ports; 1725 bus_state = &rhub->bus_state; 1726 wake_enabled = hcd->self.root_hub->do_remote_wakeup; 1727 1728 spin_lock_irqsave(&xhci->lock, flags); 1729 1730 if (wake_enabled) { 1731 if (bus_state->resuming_ports || /* USB2 */ 1732 bus_state->port_remote_wakeup) { /* USB3 */ 1733 spin_unlock_irqrestore(&xhci->lock, flags); 1734 xhci_dbg(xhci, "usb%d bus suspend to fail because a port is resuming\n", 1735 hcd->self.busnum); 1736 return -EBUSY; 1737 } 1738 } 1739 /* 1740 * Prepare ports for suspend, but don't write anything before all ports 1741 * are checked and we know bus suspend can proceed 1742 */ 1743 bus_state->bus_suspended = 0; 1744 port_index = max_ports; 1745 while (port_index--) { 1746 u32 t1, t2; 1747 int retries = 10; 1748 retry: 1749 t1 = readl(ports[port_index]->addr); 1750 t2 = xhci_port_state_to_neutral(t1); 1751 portsc_buf[port_index] = 0; 1752 1753 /* 1754 * Give a USB3 port in link training time to finish, but don't 1755 * prevent suspend as port might be stuck 1756 */ 1757 if ((hcd->speed >= HCD_USB3) && retries-- && 1758 (t1 & PORT_PLS_MASK) == XDEV_POLLING) { 1759 spin_unlock_irqrestore(&xhci->lock, flags); 1760 msleep(XHCI_PORT_POLLING_LFPS_TIME); 1761 spin_lock_irqsave(&xhci->lock, flags); 1762 xhci_dbg(xhci, "port %d-%d polling in bus suspend, waiting\n", 1763 hcd->self.busnum, port_index + 1); 1764 goto retry; 1765 } 1766 /* bail out if port detected a over-current condition */ 1767 if (t1 & PORT_OC) { 1768 bus_state->bus_suspended = 0; 1769 spin_unlock_irqrestore(&xhci->lock, flags); 1770 xhci_dbg(xhci, "Bus suspend bailout, port over-current detected\n"); 1771 return -EBUSY; 1772 } 1773 /* suspend ports in U0, or bail out for new connect changes */ 1774 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) { 1775 if ((t1 & PORT_CSC) && wake_enabled) { 1776 bus_state->bus_suspended = 0; 1777 spin_unlock_irqrestore(&xhci->lock, flags); 1778 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n"); 1779 return -EBUSY; 1780 } 1781 xhci_dbg(xhci, "port %d-%d not suspended\n", 1782 hcd->self.busnum, port_index + 1); 1783 t2 &= ~PORT_PLS_MASK; 1784 t2 |= PORT_LINK_STROBE | XDEV_U3; 1785 set_bit(port_index, &bus_state->bus_suspended); 1786 } 1787 /* USB core sets remote wake mask for USB 3.0 hubs, 1788 * including the USB 3.0 roothub, but only if CONFIG_PM 1789 * is enabled, so also enable remote wake here. 1790 */ 1791 if (wake_enabled) { 1792 if (t1 & PORT_CONNECT) { 1793 t2 |= PORT_WKOC_E | PORT_WKDISC_E; 1794 t2 &= ~PORT_WKCONN_E; 1795 } else { 1796 t2 |= PORT_WKOC_E | PORT_WKCONN_E; 1797 t2 &= ~PORT_WKDISC_E; 1798 } 1799 1800 if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) && 1801 (hcd->speed < HCD_USB3)) { 1802 if (usb_amd_pt_check_port(hcd->self.controller, 1803 port_index)) 1804 t2 &= ~PORT_WAKE_BITS; 1805 } 1806 } else 1807 t2 &= ~PORT_WAKE_BITS; 1808 1809 t1 = xhci_port_state_to_neutral(t1); 1810 if (t1 != t2) 1811 portsc_buf[port_index] = t2; 1812 } 1813 1814 /* write port settings, stopping and suspending ports if needed */ 1815 port_index = max_ports; 1816 while (port_index--) { 1817 if (!portsc_buf[port_index]) 1818 continue; 1819 if (test_bit(port_index, &bus_state->bus_suspended)) { 1820 int slot_id; 1821 1822 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 1823 port_index + 1); 1824 if (slot_id) { 1825 spin_unlock_irqrestore(&xhci->lock, flags); 1826 xhci_stop_device(xhci, slot_id, 1); 1827 spin_lock_irqsave(&xhci->lock, flags); 1828 } 1829 } 1830 writel(portsc_buf[port_index], ports[port_index]->addr); 1831 } 1832 hcd->state = HC_STATE_SUSPENDED; 1833 bus_state->next_statechange = jiffies + msecs_to_jiffies(10); 1834 spin_unlock_irqrestore(&xhci->lock, flags); 1835 1836 if (bus_state->bus_suspended) 1837 usleep_range(5000, 10000); 1838 1839 return 0; 1840 } 1841 1842 /* 1843 * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3. 1844 * warm reset a USB3 device stuck in polling or compliance mode after resume. 1845 * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8 1846 */ 1847 static bool xhci_port_missing_cas_quirk(struct xhci_port *port) 1848 { 1849 u32 portsc; 1850 1851 portsc = readl(port->addr); 1852 1853 /* if any of these are set we are not stuck */ 1854 if (portsc & (PORT_CONNECT | PORT_CAS)) 1855 return false; 1856 1857 if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) && 1858 ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE)) 1859 return false; 1860 1861 /* clear wakeup/change bits, and do a warm port reset */ 1862 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); 1863 portsc |= PORT_WR; 1864 writel(portsc, port->addr); 1865 /* flush write */ 1866 readl(port->addr); 1867 return true; 1868 } 1869 1870 int xhci_bus_resume(struct usb_hcd *hcd) 1871 { 1872 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1873 struct xhci_bus_state *bus_state; 1874 unsigned long flags; 1875 int max_ports, port_index; 1876 int slot_id; 1877 int sret; 1878 u32 next_state; 1879 u32 temp, portsc; 1880 struct xhci_hub *rhub; 1881 struct xhci_port **ports; 1882 1883 rhub = xhci_get_rhub(hcd); 1884 ports = rhub->ports; 1885 max_ports = rhub->num_ports; 1886 bus_state = &rhub->bus_state; 1887 1888 if (time_before(jiffies, bus_state->next_statechange)) 1889 msleep(5); 1890 1891 spin_lock_irqsave(&xhci->lock, flags); 1892 if (!HCD_HW_ACCESSIBLE(hcd)) { 1893 spin_unlock_irqrestore(&xhci->lock, flags); 1894 return -ESHUTDOWN; 1895 } 1896 1897 /* delay the irqs */ 1898 temp = readl(&xhci->op_regs->command); 1899 temp &= ~CMD_EIE; 1900 writel(temp, &xhci->op_regs->command); 1901 1902 /* bus specific resume for ports we suspended at bus_suspend */ 1903 if (hcd->speed >= HCD_USB3) 1904 next_state = XDEV_U0; 1905 else 1906 next_state = XDEV_RESUME; 1907 1908 port_index = max_ports; 1909 while (port_index--) { 1910 portsc = readl(ports[port_index]->addr); 1911 1912 /* warm reset CAS limited ports stuck in polling/compliance */ 1913 if ((xhci->quirks & XHCI_MISSING_CAS) && 1914 (hcd->speed >= HCD_USB3) && 1915 xhci_port_missing_cas_quirk(ports[port_index])) { 1916 xhci_dbg(xhci, "reset stuck port %d-%d\n", 1917 hcd->self.busnum, port_index + 1); 1918 clear_bit(port_index, &bus_state->bus_suspended); 1919 continue; 1920 } 1921 /* resume if we suspended the link, and it is still suspended */ 1922 if (test_bit(port_index, &bus_state->bus_suspended)) 1923 switch (portsc & PORT_PLS_MASK) { 1924 case XDEV_U3: 1925 portsc = xhci_port_state_to_neutral(portsc); 1926 portsc &= ~PORT_PLS_MASK; 1927 portsc |= PORT_LINK_STROBE | next_state; 1928 break; 1929 case XDEV_RESUME: 1930 /* resume already initiated */ 1931 break; 1932 default: 1933 /* not in a resumeable state, ignore it */ 1934 clear_bit(port_index, 1935 &bus_state->bus_suspended); 1936 break; 1937 } 1938 /* disable wake for all ports, write new link state if needed */ 1939 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); 1940 writel(portsc, ports[port_index]->addr); 1941 } 1942 1943 /* USB2 specific resume signaling delay and U0 link state transition */ 1944 if (hcd->speed < HCD_USB3) { 1945 if (bus_state->bus_suspended) { 1946 spin_unlock_irqrestore(&xhci->lock, flags); 1947 msleep(USB_RESUME_TIMEOUT); 1948 spin_lock_irqsave(&xhci->lock, flags); 1949 } 1950 for_each_set_bit(port_index, &bus_state->bus_suspended, 1951 BITS_PER_LONG) { 1952 /* Clear PLC to poll it later for U0 transition */ 1953 xhci_test_and_clear_bit(xhci, ports[port_index], 1954 PORT_PLC); 1955 xhci_set_link_state(xhci, ports[port_index], XDEV_U0); 1956 } 1957 } 1958 1959 /* poll for U0 link state complete, both USB2 and USB3 */ 1960 for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) { 1961 sret = xhci_handshake(ports[port_index]->addr, PORT_PLC, 1962 PORT_PLC, 10 * 1000); 1963 if (sret) { 1964 xhci_warn(xhci, "port %d-%d resume PLC timeout\n", 1965 hcd->self.busnum, port_index + 1); 1966 continue; 1967 } 1968 xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC); 1969 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1); 1970 if (slot_id) 1971 xhci_ring_device(xhci, slot_id); 1972 } 1973 (void) readl(&xhci->op_regs->command); 1974 1975 bus_state->next_statechange = jiffies + msecs_to_jiffies(5); 1976 /* re-enable irqs */ 1977 temp = readl(&xhci->op_regs->command); 1978 temp |= CMD_EIE; 1979 writel(temp, &xhci->op_regs->command); 1980 temp = readl(&xhci->op_regs->command); 1981 1982 spin_unlock_irqrestore(&xhci->lock, flags); 1983 return 0; 1984 } 1985 1986 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd) 1987 { 1988 struct xhci_hub *rhub = xhci_get_rhub(hcd); 1989 1990 /* USB3 port wakeups are reported via usb_wakeup_notification() */ 1991 return rhub->bus_state.resuming_ports; /* USB2 ports only */ 1992 } 1993 1994 #endif /* CONFIG_PM */ 1995