13e45ed3cSNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */
274c68741SSarah Sharp /*
374c68741SSarah Sharp * xHCI host controller driver
474c68741SSarah Sharp *
574c68741SSarah Sharp * Copyright (C) 2008 Intel Corp.
674c68741SSarah Sharp *
774c68741SSarah Sharp * Author: Sarah Sharp
874c68741SSarah Sharp * Some code borrowed from the Linux EHCI driver.
974c68741SSarah Sharp */
10*ca09b1beSMaximilian Luz
11*ca09b1beSMaximilian Luz /* HC should halt within 16 ms, but use 32 ms as some hosts take longer */
12*ca09b1beSMaximilian Luz #define XHCI_MAX_HALT_USEC (32 * 1000)
1374c68741SSarah Sharp /* HC not running - set to 1 when run/stop bit is cleared. */
1474c68741SSarah Sharp #define XHCI_STS_HALT (1<<0)
1574c68741SSarah Sharp
1674c68741SSarah Sharp /* HCCPARAMS offset from PCI base address */
1774c68741SSarah Sharp #define XHCI_HCC_PARAMS_OFFSET 0x10
1874c68741SSarah Sharp /* HCCPARAMS contains the first extended capability pointer */
1974c68741SSarah Sharp #define XHCI_HCC_EXT_CAPS(p) (((p)>>16)&0xffff)
2074c68741SSarah Sharp
2174c68741SSarah Sharp /* Command and Status registers offset from the Operational Registers address */
2274c68741SSarah Sharp #define XHCI_CMD_OFFSET 0x00
2374c68741SSarah Sharp #define XHCI_STS_OFFSET 0x04
2474c68741SSarah Sharp
2574c68741SSarah Sharp #define XHCI_MAX_EXT_CAPS 50
2674c68741SSarah Sharp
2774c68741SSarah Sharp /* Capability Register */
2874c68741SSarah Sharp /* bits 7:0 - how long is the Capabilities register */
2974c68741SSarah Sharp #define XHCI_HC_LENGTH(p) (((p)>>00)&0x00ff)
3074c68741SSarah Sharp
3174c68741SSarah Sharp /* Extended capability register fields */
3274c68741SSarah Sharp #define XHCI_EXT_CAPS_ID(p) (((p)>>0)&0xff)
3374c68741SSarah Sharp #define XHCI_EXT_CAPS_NEXT(p) (((p)>>8)&0xff)
3474c68741SSarah Sharp #define XHCI_EXT_CAPS_VAL(p) ((p)>>16)
3574c68741SSarah Sharp /* Extended capability IDs - ID 0 reserved */
3674c68741SSarah Sharp #define XHCI_EXT_CAPS_LEGACY 1
3774c68741SSarah Sharp #define XHCI_EXT_CAPS_PROTOCOL 2
3874c68741SSarah Sharp #define XHCI_EXT_CAPS_PM 3
3974c68741SSarah Sharp #define XHCI_EXT_CAPS_VIRT 4
4074c68741SSarah Sharp #define XHCI_EXT_CAPS_ROUTE 5
4174c68741SSarah Sharp /* IDs 6-9 reserved */
4274c68741SSarah Sharp #define XHCI_EXT_CAPS_DEBUG 10
43fa31b3cbSHans de Goede /* Vendor caps */
44fa31b3cbSHans de Goede #define XHCI_EXT_CAPS_VENDOR_INTEL 192
4574c68741SSarah Sharp /* USB Legacy Support Capability - section 7.1.1 */
4674c68741SSarah Sharp #define XHCI_HC_BIOS_OWNED (1 << 16)
4774c68741SSarah Sharp #define XHCI_HC_OS_OWNED (1 << 24)
4874c68741SSarah Sharp
4974c68741SSarah Sharp /* USB Legacy Support Capability - section 7.1.1 */
5074c68741SSarah Sharp /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
5174c68741SSarah Sharp #define XHCI_LEGACY_SUPPORT_OFFSET (0x00)
5274c68741SSarah Sharp
5374c68741SSarah Sharp /* USB Legacy Support Control and Status Register - section 7.1.2 */
5474c68741SSarah Sharp /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
5574c68741SSarah Sharp #define XHCI_LEGACY_CONTROL_OFFSET (0x04)
5695018a53SAlex He /* bits 1:3, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */
5795018a53SAlex He #define XHCI_LEGACY_DISABLE_SMI ((0x7 << 1) + (0xff << 5) + (0x7 << 17))
5895018a53SAlex He #define XHCI_LEGACY_SMI_EVENTS (0x7 << 29)
5974c68741SSarah Sharp
60fc71ff75SAndiry Xu /* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */
61fc71ff75SAndiry Xu #define XHCI_L1C (1 << 16)
62fc71ff75SAndiry Xu
63fc71ff75SAndiry Xu /* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */
64fc71ff75SAndiry Xu #define XHCI_HLC (1 << 19)
65dcf06a03SMathias Nyman #define XHCI_BLC (1 << 20)
66fc71ff75SAndiry Xu
6774c68741SSarah Sharp /* command register values to disable interrupts and halt the HC */
6874c68741SSarah Sharp /* start/stop HC execution - do not write unless HC is halted*/
6974c68741SSarah Sharp #define XHCI_CMD_RUN (1 << 0)
7074c68741SSarah Sharp /* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */
7174c68741SSarah Sharp #define XHCI_CMD_EIE (1 << 2)
7274c68741SSarah Sharp /* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */
7374c68741SSarah Sharp #define XHCI_CMD_HSEIE (1 << 3)
7474c68741SSarah Sharp /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
7574c68741SSarah Sharp #define XHCI_CMD_EWE (1 << 10)
7674c68741SSarah Sharp
7774c68741SSarah Sharp #define XHCI_IRQS (XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE)
7874c68741SSarah Sharp
7974c68741SSarah Sharp /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
8074c68741SSarah Sharp #define XHCI_STS_CNR (1 << 11)
8174c68741SSarah Sharp
8274c68741SSarah Sharp #include <linux/io.h>
8374c68741SSarah Sharp
8474c68741SSarah Sharp /**
8574c68741SSarah Sharp * Find the offset of the extended capabilities with capability ID id.
8674c68741SSarah Sharp *
8774c68741SSarah Sharp * @base PCI MMIO registers base address.
88d5ddcdf4SMathias Nyman * @start address at which to start looking, (0 or HCC_PARAMS to start at
89d5ddcdf4SMathias Nyman * beginning of list)
90d0a0fa9dSMathias Nyman * @id Extended capability ID to search for, or 0 for the next
91d0a0fa9dSMathias Nyman * capability
9274c68741SSarah Sharp *
93d5ddcdf4SMathias Nyman * Returns the offset of the next matching extended capability structure.
94d5ddcdf4SMathias Nyman * Some capabilities can occur several times, e.g., the XHCI_EXT_CAPS_PROTOCOL,
95d5ddcdf4SMathias Nyman * and this provides a way to find them all.
9674c68741SSarah Sharp */
97d5ddcdf4SMathias Nyman
xhci_find_next_ext_cap(void __iomem * base,u32 start,int id)98d5ddcdf4SMathias Nyman static inline int xhci_find_next_ext_cap(void __iomem *base, u32 start, int id)
9974c68741SSarah Sharp {
10074c68741SSarah Sharp u32 val;
101d5ddcdf4SMathias Nyman u32 next;
102d5ddcdf4SMathias Nyman u32 offset;
10374c68741SSarah Sharp
104d5ddcdf4SMathias Nyman offset = start;
105d5ddcdf4SMathias Nyman if (!start || start == XHCI_HCC_PARAMS_OFFSET) {
106d5ddcdf4SMathias Nyman val = readl(base + XHCI_HCC_PARAMS_OFFSET);
10789140fdaSJoe Lawrence if (val == ~0)
10889140fdaSJoe Lawrence return 0;
109d5ddcdf4SMathias Nyman offset = XHCI_HCC_EXT_CAPS(val) << 2;
110d5ddcdf4SMathias Nyman if (!offset)
111d5ddcdf4SMathias Nyman return 0;
112ec844817SFelipe Balbi }
113d5ddcdf4SMathias Nyman do {
114d5ddcdf4SMathias Nyman val = readl(base + offset);
11589140fdaSJoe Lawrence if (val == ~0)
11689140fdaSJoe Lawrence return 0;
117d0a0fa9dSMathias Nyman if (offset != start && (id == 0 || XHCI_EXT_CAPS_ID(val) == id))
118d5ddcdf4SMathias Nyman return offset;
119d5ddcdf4SMathias Nyman
120d5ddcdf4SMathias Nyman next = XHCI_EXT_CAPS_NEXT(val);
121d5ddcdf4SMathias Nyman offset += next << 2;
122d5ddcdf4SMathias Nyman } while (next);
123d5ddcdf4SMathias Nyman
12474c68741SSarah Sharp return 0;
12574c68741SSarah Sharp }
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