1 /* 2 * xHCI host controller driver 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include "xhci.h" 24 25 #define XHCI_INIT_VALUE 0x0 26 27 /* Add verbose debugging later, just print everything for now */ 28 29 void xhci_dbg_regs(struct xhci_hcd *xhci) 30 { 31 u32 temp; 32 33 xhci_dbg(xhci, "// xHCI capability registers at %p:\n", 34 xhci->cap_regs); 35 temp = readl(&xhci->cap_regs->hc_capbase); 36 xhci_dbg(xhci, "// @%p = 0x%x (CAPLENGTH AND HCIVERSION)\n", 37 &xhci->cap_regs->hc_capbase, temp); 38 xhci_dbg(xhci, "// CAPLENGTH: 0x%x\n", 39 (unsigned int) HC_LENGTH(temp)); 40 xhci_dbg(xhci, "// HCIVERSION: 0x%x\n", 41 (unsigned int) HC_VERSION(temp)); 42 43 xhci_dbg(xhci, "// xHCI operational registers at %p:\n", xhci->op_regs); 44 45 temp = readl(&xhci->cap_regs->run_regs_off); 46 xhci_dbg(xhci, "// @%p = 0x%x RTSOFF\n", 47 &xhci->cap_regs->run_regs_off, 48 (unsigned int) temp & RTSOFF_MASK); 49 xhci_dbg(xhci, "// xHCI runtime registers at %p:\n", xhci->run_regs); 50 51 temp = readl(&xhci->cap_regs->db_off); 52 xhci_dbg(xhci, "// @%p = 0x%x DBOFF\n", &xhci->cap_regs->db_off, temp); 53 xhci_dbg(xhci, "// Doorbell array at %p:\n", xhci->dba); 54 } 55 56 static void xhci_print_cap_regs(struct xhci_hcd *xhci) 57 { 58 u32 temp; 59 u32 hci_version; 60 61 xhci_dbg(xhci, "xHCI capability registers at %p:\n", xhci->cap_regs); 62 63 temp = readl(&xhci->cap_regs->hc_capbase); 64 hci_version = HC_VERSION(temp); 65 xhci_dbg(xhci, "CAPLENGTH AND HCIVERSION 0x%x:\n", 66 (unsigned int) temp); 67 xhci_dbg(xhci, "CAPLENGTH: 0x%x\n", 68 (unsigned int) HC_LENGTH(temp)); 69 xhci_dbg(xhci, "HCIVERSION: 0x%x\n", hci_version); 70 71 temp = readl(&xhci->cap_regs->hcs_params1); 72 xhci_dbg(xhci, "HCSPARAMS 1: 0x%x\n", 73 (unsigned int) temp); 74 xhci_dbg(xhci, " Max device slots: %u\n", 75 (unsigned int) HCS_MAX_SLOTS(temp)); 76 xhci_dbg(xhci, " Max interrupters: %u\n", 77 (unsigned int) HCS_MAX_INTRS(temp)); 78 xhci_dbg(xhci, " Max ports: %u\n", 79 (unsigned int) HCS_MAX_PORTS(temp)); 80 81 temp = readl(&xhci->cap_regs->hcs_params2); 82 xhci_dbg(xhci, "HCSPARAMS 2: 0x%x\n", 83 (unsigned int) temp); 84 xhci_dbg(xhci, " Isoc scheduling threshold: %u\n", 85 (unsigned int) HCS_IST(temp)); 86 xhci_dbg(xhci, " Maximum allowed segments in event ring: %u\n", 87 (unsigned int) HCS_ERST_MAX(temp)); 88 89 temp = readl(&xhci->cap_regs->hcs_params3); 90 xhci_dbg(xhci, "HCSPARAMS 3 0x%x:\n", 91 (unsigned int) temp); 92 xhci_dbg(xhci, " Worst case U1 device exit latency: %u\n", 93 (unsigned int) HCS_U1_LATENCY(temp)); 94 xhci_dbg(xhci, " Worst case U2 device exit latency: %u\n", 95 (unsigned int) HCS_U2_LATENCY(temp)); 96 97 temp = readl(&xhci->cap_regs->hcc_params); 98 xhci_dbg(xhci, "HCC PARAMS 0x%x:\n", (unsigned int) temp); 99 xhci_dbg(xhci, " HC generates %s bit addresses\n", 100 HCC_64BIT_ADDR(temp) ? "64" : "32"); 101 xhci_dbg(xhci, " HC %s Contiguous Frame ID Capability\n", 102 HCC_CFC(temp) ? "has" : "hasn't"); 103 xhci_dbg(xhci, " HC %s generate Stopped - Short Package event\n", 104 HCC_SPC(temp) ? "can" : "can't"); 105 /* FIXME */ 106 xhci_dbg(xhci, " FIXME: more HCCPARAMS debugging\n"); 107 108 temp = readl(&xhci->cap_regs->run_regs_off); 109 xhci_dbg(xhci, "RTSOFF 0x%x:\n", temp & RTSOFF_MASK); 110 111 /* xhci 1.1 controllers have the HCCPARAMS2 register */ 112 if (hci_version > 0x100) { 113 temp = readl(&xhci->cap_regs->hcc_params2); 114 xhci_dbg(xhci, "HCC PARAMS2 0x%x:\n", (unsigned int) temp); 115 xhci_dbg(xhci, " HC %s Force save context capability", 116 HCC2_FSC(temp) ? "supports" : "doesn't support"); 117 xhci_dbg(xhci, " HC %s Large ESIT Payload Capability", 118 HCC2_LEC(temp) ? "supports" : "doesn't support"); 119 xhci_dbg(xhci, " HC %s Extended TBC capability", 120 HCC2_ETC(temp) ? "supports" : "doesn't support"); 121 } 122 } 123 124 static void xhci_print_command_reg(struct xhci_hcd *xhci) 125 { 126 u32 temp; 127 128 temp = readl(&xhci->op_regs->command); 129 xhci_dbg(xhci, "USBCMD 0x%x:\n", temp); 130 xhci_dbg(xhci, " HC is %s\n", 131 (temp & CMD_RUN) ? "running" : "being stopped"); 132 xhci_dbg(xhci, " HC has %sfinished hard reset\n", 133 (temp & CMD_RESET) ? "not " : ""); 134 xhci_dbg(xhci, " Event Interrupts %s\n", 135 (temp & CMD_EIE) ? "enabled " : "disabled"); 136 xhci_dbg(xhci, " Host System Error Interrupts %s\n", 137 (temp & CMD_HSEIE) ? "enabled " : "disabled"); 138 xhci_dbg(xhci, " HC has %sfinished light reset\n", 139 (temp & CMD_LRESET) ? "not " : ""); 140 } 141 142 static void xhci_print_status(struct xhci_hcd *xhci) 143 { 144 u32 temp; 145 146 temp = readl(&xhci->op_regs->status); 147 xhci_dbg(xhci, "USBSTS 0x%x:\n", temp); 148 xhci_dbg(xhci, " Event ring is %sempty\n", 149 (temp & STS_EINT) ? "not " : ""); 150 xhci_dbg(xhci, " %sHost System Error\n", 151 (temp & STS_FATAL) ? "WARNING: " : "No "); 152 xhci_dbg(xhci, " HC is %s\n", 153 (temp & STS_HALT) ? "halted" : "running"); 154 } 155 156 static void xhci_print_op_regs(struct xhci_hcd *xhci) 157 { 158 xhci_dbg(xhci, "xHCI operational registers at %p:\n", xhci->op_regs); 159 xhci_print_command_reg(xhci); 160 xhci_print_status(xhci); 161 } 162 163 static void xhci_print_ports(struct xhci_hcd *xhci) 164 { 165 __le32 __iomem *addr; 166 int i, j; 167 int ports; 168 char *names[NUM_PORT_REGS] = { 169 "status", 170 "power", 171 "link", 172 "reserved", 173 }; 174 175 ports = HCS_MAX_PORTS(xhci->hcs_params1); 176 addr = &xhci->op_regs->port_status_base; 177 for (i = 0; i < ports; i++) { 178 for (j = 0; j < NUM_PORT_REGS; j++) { 179 xhci_dbg(xhci, "%p port %s reg = 0x%x\n", 180 addr, names[j], 181 (unsigned int) readl(addr)); 182 addr++; 183 } 184 } 185 } 186 187 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num) 188 { 189 struct xhci_intr_reg __iomem *ir_set = &xhci->run_regs->ir_set[set_num]; 190 void __iomem *addr; 191 u32 temp; 192 u64 temp_64; 193 194 addr = &ir_set->irq_pending; 195 temp = readl(addr); 196 if (temp == XHCI_INIT_VALUE) 197 return; 198 199 xhci_dbg(xhci, " %p: ir_set[%i]\n", ir_set, set_num); 200 201 xhci_dbg(xhci, " %p: ir_set.pending = 0x%x\n", addr, 202 (unsigned int)temp); 203 204 addr = &ir_set->irq_control; 205 temp = readl(addr); 206 xhci_dbg(xhci, " %p: ir_set.control = 0x%x\n", addr, 207 (unsigned int)temp); 208 209 addr = &ir_set->erst_size; 210 temp = readl(addr); 211 xhci_dbg(xhci, " %p: ir_set.erst_size = 0x%x\n", addr, 212 (unsigned int)temp); 213 214 addr = &ir_set->rsvd; 215 temp = readl(addr); 216 if (temp != XHCI_INIT_VALUE) 217 xhci_dbg(xhci, " WARN: %p: ir_set.rsvd = 0x%x\n", 218 addr, (unsigned int)temp); 219 220 addr = &ir_set->erst_base; 221 temp_64 = xhci_read_64(xhci, addr); 222 xhci_dbg(xhci, " %p: ir_set.erst_base = @%08llx\n", 223 addr, temp_64); 224 225 addr = &ir_set->erst_dequeue; 226 temp_64 = xhci_read_64(xhci, addr); 227 xhci_dbg(xhci, " %p: ir_set.erst_dequeue = @%08llx\n", 228 addr, temp_64); 229 } 230 231 void xhci_print_run_regs(struct xhci_hcd *xhci) 232 { 233 u32 temp; 234 int i; 235 236 xhci_dbg(xhci, "xHCI runtime registers at %p:\n", xhci->run_regs); 237 temp = readl(&xhci->run_regs->microframe_index); 238 xhci_dbg(xhci, " %p: Microframe index = 0x%x\n", 239 &xhci->run_regs->microframe_index, 240 (unsigned int) temp); 241 for (i = 0; i < 7; i++) { 242 temp = readl(&xhci->run_regs->rsvd[i]); 243 if (temp != XHCI_INIT_VALUE) 244 xhci_dbg(xhci, " WARN: %p: Rsvd[%i] = 0x%x\n", 245 &xhci->run_regs->rsvd[i], 246 i, (unsigned int) temp); 247 } 248 } 249 250 void xhci_print_registers(struct xhci_hcd *xhci) 251 { 252 xhci_print_cap_regs(xhci); 253 xhci_print_op_regs(xhci); 254 xhci_print_ports(xhci); 255 } 256 257 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst) 258 { 259 u64 addr = erst->erst_dma_addr; 260 int i; 261 struct xhci_erst_entry *entry; 262 263 for (i = 0; i < erst->num_entries; i++) { 264 entry = &erst->entries[i]; 265 xhci_dbg(xhci, "@%016llx %08x %08x %08x %08x\n", 266 addr, 267 lower_32_bits(le64_to_cpu(entry->seg_addr)), 268 upper_32_bits(le64_to_cpu(entry->seg_addr)), 269 le32_to_cpu(entry->seg_size), 270 le32_to_cpu(entry->rsvd)); 271 addr += sizeof(*entry); 272 } 273 } 274 275 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci) 276 { 277 u64 val; 278 279 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); 280 xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = @%08x\n", 281 lower_32_bits(val)); 282 xhci_dbg(xhci, "// xHC command ring deq ptr high bits = @%08x\n", 283 upper_32_bits(val)); 284 } 285 286 char *xhci_get_slot_state(struct xhci_hcd *xhci, 287 struct xhci_container_ctx *ctx) 288 { 289 struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx); 290 int state = GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)); 291 292 return xhci_slot_state_string(state); 293 } 294 295 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), 296 const char *fmt, ...) 297 { 298 struct va_format vaf; 299 va_list args; 300 301 va_start(args, fmt); 302 vaf.fmt = fmt; 303 vaf.va = &args; 304 xhci_dbg(xhci, "%pV\n", &vaf); 305 trace(&vaf); 306 va_end(args); 307 } 308 EXPORT_SYMBOL_GPL(xhci_dbg_trace); 309