1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include "xhci.h" 12 13 #define XHCI_INIT_VALUE 0x0 14 15 /* Add verbose debugging later, just print everything for now */ 16 17 void xhci_dbg_regs(struct xhci_hcd *xhci) 18 { 19 u32 temp; 20 21 xhci_dbg(xhci, "// xHCI capability registers at %p:\n", 22 xhci->cap_regs); 23 temp = readl(&xhci->cap_regs->hc_capbase); 24 xhci_dbg(xhci, "// @%p = 0x%x (CAPLENGTH AND HCIVERSION)\n", 25 &xhci->cap_regs->hc_capbase, temp); 26 xhci_dbg(xhci, "// CAPLENGTH: 0x%x\n", 27 (unsigned int) HC_LENGTH(temp)); 28 xhci_dbg(xhci, "// HCIVERSION: 0x%x\n", 29 (unsigned int) HC_VERSION(temp)); 30 31 xhci_dbg(xhci, "// xHCI operational registers at %p:\n", xhci->op_regs); 32 33 temp = readl(&xhci->cap_regs->run_regs_off); 34 xhci_dbg(xhci, "// @%p = 0x%x RTSOFF\n", 35 &xhci->cap_regs->run_regs_off, 36 (unsigned int) temp & RTSOFF_MASK); 37 xhci_dbg(xhci, "// xHCI runtime registers at %p:\n", xhci->run_regs); 38 39 temp = readl(&xhci->cap_regs->db_off); 40 xhci_dbg(xhci, "// @%p = 0x%x DBOFF\n", &xhci->cap_regs->db_off, temp); 41 xhci_dbg(xhci, "// Doorbell array at %p:\n", xhci->dba); 42 } 43 44 static void xhci_print_cap_regs(struct xhci_hcd *xhci) 45 { 46 u32 temp; 47 u32 hci_version; 48 49 xhci_dbg(xhci, "xHCI capability registers at %p:\n", xhci->cap_regs); 50 51 temp = readl(&xhci->cap_regs->hc_capbase); 52 hci_version = HC_VERSION(temp); 53 xhci_dbg(xhci, "CAPLENGTH AND HCIVERSION 0x%x:\n", 54 (unsigned int) temp); 55 xhci_dbg(xhci, "CAPLENGTH: 0x%x\n", 56 (unsigned int) HC_LENGTH(temp)); 57 xhci_dbg(xhci, "HCIVERSION: 0x%x\n", hci_version); 58 59 temp = readl(&xhci->cap_regs->hcs_params1); 60 xhci_dbg(xhci, "HCSPARAMS 1: 0x%x\n", 61 (unsigned int) temp); 62 xhci_dbg(xhci, " Max device slots: %u\n", 63 (unsigned int) HCS_MAX_SLOTS(temp)); 64 xhci_dbg(xhci, " Max interrupters: %u\n", 65 (unsigned int) HCS_MAX_INTRS(temp)); 66 xhci_dbg(xhci, " Max ports: %u\n", 67 (unsigned int) HCS_MAX_PORTS(temp)); 68 69 temp = readl(&xhci->cap_regs->hcs_params2); 70 xhci_dbg(xhci, "HCSPARAMS 2: 0x%x\n", 71 (unsigned int) temp); 72 xhci_dbg(xhci, " Isoc scheduling threshold: %u\n", 73 (unsigned int) HCS_IST(temp)); 74 xhci_dbg(xhci, " Maximum allowed segments in event ring: %u\n", 75 (unsigned int) HCS_ERST_MAX(temp)); 76 77 temp = readl(&xhci->cap_regs->hcs_params3); 78 xhci_dbg(xhci, "HCSPARAMS 3 0x%x:\n", 79 (unsigned int) temp); 80 xhci_dbg(xhci, " Worst case U1 device exit latency: %u\n", 81 (unsigned int) HCS_U1_LATENCY(temp)); 82 xhci_dbg(xhci, " Worst case U2 device exit latency: %u\n", 83 (unsigned int) HCS_U2_LATENCY(temp)); 84 85 temp = readl(&xhci->cap_regs->hcc_params); 86 xhci_dbg(xhci, "HCC PARAMS 0x%x:\n", (unsigned int) temp); 87 xhci_dbg(xhci, " HC generates %s bit addresses\n", 88 HCC_64BIT_ADDR(temp) ? "64" : "32"); 89 xhci_dbg(xhci, " HC %s Contiguous Frame ID Capability\n", 90 HCC_CFC(temp) ? "has" : "hasn't"); 91 xhci_dbg(xhci, " HC %s generate Stopped - Short Package event\n", 92 HCC_SPC(temp) ? "can" : "can't"); 93 /* FIXME */ 94 xhci_dbg(xhci, " FIXME: more HCCPARAMS debugging\n"); 95 96 temp = readl(&xhci->cap_regs->run_regs_off); 97 xhci_dbg(xhci, "RTSOFF 0x%x:\n", temp & RTSOFF_MASK); 98 99 /* xhci 1.1 controllers have the HCCPARAMS2 register */ 100 if (hci_version > 0x100) { 101 temp = readl(&xhci->cap_regs->hcc_params2); 102 xhci_dbg(xhci, "HCC PARAMS2 0x%x:\n", (unsigned int) temp); 103 xhci_dbg(xhci, " HC %s Force save context capability", 104 HCC2_FSC(temp) ? "supports" : "doesn't support"); 105 xhci_dbg(xhci, " HC %s Large ESIT Payload Capability", 106 HCC2_LEC(temp) ? "supports" : "doesn't support"); 107 xhci_dbg(xhci, " HC %s Extended TBC capability", 108 HCC2_ETC(temp) ? "supports" : "doesn't support"); 109 } 110 } 111 112 static void xhci_print_command_reg(struct xhci_hcd *xhci) 113 { 114 u32 temp; 115 116 temp = readl(&xhci->op_regs->command); 117 xhci_dbg(xhci, "USBCMD 0x%x:\n", temp); 118 xhci_dbg(xhci, " HC is %s\n", 119 (temp & CMD_RUN) ? "running" : "being stopped"); 120 xhci_dbg(xhci, " HC has %sfinished hard reset\n", 121 (temp & CMD_RESET) ? "not " : ""); 122 xhci_dbg(xhci, " Event Interrupts %s\n", 123 (temp & CMD_EIE) ? "enabled " : "disabled"); 124 xhci_dbg(xhci, " Host System Error Interrupts %s\n", 125 (temp & CMD_HSEIE) ? "enabled " : "disabled"); 126 xhci_dbg(xhci, " HC has %sfinished light reset\n", 127 (temp & CMD_LRESET) ? "not " : ""); 128 } 129 130 static void xhci_print_status(struct xhci_hcd *xhci) 131 { 132 u32 temp; 133 134 temp = readl(&xhci->op_regs->status); 135 xhci_dbg(xhci, "USBSTS 0x%x:\n", temp); 136 xhci_dbg(xhci, " Event ring is %sempty\n", 137 (temp & STS_EINT) ? "not " : ""); 138 xhci_dbg(xhci, " %sHost System Error\n", 139 (temp & STS_FATAL) ? "WARNING: " : "No "); 140 xhci_dbg(xhci, " HC is %s\n", 141 (temp & STS_HALT) ? "halted" : "running"); 142 } 143 144 static void xhci_print_op_regs(struct xhci_hcd *xhci) 145 { 146 xhci_dbg(xhci, "xHCI operational registers at %p:\n", xhci->op_regs); 147 xhci_print_command_reg(xhci); 148 xhci_print_status(xhci); 149 } 150 151 static void xhci_print_ports(struct xhci_hcd *xhci) 152 { 153 __le32 __iomem *addr; 154 int i, j; 155 int ports; 156 char *names[NUM_PORT_REGS] = { 157 "status", 158 "power", 159 "link", 160 "reserved", 161 }; 162 163 ports = HCS_MAX_PORTS(xhci->hcs_params1); 164 addr = &xhci->op_regs->port_status_base; 165 for (i = 0; i < ports; i++) { 166 for (j = 0; j < NUM_PORT_REGS; j++) { 167 xhci_dbg(xhci, "%p port %s reg = 0x%x\n", 168 addr, names[j], 169 (unsigned int) readl(addr)); 170 addr++; 171 } 172 } 173 } 174 175 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num) 176 { 177 struct xhci_intr_reg __iomem *ir_set = &xhci->run_regs->ir_set[set_num]; 178 void __iomem *addr; 179 u32 temp; 180 u64 temp_64; 181 182 addr = &ir_set->irq_pending; 183 temp = readl(addr); 184 if (temp == XHCI_INIT_VALUE) 185 return; 186 187 xhci_dbg(xhci, " %p: ir_set[%i]\n", ir_set, set_num); 188 189 xhci_dbg(xhci, " %p: ir_set.pending = 0x%x\n", addr, 190 (unsigned int)temp); 191 192 addr = &ir_set->irq_control; 193 temp = readl(addr); 194 xhci_dbg(xhci, " %p: ir_set.control = 0x%x\n", addr, 195 (unsigned int)temp); 196 197 addr = &ir_set->erst_size; 198 temp = readl(addr); 199 xhci_dbg(xhci, " %p: ir_set.erst_size = 0x%x\n", addr, 200 (unsigned int)temp); 201 202 addr = &ir_set->rsvd; 203 temp = readl(addr); 204 if (temp != XHCI_INIT_VALUE) 205 xhci_dbg(xhci, " WARN: %p: ir_set.rsvd = 0x%x\n", 206 addr, (unsigned int)temp); 207 208 addr = &ir_set->erst_base; 209 temp_64 = xhci_read_64(xhci, addr); 210 xhci_dbg(xhci, " %p: ir_set.erst_base = @%08llx\n", 211 addr, temp_64); 212 213 addr = &ir_set->erst_dequeue; 214 temp_64 = xhci_read_64(xhci, addr); 215 xhci_dbg(xhci, " %p: ir_set.erst_dequeue = @%08llx\n", 216 addr, temp_64); 217 } 218 219 void xhci_print_run_regs(struct xhci_hcd *xhci) 220 { 221 u32 temp; 222 int i; 223 224 xhci_dbg(xhci, "xHCI runtime registers at %p:\n", xhci->run_regs); 225 temp = readl(&xhci->run_regs->microframe_index); 226 xhci_dbg(xhci, " %p: Microframe index = 0x%x\n", 227 &xhci->run_regs->microframe_index, 228 (unsigned int) temp); 229 for (i = 0; i < 7; i++) { 230 temp = readl(&xhci->run_regs->rsvd[i]); 231 if (temp != XHCI_INIT_VALUE) 232 xhci_dbg(xhci, " WARN: %p: Rsvd[%i] = 0x%x\n", 233 &xhci->run_regs->rsvd[i], 234 i, (unsigned int) temp); 235 } 236 } 237 238 void xhci_print_registers(struct xhci_hcd *xhci) 239 { 240 xhci_print_cap_regs(xhci); 241 xhci_print_op_regs(xhci); 242 xhci_print_ports(xhci); 243 } 244 245 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst) 246 { 247 u64 addr = erst->erst_dma_addr; 248 int i; 249 struct xhci_erst_entry *entry; 250 251 for (i = 0; i < erst->num_entries; i++) { 252 entry = &erst->entries[i]; 253 xhci_dbg(xhci, "@%016llx %08x %08x %08x %08x\n", 254 addr, 255 lower_32_bits(le64_to_cpu(entry->seg_addr)), 256 upper_32_bits(le64_to_cpu(entry->seg_addr)), 257 le32_to_cpu(entry->seg_size), 258 le32_to_cpu(entry->rsvd)); 259 addr += sizeof(*entry); 260 } 261 } 262 263 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci) 264 { 265 u64 val; 266 267 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); 268 xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = @%08x\n", 269 lower_32_bits(val)); 270 xhci_dbg(xhci, "// xHC command ring deq ptr high bits = @%08x\n", 271 upper_32_bits(val)); 272 } 273 274 char *xhci_get_slot_state(struct xhci_hcd *xhci, 275 struct xhci_container_ctx *ctx) 276 { 277 struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx); 278 int state = GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)); 279 280 return xhci_slot_state_string(state); 281 } 282 283 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), 284 const char *fmt, ...) 285 { 286 struct va_format vaf; 287 va_list args; 288 289 va_start(args, fmt); 290 vaf.fmt = fmt; 291 vaf.va = &args; 292 xhci_dbg(xhci, "%pV\n", &vaf); 293 trace(&vaf); 294 va_end(args); 295 } 296 EXPORT_SYMBOL_GPL(xhci_dbg_trace); 297