1 /* 2 * Universal Host Controller Interface driver for USB. 3 * 4 * Maintainer: Alan Stern <stern@rowland.harvard.edu> 5 * 6 * (C) Copyright 1999 Linus Torvalds 7 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com 8 * (C) Copyright 1999 Randy Dunlap 9 * (C) Copyright 1999 Georg Acher, acher@in.tum.de 10 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de 11 * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch 12 * (C) Copyright 2004 Alan Stern, stern@rowland.harvard.edu 13 */ 14 15 static const __u8 root_hub_hub_des[] = 16 { 17 0x09, /* __u8 bLength; */ 18 USB_DT_HUB, /* __u8 bDescriptorType; Hub-descriptor */ 19 0x02, /* __u8 bNbrPorts; */ 20 HUB_CHAR_NO_LPSM | /* __u16 wHubCharacteristics; */ 21 HUB_CHAR_INDV_PORT_OCPM, /* (per-port OC, no power switching) */ 22 0x00, 23 0x01, /* __u8 bPwrOn2pwrGood; 2ms */ 24 0x00, /* __u8 bHubContrCurrent; 0 mA */ 25 0x00, /* __u8 DeviceRemovable; *** 7 Ports max */ 26 0xff /* __u8 PortPwrCtrlMask; *** 7 ports max */ 27 }; 28 29 #define UHCI_RH_MAXCHILD 7 30 31 /* must write as zeroes */ 32 #define WZ_BITS (USBPORTSC_RES2 | USBPORTSC_RES3 | USBPORTSC_RES4) 33 34 /* status change bits: nonzero writes will clear */ 35 #define RWC_BITS (USBPORTSC_OCC | USBPORTSC_PEC | USBPORTSC_CSC) 36 37 /* suspend/resume bits: port suspended or port resuming */ 38 #define SUSPEND_BITS (USBPORTSC_SUSP | USBPORTSC_RD) 39 40 /* A port that either is connected or has a changed-bit set will prevent 41 * us from AUTO_STOPPING. 42 */ 43 static int any_ports_active(struct uhci_hcd *uhci) 44 { 45 int port; 46 47 for (port = 0; port < uhci->rh_numports; ++port) { 48 if ((uhci_readw(uhci, USBPORTSC1 + port * 2) & 49 (USBPORTSC_CCS | RWC_BITS)) || 50 test_bit(port, &uhci->port_c_suspend)) 51 return 1; 52 } 53 return 0; 54 } 55 56 static inline int get_hub_status_data(struct uhci_hcd *uhci, char *buf) 57 { 58 int port; 59 int mask = RWC_BITS; 60 61 /* Some boards (both VIA and Intel apparently) report bogus 62 * overcurrent indications, causing massive log spam unless 63 * we completely ignore them. This doesn't seem to be a problem 64 * with the chipset so much as with the way it is connected on 65 * the motherboard; if the overcurrent input is left to float 66 * then it may constantly register false positives. */ 67 if (ignore_oc) 68 mask &= ~USBPORTSC_OCC; 69 70 *buf = 0; 71 for (port = 0; port < uhci->rh_numports; ++port) { 72 if ((uhci_readw(uhci, USBPORTSC1 + port * 2) & mask) || 73 test_bit(port, &uhci->port_c_suspend)) 74 *buf |= (1 << (port + 1)); 75 } 76 return !!*buf; 77 } 78 79 #define CLR_RH_PORTSTAT(x) \ 80 status = uhci_readw(uhci, port_addr); \ 81 status &= ~(RWC_BITS|WZ_BITS); \ 82 status &= ~(x); \ 83 status |= RWC_BITS & (x); \ 84 uhci_writew(uhci, status, port_addr) 85 86 #define SET_RH_PORTSTAT(x) \ 87 status = uhci_readw(uhci, port_addr); \ 88 status |= (x); \ 89 status &= ~(RWC_BITS|WZ_BITS); \ 90 uhci_writew(uhci, status, port_addr) 91 92 /* UHCI controllers don't automatically stop resume signalling after 20 msec, 93 * so we have to poll and check timeouts in order to take care of it. 94 */ 95 static void uhci_finish_suspend(struct uhci_hcd *uhci, int port, 96 unsigned long port_addr) 97 { 98 int status; 99 int i; 100 101 if (uhci_readw(uhci, port_addr) & SUSPEND_BITS) { 102 CLR_RH_PORTSTAT(SUSPEND_BITS); 103 if (test_bit(port, &uhci->resuming_ports)) 104 set_bit(port, &uhci->port_c_suspend); 105 106 /* The controller won't actually turn off the RD bit until 107 * it has had a chance to send a low-speed EOP sequence, 108 * which is supposed to take 3 bit times (= 2 microseconds). 109 * Experiments show that some controllers take longer, so 110 * we'll poll for completion. */ 111 for (i = 0; i < 10; ++i) { 112 if (!(uhci_readw(uhci, port_addr) & SUSPEND_BITS)) 113 break; 114 udelay(1); 115 } 116 } 117 clear_bit(port, &uhci->resuming_ports); 118 usb_hcd_end_port_resume(&uhci_to_hcd(uhci)->self, port); 119 } 120 121 /* Wait for the UHCI controller in HP's iLO2 server management chip. 122 * It can take up to 250 us to finish a reset and set the CSC bit. 123 */ 124 static void wait_for_HP(struct uhci_hcd *uhci, unsigned long port_addr) 125 { 126 int i; 127 128 for (i = 10; i < 250; i += 10) { 129 if (uhci_readw(uhci, port_addr) & USBPORTSC_CSC) 130 return; 131 udelay(10); 132 } 133 /* Log a warning? */ 134 } 135 136 static void uhci_check_ports(struct uhci_hcd *uhci) 137 { 138 unsigned int port; 139 unsigned long port_addr; 140 int status; 141 142 for (port = 0; port < uhci->rh_numports; ++port) { 143 port_addr = USBPORTSC1 + 2 * port; 144 status = uhci_readw(uhci, port_addr); 145 if (unlikely(status & USBPORTSC_PR)) { 146 if (time_after_eq(jiffies, uhci->ports_timeout)) { 147 CLR_RH_PORTSTAT(USBPORTSC_PR); 148 udelay(10); 149 150 /* HP's server management chip requires 151 * a longer delay. */ 152 if (uhci->wait_for_hp) 153 wait_for_HP(uhci, port_addr); 154 155 /* If the port was enabled before, turning 156 * reset on caused a port enable change. 157 * Turning reset off causes a port connect 158 * status change. Clear these changes. */ 159 CLR_RH_PORTSTAT(USBPORTSC_CSC | USBPORTSC_PEC); 160 SET_RH_PORTSTAT(USBPORTSC_PE); 161 } 162 } 163 if (unlikely(status & USBPORTSC_RD)) { 164 if (!test_bit(port, &uhci->resuming_ports)) { 165 166 /* Port received a wakeup request */ 167 set_bit(port, &uhci->resuming_ports); 168 uhci->ports_timeout = jiffies + 169 msecs_to_jiffies(USB_RESUME_TIMEOUT); 170 usb_hcd_start_port_resume( 171 &uhci_to_hcd(uhci)->self, port); 172 173 /* Make sure we see the port again 174 * after the resuming period is over. */ 175 mod_timer(&uhci_to_hcd(uhci)->rh_timer, 176 uhci->ports_timeout); 177 } else if (time_after_eq(jiffies, 178 uhci->ports_timeout)) { 179 uhci_finish_suspend(uhci, port, port_addr); 180 } 181 } 182 } 183 } 184 185 static int uhci_hub_status_data(struct usb_hcd *hcd, char *buf) 186 { 187 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 188 unsigned long flags; 189 int status = 0; 190 191 spin_lock_irqsave(&uhci->lock, flags); 192 193 uhci_scan_schedule(uhci); 194 if (!HCD_HW_ACCESSIBLE(hcd) || uhci->dead) 195 goto done; 196 uhci_check_ports(uhci); 197 198 status = get_hub_status_data(uhci, buf); 199 200 switch (uhci->rh_state) { 201 case UHCI_RH_SUSPENDED: 202 /* if port change, ask to be resumed */ 203 if (status || uhci->resuming_ports) { 204 status = 1; 205 usb_hcd_resume_root_hub(hcd); 206 } 207 break; 208 209 case UHCI_RH_AUTO_STOPPED: 210 /* if port change, auto start */ 211 if (status) 212 wakeup_rh(uhci); 213 break; 214 215 case UHCI_RH_RUNNING: 216 /* are any devices attached? */ 217 if (!any_ports_active(uhci)) { 218 uhci->rh_state = UHCI_RH_RUNNING_NODEVS; 219 uhci->auto_stop_time = jiffies + HZ; 220 } 221 break; 222 223 case UHCI_RH_RUNNING_NODEVS: 224 /* auto-stop if nothing connected for 1 second */ 225 if (any_ports_active(uhci)) 226 uhci->rh_state = UHCI_RH_RUNNING; 227 else if (time_after_eq(jiffies, uhci->auto_stop_time) && 228 !uhci->wait_for_hp) 229 suspend_rh(uhci, UHCI_RH_AUTO_STOPPED); 230 break; 231 232 default: 233 break; 234 } 235 236 done: 237 spin_unlock_irqrestore(&uhci->lock, flags); 238 return status; 239 } 240 241 /* size of returned buffer is part of USB spec */ 242 static int uhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 243 u16 wIndex, char *buf, u16 wLength) 244 { 245 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 246 int status, lstatus, retval = 0; 247 unsigned int port = wIndex - 1; 248 unsigned long port_addr = USBPORTSC1 + 2 * port; 249 u16 wPortChange, wPortStatus; 250 unsigned long flags; 251 252 if (!HCD_HW_ACCESSIBLE(hcd) || uhci->dead) 253 return -ETIMEDOUT; 254 255 spin_lock_irqsave(&uhci->lock, flags); 256 switch (typeReq) { 257 258 case GetHubStatus: 259 *(__le32 *)buf = cpu_to_le32(0); 260 retval = 4; /* hub power */ 261 break; 262 case GetPortStatus: 263 if (port >= uhci->rh_numports) 264 goto err; 265 266 uhci_check_ports(uhci); 267 status = uhci_readw(uhci, port_addr); 268 269 /* Intel controllers report the OverCurrent bit active on. 270 * VIA controllers report it active off, so we'll adjust the 271 * bit value. (It's not standardized in the UHCI spec.) 272 */ 273 if (uhci->oc_low) 274 status ^= USBPORTSC_OC; 275 276 /* UHCI doesn't support C_RESET (always false) */ 277 wPortChange = lstatus = 0; 278 if (status & USBPORTSC_CSC) 279 wPortChange |= USB_PORT_STAT_C_CONNECTION; 280 if (status & USBPORTSC_PEC) 281 wPortChange |= USB_PORT_STAT_C_ENABLE; 282 if ((status & USBPORTSC_OCC) && !ignore_oc) 283 wPortChange |= USB_PORT_STAT_C_OVERCURRENT; 284 285 if (test_bit(port, &uhci->port_c_suspend)) { 286 wPortChange |= USB_PORT_STAT_C_SUSPEND; 287 lstatus |= 1; 288 } 289 if (test_bit(port, &uhci->resuming_ports)) 290 lstatus |= 4; 291 292 /* UHCI has no power switching (always on) */ 293 wPortStatus = USB_PORT_STAT_POWER; 294 if (status & USBPORTSC_CCS) 295 wPortStatus |= USB_PORT_STAT_CONNECTION; 296 if (status & USBPORTSC_PE) { 297 wPortStatus |= USB_PORT_STAT_ENABLE; 298 if (status & SUSPEND_BITS) 299 wPortStatus |= USB_PORT_STAT_SUSPEND; 300 } 301 if (status & USBPORTSC_OC) 302 wPortStatus |= USB_PORT_STAT_OVERCURRENT; 303 if (status & USBPORTSC_PR) 304 wPortStatus |= USB_PORT_STAT_RESET; 305 if (status & USBPORTSC_LSDA) 306 wPortStatus |= USB_PORT_STAT_LOW_SPEED; 307 308 if (wPortChange) 309 dev_dbg(uhci_dev(uhci), "port %d portsc %04x,%02x\n", 310 wIndex, status, lstatus); 311 312 *(__le16 *)buf = cpu_to_le16(wPortStatus); 313 *(__le16 *)(buf + 2) = cpu_to_le16(wPortChange); 314 retval = 4; 315 break; 316 case SetHubFeature: /* We don't implement these */ 317 case ClearHubFeature: 318 switch (wValue) { 319 case C_HUB_OVER_CURRENT: 320 case C_HUB_LOCAL_POWER: 321 break; 322 default: 323 goto err; 324 } 325 break; 326 case SetPortFeature: 327 if (port >= uhci->rh_numports) 328 goto err; 329 330 switch (wValue) { 331 case USB_PORT_FEAT_SUSPEND: 332 SET_RH_PORTSTAT(USBPORTSC_SUSP); 333 break; 334 case USB_PORT_FEAT_RESET: 335 SET_RH_PORTSTAT(USBPORTSC_PR); 336 337 /* Reset terminates Resume signalling */ 338 uhci_finish_suspend(uhci, port, port_addr); 339 340 /* USB v2.0 7.1.7.5 */ 341 uhci->ports_timeout = jiffies + 342 msecs_to_jiffies(USB_RESUME_TIMEOUT); 343 break; 344 case USB_PORT_FEAT_POWER: 345 /* UHCI has no power switching */ 346 break; 347 default: 348 goto err; 349 } 350 break; 351 case ClearPortFeature: 352 if (port >= uhci->rh_numports) 353 goto err; 354 355 switch (wValue) { 356 case USB_PORT_FEAT_ENABLE: 357 CLR_RH_PORTSTAT(USBPORTSC_PE); 358 359 /* Disable terminates Resume signalling */ 360 uhci_finish_suspend(uhci, port, port_addr); 361 break; 362 case USB_PORT_FEAT_C_ENABLE: 363 CLR_RH_PORTSTAT(USBPORTSC_PEC); 364 break; 365 case USB_PORT_FEAT_SUSPEND: 366 if (!(uhci_readw(uhci, port_addr) & USBPORTSC_SUSP)) { 367 368 /* Make certain the port isn't suspended */ 369 uhci_finish_suspend(uhci, port, port_addr); 370 } else if (!test_and_set_bit(port, 371 &uhci->resuming_ports)) { 372 SET_RH_PORTSTAT(USBPORTSC_RD); 373 374 /* The controller won't allow RD to be set 375 * if the port is disabled. When this happens 376 * just skip the Resume signalling. 377 */ 378 if (!(uhci_readw(uhci, port_addr) & 379 USBPORTSC_RD)) 380 uhci_finish_suspend(uhci, port, 381 port_addr); 382 else 383 /* USB v2.0 7.1.7.7 */ 384 uhci->ports_timeout = jiffies + 385 msecs_to_jiffies(20); 386 } 387 break; 388 case USB_PORT_FEAT_C_SUSPEND: 389 clear_bit(port, &uhci->port_c_suspend); 390 break; 391 case USB_PORT_FEAT_POWER: 392 /* UHCI has no power switching */ 393 goto err; 394 case USB_PORT_FEAT_C_CONNECTION: 395 CLR_RH_PORTSTAT(USBPORTSC_CSC); 396 break; 397 case USB_PORT_FEAT_C_OVER_CURRENT: 398 CLR_RH_PORTSTAT(USBPORTSC_OCC); 399 break; 400 case USB_PORT_FEAT_C_RESET: 401 /* this driver won't report these */ 402 break; 403 default: 404 goto err; 405 } 406 break; 407 case GetHubDescriptor: 408 retval = min_t(unsigned int, sizeof(root_hub_hub_des), wLength); 409 memcpy(buf, root_hub_hub_des, retval); 410 if (retval > 2) 411 buf[2] = uhci->rh_numports; 412 break; 413 default: 414 err: 415 retval = -EPIPE; 416 } 417 spin_unlock_irqrestore(&uhci->lock, flags); 418 419 return retval; 420 } 421