1 /* 2 * Universal Host Controller Interface driver for USB. 3 * 4 * Maintainer: Alan Stern <stern@rowland.harvard.edu> 5 * 6 * (C) Copyright 1999 Linus Torvalds 7 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com 8 * (C) Copyright 1999 Randy Dunlap 9 * (C) Copyright 1999 Georg Acher, acher@in.tum.de 10 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de 11 * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch 12 * (C) Copyright 2004 Alan Stern, stern@rowland.harvard.edu 13 */ 14 15 static const __u8 root_hub_hub_des[] = 16 { 17 0x09, /* __u8 bLength; */ 18 0x29, /* __u8 bDescriptorType; Hub-descriptor */ 19 0x02, /* __u8 bNbrPorts; */ 20 0x0a, /* __u16 wHubCharacteristics; */ 21 0x00, /* (per-port OC, no power switching) */ 22 0x01, /* __u8 bPwrOn2pwrGood; 2ms */ 23 0x00, /* __u8 bHubContrCurrent; 0 mA */ 24 0x00, /* __u8 DeviceRemovable; *** 7 Ports max */ 25 0xff /* __u8 PortPwrCtrlMask; *** 7 ports max */ 26 }; 27 28 #define UHCI_RH_MAXCHILD 7 29 30 /* must write as zeroes */ 31 #define WZ_BITS (USBPORTSC_RES2 | USBPORTSC_RES3 | USBPORTSC_RES4) 32 33 /* status change bits: nonzero writes will clear */ 34 #define RWC_BITS (USBPORTSC_OCC | USBPORTSC_PEC | USBPORTSC_CSC) 35 36 /* suspend/resume bits: port suspended or port resuming */ 37 #define SUSPEND_BITS (USBPORTSC_SUSP | USBPORTSC_RD) 38 39 /* A port that either is connected or has a changed-bit set will prevent 40 * us from AUTO_STOPPING. 41 */ 42 static int any_ports_active(struct uhci_hcd *uhci) 43 { 44 int port; 45 46 for (port = 0; port < uhci->rh_numports; ++port) { 47 if ((uhci_readw(uhci, USBPORTSC1 + port * 2) & 48 (USBPORTSC_CCS | RWC_BITS)) || 49 test_bit(port, &uhci->port_c_suspend)) 50 return 1; 51 } 52 return 0; 53 } 54 55 static inline int get_hub_status_data(struct uhci_hcd *uhci, char *buf) 56 { 57 int port; 58 int mask = RWC_BITS; 59 60 /* Some boards (both VIA and Intel apparently) report bogus 61 * overcurrent indications, causing massive log spam unless 62 * we completely ignore them. This doesn't seem to be a problem 63 * with the chipset so much as with the way it is connected on 64 * the motherboard; if the overcurrent input is left to float 65 * then it may constantly register false positives. */ 66 if (ignore_oc) 67 mask &= ~USBPORTSC_OCC; 68 69 *buf = 0; 70 for (port = 0; port < uhci->rh_numports; ++port) { 71 if ((uhci_readw(uhci, USBPORTSC1 + port * 2) & mask) || 72 test_bit(port, &uhci->port_c_suspend)) 73 *buf |= (1 << (port + 1)); 74 } 75 return !!*buf; 76 } 77 78 #define CLR_RH_PORTSTAT(x) \ 79 status = uhci_readw(uhci, port_addr); \ 80 status &= ~(RWC_BITS|WZ_BITS); \ 81 status &= ~(x); \ 82 status |= RWC_BITS & (x); \ 83 uhci_writew(uhci, status, port_addr) 84 85 #define SET_RH_PORTSTAT(x) \ 86 status = uhci_readw(uhci, port_addr); \ 87 status |= (x); \ 88 status &= ~(RWC_BITS|WZ_BITS); \ 89 uhci_writew(uhci, status, port_addr) 90 91 /* UHCI controllers don't automatically stop resume signalling after 20 msec, 92 * so we have to poll and check timeouts in order to take care of it. 93 */ 94 static void uhci_finish_suspend(struct uhci_hcd *uhci, int port, 95 unsigned long port_addr) 96 { 97 int status; 98 int i; 99 100 if (uhci_readw(uhci, port_addr) & SUSPEND_BITS) { 101 CLR_RH_PORTSTAT(SUSPEND_BITS); 102 if (test_bit(port, &uhci->resuming_ports)) 103 set_bit(port, &uhci->port_c_suspend); 104 105 /* The controller won't actually turn off the RD bit until 106 * it has had a chance to send a low-speed EOP sequence, 107 * which is supposed to take 3 bit times (= 2 microseconds). 108 * Experiments show that some controllers take longer, so 109 * we'll poll for completion. */ 110 for (i = 0; i < 10; ++i) { 111 if (!(uhci_readw(uhci, port_addr) & SUSPEND_BITS)) 112 break; 113 udelay(1); 114 } 115 } 116 clear_bit(port, &uhci->resuming_ports); 117 usb_hcd_end_port_resume(&uhci_to_hcd(uhci)->self, port); 118 } 119 120 /* Wait for the UHCI controller in HP's iLO2 server management chip. 121 * It can take up to 250 us to finish a reset and set the CSC bit. 122 */ 123 static void wait_for_HP(struct uhci_hcd *uhci, unsigned long port_addr) 124 { 125 int i; 126 127 for (i = 10; i < 250; i += 10) { 128 if (uhci_readw(uhci, port_addr) & USBPORTSC_CSC) 129 return; 130 udelay(10); 131 } 132 /* Log a warning? */ 133 } 134 135 static void uhci_check_ports(struct uhci_hcd *uhci) 136 { 137 unsigned int port; 138 unsigned long port_addr; 139 int status; 140 141 for (port = 0; port < uhci->rh_numports; ++port) { 142 port_addr = USBPORTSC1 + 2 * port; 143 status = uhci_readw(uhci, port_addr); 144 if (unlikely(status & USBPORTSC_PR)) { 145 if (time_after_eq(jiffies, uhci->ports_timeout)) { 146 CLR_RH_PORTSTAT(USBPORTSC_PR); 147 udelay(10); 148 149 /* HP's server management chip requires 150 * a longer delay. */ 151 if (uhci->wait_for_hp) 152 wait_for_HP(uhci, port_addr); 153 154 /* If the port was enabled before, turning 155 * reset on caused a port enable change. 156 * Turning reset off causes a port connect 157 * status change. Clear these changes. */ 158 CLR_RH_PORTSTAT(USBPORTSC_CSC | USBPORTSC_PEC); 159 SET_RH_PORTSTAT(USBPORTSC_PE); 160 } 161 } 162 if (unlikely(status & USBPORTSC_RD)) { 163 if (!test_bit(port, &uhci->resuming_ports)) { 164 165 /* Port received a wakeup request */ 166 set_bit(port, &uhci->resuming_ports); 167 uhci->ports_timeout = jiffies + 168 msecs_to_jiffies(25); 169 usb_hcd_start_port_resume( 170 &uhci_to_hcd(uhci)->self, port); 171 172 /* Make sure we see the port again 173 * after the resuming period is over. */ 174 mod_timer(&uhci_to_hcd(uhci)->rh_timer, 175 uhci->ports_timeout); 176 } else if (time_after_eq(jiffies, 177 uhci->ports_timeout)) { 178 uhci_finish_suspend(uhci, port, port_addr); 179 } 180 } 181 } 182 } 183 184 static int uhci_hub_status_data(struct usb_hcd *hcd, char *buf) 185 { 186 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 187 unsigned long flags; 188 int status = 0; 189 190 spin_lock_irqsave(&uhci->lock, flags); 191 192 uhci_scan_schedule(uhci); 193 if (!HCD_HW_ACCESSIBLE(hcd) || uhci->dead) 194 goto done; 195 uhci_check_ports(uhci); 196 197 status = get_hub_status_data(uhci, buf); 198 199 switch (uhci->rh_state) { 200 case UHCI_RH_SUSPENDED: 201 /* if port change, ask to be resumed */ 202 if (status || uhci->resuming_ports) { 203 status = 1; 204 usb_hcd_resume_root_hub(hcd); 205 } 206 break; 207 208 case UHCI_RH_AUTO_STOPPED: 209 /* if port change, auto start */ 210 if (status) 211 wakeup_rh(uhci); 212 break; 213 214 case UHCI_RH_RUNNING: 215 /* are any devices attached? */ 216 if (!any_ports_active(uhci)) { 217 uhci->rh_state = UHCI_RH_RUNNING_NODEVS; 218 uhci->auto_stop_time = jiffies + HZ; 219 } 220 break; 221 222 case UHCI_RH_RUNNING_NODEVS: 223 /* auto-stop if nothing connected for 1 second */ 224 if (any_ports_active(uhci)) 225 uhci->rh_state = UHCI_RH_RUNNING; 226 else if (time_after_eq(jiffies, uhci->auto_stop_time) && 227 !uhci->wait_for_hp) 228 suspend_rh(uhci, UHCI_RH_AUTO_STOPPED); 229 break; 230 231 default: 232 break; 233 } 234 235 done: 236 spin_unlock_irqrestore(&uhci->lock, flags); 237 return status; 238 } 239 240 /* size of returned buffer is part of USB spec */ 241 static int uhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 242 u16 wIndex, char *buf, u16 wLength) 243 { 244 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 245 int status, lstatus, retval = 0; 246 unsigned int port = wIndex - 1; 247 unsigned long port_addr = USBPORTSC1 + 2 * port; 248 u16 wPortChange, wPortStatus; 249 unsigned long flags; 250 251 if (!HCD_HW_ACCESSIBLE(hcd) || uhci->dead) 252 return -ETIMEDOUT; 253 254 spin_lock_irqsave(&uhci->lock, flags); 255 switch (typeReq) { 256 257 case GetHubStatus: 258 *(__le32 *)buf = cpu_to_le32(0); 259 retval = 4; /* hub power */ 260 break; 261 case GetPortStatus: 262 if (port >= uhci->rh_numports) 263 goto err; 264 265 uhci_check_ports(uhci); 266 status = uhci_readw(uhci, port_addr); 267 268 /* Intel controllers report the OverCurrent bit active on. 269 * VIA controllers report it active off, so we'll adjust the 270 * bit value. (It's not standardized in the UHCI spec.) 271 */ 272 if (uhci->oc_low) 273 status ^= USBPORTSC_OC; 274 275 /* UHCI doesn't support C_RESET (always false) */ 276 wPortChange = lstatus = 0; 277 if (status & USBPORTSC_CSC) 278 wPortChange |= USB_PORT_STAT_C_CONNECTION; 279 if (status & USBPORTSC_PEC) 280 wPortChange |= USB_PORT_STAT_C_ENABLE; 281 if ((status & USBPORTSC_OCC) && !ignore_oc) 282 wPortChange |= USB_PORT_STAT_C_OVERCURRENT; 283 284 if (test_bit(port, &uhci->port_c_suspend)) { 285 wPortChange |= USB_PORT_STAT_C_SUSPEND; 286 lstatus |= 1; 287 } 288 if (test_bit(port, &uhci->resuming_ports)) 289 lstatus |= 4; 290 291 /* UHCI has no power switching (always on) */ 292 wPortStatus = USB_PORT_STAT_POWER; 293 if (status & USBPORTSC_CCS) 294 wPortStatus |= USB_PORT_STAT_CONNECTION; 295 if (status & USBPORTSC_PE) { 296 wPortStatus |= USB_PORT_STAT_ENABLE; 297 if (status & SUSPEND_BITS) 298 wPortStatus |= USB_PORT_STAT_SUSPEND; 299 } 300 if (status & USBPORTSC_OC) 301 wPortStatus |= USB_PORT_STAT_OVERCURRENT; 302 if (status & USBPORTSC_PR) 303 wPortStatus |= USB_PORT_STAT_RESET; 304 if (status & USBPORTSC_LSDA) 305 wPortStatus |= USB_PORT_STAT_LOW_SPEED; 306 307 if (wPortChange) 308 dev_dbg(uhci_dev(uhci), "port %d portsc %04x,%02x\n", 309 wIndex, status, lstatus); 310 311 *(__le16 *)buf = cpu_to_le16(wPortStatus); 312 *(__le16 *)(buf + 2) = cpu_to_le16(wPortChange); 313 retval = 4; 314 break; 315 case SetHubFeature: /* We don't implement these */ 316 case ClearHubFeature: 317 switch (wValue) { 318 case C_HUB_OVER_CURRENT: 319 case C_HUB_LOCAL_POWER: 320 break; 321 default: 322 goto err; 323 } 324 break; 325 case SetPortFeature: 326 if (port >= uhci->rh_numports) 327 goto err; 328 329 switch (wValue) { 330 case USB_PORT_FEAT_SUSPEND: 331 SET_RH_PORTSTAT(USBPORTSC_SUSP); 332 break; 333 case USB_PORT_FEAT_RESET: 334 SET_RH_PORTSTAT(USBPORTSC_PR); 335 336 /* Reset terminates Resume signalling */ 337 uhci_finish_suspend(uhci, port, port_addr); 338 339 /* USB v2.0 7.1.7.5 */ 340 uhci->ports_timeout = jiffies + msecs_to_jiffies(50); 341 break; 342 case USB_PORT_FEAT_POWER: 343 /* UHCI has no power switching */ 344 break; 345 default: 346 goto err; 347 } 348 break; 349 case ClearPortFeature: 350 if (port >= uhci->rh_numports) 351 goto err; 352 353 switch (wValue) { 354 case USB_PORT_FEAT_ENABLE: 355 CLR_RH_PORTSTAT(USBPORTSC_PE); 356 357 /* Disable terminates Resume signalling */ 358 uhci_finish_suspend(uhci, port, port_addr); 359 break; 360 case USB_PORT_FEAT_C_ENABLE: 361 CLR_RH_PORTSTAT(USBPORTSC_PEC); 362 break; 363 case USB_PORT_FEAT_SUSPEND: 364 if (!(uhci_readw(uhci, port_addr) & USBPORTSC_SUSP)) { 365 366 /* Make certain the port isn't suspended */ 367 uhci_finish_suspend(uhci, port, port_addr); 368 } else if (!test_and_set_bit(port, 369 &uhci->resuming_ports)) { 370 SET_RH_PORTSTAT(USBPORTSC_RD); 371 372 /* The controller won't allow RD to be set 373 * if the port is disabled. When this happens 374 * just skip the Resume signalling. 375 */ 376 if (!(uhci_readw(uhci, port_addr) & 377 USBPORTSC_RD)) 378 uhci_finish_suspend(uhci, port, 379 port_addr); 380 else 381 /* USB v2.0 7.1.7.7 */ 382 uhci->ports_timeout = jiffies + 383 msecs_to_jiffies(20); 384 } 385 break; 386 case USB_PORT_FEAT_C_SUSPEND: 387 clear_bit(port, &uhci->port_c_suspend); 388 break; 389 case USB_PORT_FEAT_POWER: 390 /* UHCI has no power switching */ 391 goto err; 392 case USB_PORT_FEAT_C_CONNECTION: 393 CLR_RH_PORTSTAT(USBPORTSC_CSC); 394 break; 395 case USB_PORT_FEAT_C_OVER_CURRENT: 396 CLR_RH_PORTSTAT(USBPORTSC_OCC); 397 break; 398 case USB_PORT_FEAT_C_RESET: 399 /* this driver won't report these */ 400 break; 401 default: 402 goto err; 403 } 404 break; 405 case GetHubDescriptor: 406 retval = min_t(unsigned int, sizeof(root_hub_hub_des), wLength); 407 memcpy(buf, root_hub_hub_des, retval); 408 if (retval > 2) 409 buf[2] = uhci->rh_numports; 410 break; 411 default: 412 err: 413 retval = -EPIPE; 414 } 415 spin_unlock_irqrestore(&uhci->lock, flags); 416 417 return retval; 418 } 419