1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __LINUX_UHCI_HCD_H 3 #define __LINUX_UHCI_HCD_H 4 5 #include <linux/list.h> 6 #include <linux/usb.h> 7 8 #define usb_packetid(pipe) (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT) 9 #define PIPE_DEVEP_MASK 0x0007ff00 10 11 12 /* 13 * Universal Host Controller Interface data structures and defines 14 */ 15 16 /* Command register */ 17 #define USBCMD 0 18 #define USBCMD_RS 0x0001 /* Run/Stop */ 19 #define USBCMD_HCRESET 0x0002 /* Host reset */ 20 #define USBCMD_GRESET 0x0004 /* Global reset */ 21 #define USBCMD_EGSM 0x0008 /* Global Suspend Mode */ 22 #define USBCMD_FGR 0x0010 /* Force Global Resume */ 23 #define USBCMD_SWDBG 0x0020 /* SW Debug mode */ 24 #define USBCMD_CF 0x0040 /* Config Flag (sw only) */ 25 #define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */ 26 27 /* Status register */ 28 #define USBSTS 2 29 #define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */ 30 #define USBSTS_ERROR 0x0002 /* Interrupt due to error */ 31 #define USBSTS_RD 0x0004 /* Resume Detect */ 32 #define USBSTS_HSE 0x0008 /* Host System Error: PCI problems */ 33 #define USBSTS_HCPE 0x0010 /* Host Controller Process Error: 34 * the schedule is buggy */ 35 #define USBSTS_HCH 0x0020 /* HC Halted */ 36 37 /* Interrupt enable register */ 38 #define USBINTR 4 39 #define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */ 40 #define USBINTR_RESUME 0x0002 /* Resume interrupt enable */ 41 #define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */ 42 #define USBINTR_SP 0x0008 /* Short packet interrupt enable */ 43 44 #define USBFRNUM 6 45 #define USBFLBASEADD 8 46 #define USBSOF 12 47 #define USBSOF_DEFAULT 64 /* Frame length is exactly 1 ms */ 48 49 /* USB port status and control registers */ 50 #define USBPORTSC1 16 51 #define USBPORTSC2 18 52 #define USBPORTSC3 20 53 #define USBPORTSC4 22 54 #define USBPORTSC_CCS 0x0001 /* Current Connect Status 55 * ("device present") */ 56 #define USBPORTSC_CSC 0x0002 /* Connect Status Change */ 57 #define USBPORTSC_PE 0x0004 /* Port Enable */ 58 #define USBPORTSC_PEC 0x0008 /* Port Enable Change */ 59 #define USBPORTSC_DPLUS 0x0010 /* D+ high (line status) */ 60 #define USBPORTSC_DMINUS 0x0020 /* D- high (line status) */ 61 #define USBPORTSC_RD 0x0040 /* Resume Detect */ 62 #define USBPORTSC_RES1 0x0080 /* reserved, always 1 */ 63 #define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */ 64 #define USBPORTSC_PR 0x0200 /* Port Reset */ 65 /* OC and OCC from Intel 430TX and later (not UHCI 1.1d spec) */ 66 #define USBPORTSC_OC 0x0400 /* Over Current condition */ 67 #define USBPORTSC_OCC 0x0800 /* Over Current Change R/WC */ 68 #define USBPORTSC_SUSP 0x1000 /* Suspend */ 69 #define USBPORTSC_RES2 0x2000 /* reserved, write zeroes */ 70 #define USBPORTSC_RES3 0x4000 /* reserved, write zeroes */ 71 #define USBPORTSC_RES4 0x8000 /* reserved, write zeroes */ 72 73 /* PCI legacy support register */ 74 #define USBLEGSUP 0xc0 75 #define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */ 76 #define USBLEGSUP_RWC 0x8f00 /* the R/WC bits */ 77 #define USBLEGSUP_RO 0x5040 /* R/O and reserved bits */ 78 79 /* PCI Intel-specific resume-enable register */ 80 #define USBRES_INTEL 0xc4 81 #define USBPORT1EN 0x01 82 #define USBPORT2EN 0x02 83 84 #define UHCI_PTR_BITS(uhci) cpu_to_hc32((uhci), 0x000F) 85 #define UHCI_PTR_TERM(uhci) cpu_to_hc32((uhci), 0x0001) 86 #define UHCI_PTR_QH(uhci) cpu_to_hc32((uhci), 0x0002) 87 #define UHCI_PTR_DEPTH(uhci) cpu_to_hc32((uhci), 0x0004) 88 #define UHCI_PTR_BREADTH(uhci) cpu_to_hc32((uhci), 0x0000) 89 90 #define UHCI_NUMFRAMES 1024 /* in the frame list [array] */ 91 #define UHCI_MAX_SOF_NUMBER 2047 /* in an SOF packet */ 92 #define CAN_SCHEDULE_FRAMES 1000 /* how far in the future frames 93 * can be scheduled */ 94 #define MAX_PHASE 32 /* Periodic scheduling length */ 95 96 /* When no queues need Full-Speed Bandwidth Reclamation, 97 * delay this long before turning FSBR off */ 98 #define FSBR_OFF_DELAY msecs_to_jiffies(10) 99 100 /* If a queue hasn't advanced after this much time, assume it is stuck */ 101 #define QH_WAIT_TIMEOUT msecs_to_jiffies(200) 102 103 104 /* 105 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to 106 * __leXX (normally) or __beXX (given UHCI_BIG_ENDIAN_DESC), depending on 107 * the host controller implementation. 108 * 109 * To facilitate the strongest possible byte-order checking from "sparse" 110 * and so on, we use __leXX unless that's not practical. 111 */ 112 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_DESC 113 typedef __u32 __bitwise __hc32; 114 typedef __u16 __bitwise __hc16; 115 #else 116 #define __hc32 __le32 117 #define __hc16 __le16 118 #endif 119 120 /* 121 * Queue Headers 122 */ 123 124 /* 125 * One role of a QH is to hold a queue of TDs for some endpoint. One QH goes 126 * with each endpoint, and qh->element (updated by the HC) is either: 127 * - the next unprocessed TD in the endpoint's queue, or 128 * - UHCI_PTR_TERM (when there's no more traffic for this endpoint). 129 * 130 * The other role of a QH is to serve as a "skeleton" framelist entry, so we 131 * can easily splice a QH for some endpoint into the schedule at the right 132 * place. Then qh->element is UHCI_PTR_TERM. 133 * 134 * In the schedule, qh->link maintains a list of QHs seen by the HC: 135 * skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ... 136 * 137 * qh->node is the software equivalent of qh->link. The differences 138 * are that the software list is doubly-linked and QHs in the UNLINKING 139 * state are on the software list but not the hardware schedule. 140 * 141 * For bookkeeping purposes we maintain QHs even for Isochronous endpoints, 142 * but they never get added to the hardware schedule. 143 */ 144 #define QH_STATE_IDLE 1 /* QH is not being used */ 145 #define QH_STATE_UNLINKING 2 /* QH has been removed from the 146 * schedule but the hardware may 147 * still be using it */ 148 #define QH_STATE_ACTIVE 3 /* QH is on the schedule */ 149 150 struct uhci_qh { 151 /* Hardware fields */ 152 __hc32 link; /* Next QH in the schedule */ 153 __hc32 element; /* Queue element (TD) pointer */ 154 155 /* Software fields */ 156 dma_addr_t dma_handle; 157 158 struct list_head node; /* Node in the list of QHs */ 159 struct usb_host_endpoint *hep; /* Endpoint information */ 160 struct usb_device *udev; 161 struct list_head queue; /* Queue of urbps for this QH */ 162 struct uhci_td *dummy_td; /* Dummy TD to end the queue */ 163 struct uhci_td *post_td; /* Last TD completed */ 164 165 struct usb_iso_packet_descriptor *iso_packet_desc; 166 /* Next urb->iso_frame_desc entry */ 167 unsigned long advance_jiffies; /* Time of last queue advance */ 168 unsigned int unlink_frame; /* When the QH was unlinked */ 169 unsigned int period; /* For Interrupt and Isochronous QHs */ 170 short phase; /* Between 0 and period-1 */ 171 short load; /* Periodic time requirement, in us */ 172 unsigned int iso_frame; /* Frame # for iso_packet_desc */ 173 174 int state; /* QH_STATE_xxx; see above */ 175 int type; /* Queue type (control, bulk, etc) */ 176 int skel; /* Skeleton queue number */ 177 178 unsigned int initial_toggle:1; /* Endpoint's current toggle value */ 179 unsigned int needs_fixup:1; /* Must fix the TD toggle values */ 180 unsigned int is_stopped:1; /* Queue was stopped by error/unlink */ 181 unsigned int wait_expired:1; /* QH_WAIT_TIMEOUT has expired */ 182 unsigned int bandwidth_reserved:1; /* Periodic bandwidth has 183 * been allocated */ 184 } __attribute__((aligned(16))); 185 186 /* 187 * We need a special accessor for the element pointer because it is 188 * subject to asynchronous updates by the controller. 189 */ 190 #define qh_element(qh) READ_ONCE((qh)->element) 191 192 #define LINK_TO_QH(uhci, qh) (UHCI_PTR_QH((uhci)) | \ 193 cpu_to_hc32((uhci), (qh)->dma_handle)) 194 195 196 /* 197 * Transfer Descriptors 198 */ 199 200 /* 201 * for TD <status>: 202 */ 203 #define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */ 204 #define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */ 205 #define TD_CTRL_C_ERR_SHIFT 27 206 #define TD_CTRL_LS (1 << 26) /* Low Speed Device */ 207 #define TD_CTRL_IOS (1 << 25) /* Isochronous Select */ 208 #define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */ 209 #define TD_CTRL_ACTIVE (1 << 23) /* TD Active */ 210 #define TD_CTRL_STALLED (1 << 22) /* TD Stalled */ 211 #define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */ 212 #define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */ 213 #define TD_CTRL_NAK (1 << 19) /* NAK Received */ 214 #define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */ 215 #define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */ 216 #define TD_CTRL_ACTLEN_MASK 0x7FF /* actual length, encoded as n - 1 */ 217 218 #define uhci_maxerr(err) ((err) << TD_CTRL_C_ERR_SHIFT) 219 #define uhci_status_bits(ctrl_sts) ((ctrl_sts) & 0xF60000) 220 #define uhci_actual_length(ctrl_sts) (((ctrl_sts) + 1) & \ 221 TD_CTRL_ACTLEN_MASK) /* 1-based */ 222 223 /* 224 * for TD <info>: (a.k.a. Token) 225 */ 226 #define td_token(uhci, td) hc32_to_cpu((uhci), (td)->token) 227 #define TD_TOKEN_DEVADDR_SHIFT 8 228 #define TD_TOKEN_TOGGLE_SHIFT 19 229 #define TD_TOKEN_TOGGLE (1 << 19) 230 #define TD_TOKEN_EXPLEN_SHIFT 21 231 #define TD_TOKEN_EXPLEN_MASK 0x7FF /* expected length, encoded as n-1 */ 232 #define TD_TOKEN_PID_MASK 0xFF 233 234 #define uhci_explen(len) ((((len) - 1) & TD_TOKEN_EXPLEN_MASK) << \ 235 TD_TOKEN_EXPLEN_SHIFT) 236 237 #define uhci_expected_length(token) ((((token) >> TD_TOKEN_EXPLEN_SHIFT) + \ 238 1) & TD_TOKEN_EXPLEN_MASK) 239 #define uhci_toggle(token) (((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1) 240 #define uhci_endpoint(token) (((token) >> 15) & 0xf) 241 #define uhci_devaddr(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f) 242 #define uhci_devep(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff) 243 #define uhci_packetid(token) ((token) & TD_TOKEN_PID_MASK) 244 #define uhci_packetout(token) (uhci_packetid(token) != USB_PID_IN) 245 #define uhci_packetin(token) (uhci_packetid(token) == USB_PID_IN) 246 247 /* 248 * The documentation says "4 words for hardware, 4 words for software". 249 * 250 * That's silly, the hardware doesn't care. The hardware only cares that 251 * the hardware words are 16-byte aligned, and we can have any amount of 252 * sw space after the TD entry. 253 * 254 * td->link points to either another TD (not necessarily for the same urb or 255 * even the same endpoint), or nothing (PTR_TERM), or a QH. 256 */ 257 struct uhci_td { 258 /* Hardware fields */ 259 __hc32 link; 260 __hc32 status; 261 __hc32 token; 262 __hc32 buffer; 263 264 /* Software fields */ 265 dma_addr_t dma_handle; 266 267 struct list_head list; 268 269 int frame; /* for iso: what frame? */ 270 struct list_head fl_list; 271 } __attribute__((aligned(16))); 272 273 /* 274 * We need a special accessor for the control/status word because it is 275 * subject to asynchronous updates by the controller. 276 */ 277 #define td_status(uhci, td) hc32_to_cpu((uhci), \ 278 READ_ONCE((td)->status)) 279 280 #define LINK_TO_TD(uhci, td) (cpu_to_hc32((uhci), (td)->dma_handle)) 281 282 283 /* 284 * Skeleton Queue Headers 285 */ 286 287 /* 288 * The UHCI driver uses QHs with Interrupt, Control and Bulk URBs for 289 * automatic queuing. To make it easy to insert entries into the schedule, 290 * we have a skeleton of QHs for each predefined Interrupt latency. 291 * Asynchronous QHs (low-speed control, full-speed control, and bulk) 292 * go onto the period-1 interrupt list, since they all get accessed on 293 * every frame. 294 * 295 * When we want to add a new QH, we add it to the list starting from the 296 * appropriate skeleton QH. For instance, the schedule can look like this: 297 * 298 * skel int128 QH 299 * dev 1 interrupt QH 300 * dev 5 interrupt QH 301 * skel int64 QH 302 * skel int32 QH 303 * ... 304 * skel int1 + async QH 305 * dev 5 low-speed control QH 306 * dev 1 bulk QH 307 * dev 2 bulk QH 308 * 309 * There is a special terminating QH used to keep full-speed bandwidth 310 * reclamation active when no full-speed control or bulk QHs are linked 311 * into the schedule. It has an inactive TD (to work around a PIIX bug, 312 * see the Intel errata) and it points back to itself. 313 * 314 * There's a special skeleton QH for Isochronous QHs which never appears 315 * on the schedule. Isochronous TDs go on the schedule before the 316 * the skeleton QHs. The hardware accesses them directly rather than 317 * through their QH, which is used only for bookkeeping purposes. 318 * While the UHCI spec doesn't forbid the use of QHs for Isochronous, 319 * it doesn't use them either. And the spec says that queues never 320 * advance on an error completion status, which makes them totally 321 * unsuitable for Isochronous transfers. 322 * 323 * There's also a special skeleton QH used for QHs which are in the process 324 * of unlinking and so may still be in use by the hardware. It too never 325 * appears on the schedule. 326 */ 327 328 #define UHCI_NUM_SKELQH 11 329 #define SKEL_UNLINK 0 330 #define skel_unlink_qh skelqh[SKEL_UNLINK] 331 #define SKEL_ISO 1 332 #define skel_iso_qh skelqh[SKEL_ISO] 333 /* int128, int64, ..., int1 = 2, 3, ..., 9 */ 334 #define SKEL_INDEX(exponent) (9 - exponent) 335 #define SKEL_ASYNC 9 336 #define skel_async_qh skelqh[SKEL_ASYNC] 337 #define SKEL_TERM 10 338 #define skel_term_qh skelqh[SKEL_TERM] 339 340 /* The following entries refer to sublists of skel_async_qh */ 341 #define SKEL_LS_CONTROL 20 342 #define SKEL_FS_CONTROL 21 343 #define SKEL_FSBR SKEL_FS_CONTROL 344 #define SKEL_BULK 22 345 346 /* 347 * The UHCI controller and root hub 348 */ 349 350 /* 351 * States for the root hub: 352 * 353 * To prevent "bouncing" in the presence of electrical noise, 354 * when there are no devices attached we delay for 1 second in the 355 * RUNNING_NODEVS state before switching to the AUTO_STOPPED state. 356 * 357 * (Note that the AUTO_STOPPED state won't be necessary once the hub 358 * driver learns to autosuspend.) 359 */ 360 enum uhci_rh_state { 361 /* In the following states the HC must be halted. 362 * These two must come first. */ 363 UHCI_RH_RESET, 364 UHCI_RH_SUSPENDED, 365 366 UHCI_RH_AUTO_STOPPED, 367 UHCI_RH_RESUMING, 368 369 /* In this state the HC changes from running to halted, 370 * so it can legally appear either way. */ 371 UHCI_RH_SUSPENDING, 372 373 /* In the following states it's an error if the HC is halted. 374 * These two must come last. */ 375 UHCI_RH_RUNNING, /* The normal state */ 376 UHCI_RH_RUNNING_NODEVS, /* Running with no devices attached */ 377 }; 378 379 /* 380 * The full UHCI controller information: 381 */ 382 struct uhci_hcd { 383 384 /* debugfs */ 385 struct dentry *dentry; 386 387 /* Grabbed from PCI */ 388 unsigned long io_addr; 389 390 /* Used when registers are memory mapped */ 391 void __iomem *regs; 392 393 struct dma_pool *qh_pool; 394 struct dma_pool *td_pool; 395 396 struct uhci_td *term_td; /* Terminating TD, see UHCI bug */ 397 struct uhci_qh *skelqh[UHCI_NUM_SKELQH]; /* Skeleton QHs */ 398 struct uhci_qh *next_qh; /* Next QH to scan */ 399 400 spinlock_t lock; 401 402 dma_addr_t frame_dma_handle; /* Hardware frame list */ 403 __hc32 *frame; 404 void **frame_cpu; /* CPU's frame list */ 405 406 enum uhci_rh_state rh_state; 407 unsigned long auto_stop_time; /* When to AUTO_STOP */ 408 409 unsigned int frame_number; /* As of last check */ 410 unsigned int is_stopped; 411 #define UHCI_IS_STOPPED 9999 /* Larger than a frame # */ 412 unsigned int last_iso_frame; /* Frame of last scan */ 413 unsigned int cur_iso_frame; /* Frame for current scan */ 414 415 unsigned int scan_in_progress:1; /* Schedule scan is running */ 416 unsigned int need_rescan:1; /* Redo the schedule scan */ 417 unsigned int dead:1; /* Controller has died */ 418 unsigned int RD_enable:1; /* Suspended root hub with 419 Resume-Detect interrupts 420 enabled */ 421 unsigned int is_initialized:1; /* Data structure is usable */ 422 unsigned int fsbr_is_on:1; /* FSBR is turned on */ 423 unsigned int fsbr_is_wanted:1; /* Does any URB want FSBR? */ 424 unsigned int fsbr_expiring:1; /* FSBR is timing out */ 425 426 struct timer_list fsbr_timer; /* For turning off FBSR */ 427 428 /* Silicon quirks */ 429 unsigned int oc_low:1; /* OverCurrent bit active low */ 430 unsigned int wait_for_hp:1; /* Wait for HP port reset */ 431 unsigned int big_endian_mmio:1; /* Big endian registers */ 432 unsigned int big_endian_desc:1; /* Big endian descriptors */ 433 unsigned int is_aspeed:1; /* Aspeed impl. workarounds */ 434 435 /* Support for port suspend/resume/reset */ 436 unsigned long port_c_suspend; /* Bit-arrays of ports */ 437 unsigned long resuming_ports; 438 unsigned long ports_timeout; /* Time to stop signalling */ 439 440 struct list_head idle_qh_list; /* Where the idle QHs live */ 441 442 int rh_numports; /* Number of root-hub ports */ 443 444 wait_queue_head_t waitqh; /* endpoint_disable waiters */ 445 int num_waiting; /* Number of waiters */ 446 447 int total_load; /* Sum of array values */ 448 short load[MAX_PHASE]; /* Periodic allocations */ 449 450 /* Reset host controller */ 451 void (*reset_hc) (struct uhci_hcd *uhci); 452 int (*check_and_reset_hc) (struct uhci_hcd *uhci); 453 /* configure_hc should perform arch specific settings, if needed */ 454 void (*configure_hc) (struct uhci_hcd *uhci); 455 /* Check for broken resume detect interrupts */ 456 int (*resume_detect_interrupts_are_broken) (struct uhci_hcd *uhci); 457 /* Check for broken global suspend */ 458 int (*global_suspend_mode_is_broken) (struct uhci_hcd *uhci); 459 }; 460 461 /* Convert between a usb_hcd pointer and the corresponding uhci_hcd */ 462 static inline struct uhci_hcd *hcd_to_uhci(struct usb_hcd *hcd) 463 { 464 return (struct uhci_hcd *) (hcd->hcd_priv); 465 } 466 static inline struct usb_hcd *uhci_to_hcd(struct uhci_hcd *uhci) 467 { 468 return container_of((void *) uhci, struct usb_hcd, hcd_priv); 469 } 470 471 #define uhci_dev(u) (uhci_to_hcd(u)->self.controller) 472 473 /* Utility macro for comparing frame numbers */ 474 #define uhci_frame_before_eq(f1, f2) (0 <= (int) ((f2) - (f1))) 475 476 477 /* 478 * Private per-URB data 479 */ 480 struct urb_priv { 481 struct list_head node; /* Node in the QH's urbp list */ 482 483 struct urb *urb; 484 485 struct uhci_qh *qh; /* QH for this URB */ 486 struct list_head td_list; 487 488 unsigned fsbr:1; /* URB wants FSBR */ 489 }; 490 491 492 /* Some special IDs */ 493 494 #define PCI_VENDOR_ID_GENESYS 0x17a0 495 #define PCI_DEVICE_ID_GL880S_UHCI 0x8083 496 497 /* Aspeed SoC needs some quirks */ 498 static inline bool uhci_is_aspeed(const struct uhci_hcd *uhci) 499 { 500 return IS_ENABLED(CONFIG_USB_UHCI_ASPEED) && uhci->is_aspeed; 501 } 502 503 /* 504 * Functions used to access controller registers. The UCHI spec says that host 505 * controller I/O registers are mapped into PCI I/O space. For non-PCI hosts 506 * we use memory mapped registers. 507 */ 508 509 #ifndef CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC 510 /* Support PCI only */ 511 static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg) 512 { 513 return inl(uhci->io_addr + reg); 514 } 515 516 static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg) 517 { 518 outl(val, uhci->io_addr + reg); 519 } 520 521 static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg) 522 { 523 return inw(uhci->io_addr + reg); 524 } 525 526 static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg) 527 { 528 outw(val, uhci->io_addr + reg); 529 } 530 531 static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg) 532 { 533 return inb(uhci->io_addr + reg); 534 } 535 536 static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg) 537 { 538 outb(val, uhci->io_addr + reg); 539 } 540 541 #else 542 /* Support non-PCI host controllers */ 543 #ifdef CONFIG_USB_PCI 544 /* Support PCI and non-PCI host controllers */ 545 #define uhci_has_pci_registers(u) ((u)->io_addr != 0) 546 #else 547 /* Support non-PCI host controllers only */ 548 #define uhci_has_pci_registers(u) 0 549 #endif 550 551 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO 552 /* Support (non-PCI) big endian host controllers */ 553 #define uhci_big_endian_mmio(u) ((u)->big_endian_mmio) 554 #else 555 #define uhci_big_endian_mmio(u) 0 556 #endif 557 558 static inline int uhci_aspeed_reg(unsigned int reg) 559 { 560 switch (reg) { 561 case USBCMD: 562 return 00; 563 case USBSTS: 564 return 0x04; 565 case USBINTR: 566 return 0x08; 567 case USBFRNUM: 568 return 0x80; 569 case USBFLBASEADD: 570 return 0x0c; 571 case USBSOF: 572 return 0x84; 573 case USBPORTSC1: 574 return 0x88; 575 case USBPORTSC2: 576 return 0x8c; 577 case USBPORTSC3: 578 return 0x90; 579 case USBPORTSC4: 580 return 0x94; 581 default: 582 pr_warn("UHCI: Unsupported register 0x%02x on Aspeed\n", reg); 583 /* Return an unimplemented register */ 584 return 0x10; 585 } 586 } 587 588 static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg) 589 { 590 if (uhci_has_pci_registers(uhci)) 591 return inl(uhci->io_addr + reg); 592 else if (uhci_is_aspeed(uhci)) 593 return readl(uhci->regs + uhci_aspeed_reg(reg)); 594 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO 595 else if (uhci_big_endian_mmio(uhci)) 596 return readl_be(uhci->regs + reg); 597 #endif 598 else 599 return readl(uhci->regs + reg); 600 } 601 602 static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg) 603 { 604 if (uhci_has_pci_registers(uhci)) 605 outl(val, uhci->io_addr + reg); 606 else if (uhci_is_aspeed(uhci)) 607 writel(val, uhci->regs + uhci_aspeed_reg(reg)); 608 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO 609 else if (uhci_big_endian_mmio(uhci)) 610 writel_be(val, uhci->regs + reg); 611 #endif 612 else 613 writel(val, uhci->regs + reg); 614 } 615 616 static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg) 617 { 618 if (uhci_has_pci_registers(uhci)) 619 return inw(uhci->io_addr + reg); 620 else if (uhci_is_aspeed(uhci)) 621 return readl(uhci->regs + uhci_aspeed_reg(reg)); 622 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO 623 else if (uhci_big_endian_mmio(uhci)) 624 return readw_be(uhci->regs + reg); 625 #endif 626 else 627 return readw(uhci->regs + reg); 628 } 629 630 static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg) 631 { 632 if (uhci_has_pci_registers(uhci)) 633 outw(val, uhci->io_addr + reg); 634 else if (uhci_is_aspeed(uhci)) 635 writel(val, uhci->regs + uhci_aspeed_reg(reg)); 636 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO 637 else if (uhci_big_endian_mmio(uhci)) 638 writew_be(val, uhci->regs + reg); 639 #endif 640 else 641 writew(val, uhci->regs + reg); 642 } 643 644 static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg) 645 { 646 if (uhci_has_pci_registers(uhci)) 647 return inb(uhci->io_addr + reg); 648 else if (uhci_is_aspeed(uhci)) 649 return readl(uhci->regs + uhci_aspeed_reg(reg)); 650 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO 651 else if (uhci_big_endian_mmio(uhci)) 652 return readb_be(uhci->regs + reg); 653 #endif 654 else 655 return readb(uhci->regs + reg); 656 } 657 658 static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg) 659 { 660 if (uhci_has_pci_registers(uhci)) 661 outb(val, uhci->io_addr + reg); 662 else if (uhci_is_aspeed(uhci)) 663 writel(val, uhci->regs + uhci_aspeed_reg(reg)); 664 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO 665 else if (uhci_big_endian_mmio(uhci)) 666 writeb_be(val, uhci->regs + reg); 667 #endif 668 else 669 writeb(val, uhci->regs + reg); 670 } 671 #endif /* CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC */ 672 673 /* 674 * The GRLIB GRUSBHC controller can use big endian format for its descriptors. 675 * 676 * UHCI controllers accessed through PCI work normally (little-endian 677 * everywhere), so we don't bother supporting a BE-only mode. 678 */ 679 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_DESC 680 #define uhci_big_endian_desc(u) ((u)->big_endian_desc) 681 682 /* cpu to uhci */ 683 static inline __hc32 cpu_to_hc32(const struct uhci_hcd *uhci, const u32 x) 684 { 685 return uhci_big_endian_desc(uhci) 686 ? (__force __hc32)cpu_to_be32(x) 687 : (__force __hc32)cpu_to_le32(x); 688 } 689 690 /* uhci to cpu */ 691 static inline u32 hc32_to_cpu(const struct uhci_hcd *uhci, const __hc32 x) 692 { 693 return uhci_big_endian_desc(uhci) 694 ? be32_to_cpu((__force __be32)x) 695 : le32_to_cpu((__force __le32)x); 696 } 697 698 #else 699 /* cpu to uhci */ 700 static inline __hc32 cpu_to_hc32(const struct uhci_hcd *uhci, const u32 x) 701 { 702 return cpu_to_le32(x); 703 } 704 705 /* uhci to cpu */ 706 static inline u32 hc32_to_cpu(const struct uhci_hcd *uhci, const __hc32 x) 707 { 708 return le32_to_cpu(x); 709 } 710 #endif 711 712 #endif 713