1 /* 2 * R8A66597 HCD (Host Controller Driver) 3 * 4 * Copyright (C) 2006-2007 Renesas Solutions Corp. 5 * Portions Copyright (C) 2004 Psion Teklogix (for NetBook PRO) 6 * Portions Copyright (C) 2004-2005 David Brownell 7 * Portions Copyright (C) 1999 Roman Weissgaerber 8 * 9 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; version 2 of the License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 23 * 24 */ 25 26 #ifndef __R8A66597_H__ 27 #define __R8A66597_H__ 28 29 #include <linux/clk.h> 30 #include <linux/usb/r8a66597.h> 31 32 #define R8A66597_MAX_NUM_PIPE 10 33 #define R8A66597_BUF_BSIZE 8 34 #define R8A66597_MAX_DEVICE 10 35 #define R8A66597_MAX_ROOT_HUB 2 36 #define R8A66597_MAX_SAMPLING 5 37 #define R8A66597_RH_POLL_TIME 10 38 #define R8A66597_MAX_DMA_CHANNEL 2 39 #define R8A66597_PIPE_NO_DMA R8A66597_MAX_DMA_CHANNEL 40 #define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5)) 41 #define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9)) 42 #define make_devsel(addr) (addr << 12) 43 44 struct r8a66597_pipe_info { 45 unsigned long timer_interval; 46 u16 pipenum; 47 u16 address; /* R8A66597 HCD usb address */ 48 u16 epnum; 49 u16 maxpacket; 50 u16 type; 51 u16 bufnum; 52 u16 buf_bsize; 53 u16 interval; 54 u16 dir_in; 55 }; 56 57 struct r8a66597_pipe { 58 struct r8a66597_pipe_info info; 59 60 unsigned long fifoaddr; 61 unsigned long fifosel; 62 unsigned long fifoctr; 63 unsigned long pipectr; 64 unsigned long pipetre; 65 unsigned long pipetrn; 66 }; 67 68 struct r8a66597_td { 69 struct r8a66597_pipe *pipe; 70 struct urb *urb; 71 struct list_head queue; 72 73 u16 type; 74 u16 pipenum; 75 int iso_cnt; 76 77 u16 address; /* R8A66597's USB address */ 78 u16 maxpacket; 79 80 unsigned zero_packet:1; 81 unsigned short_packet:1; 82 unsigned set_address:1; 83 }; 84 85 struct r8a66597_device { 86 u16 address; /* R8A66597's USB address */ 87 u16 hub_port; 88 u16 root_port; 89 90 unsigned short ep_in_toggle; 91 unsigned short ep_out_toggle; 92 unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE]; 93 unsigned char dma_map; 94 95 enum usb_device_state state; 96 97 struct usb_device *udev; 98 int usb_address; 99 struct list_head device_list; 100 }; 101 102 struct r8a66597_root_hub { 103 u32 port; 104 u16 old_syssts; 105 int scount; 106 107 struct r8a66597_device *dev; 108 }; 109 110 struct r8a66597 { 111 spinlock_t lock; 112 void __iomem *reg; 113 struct clk *clk; 114 struct r8a66597_platdata *pdata; 115 struct r8a66597_device device0; 116 struct r8a66597_root_hub root_hub[R8A66597_MAX_ROOT_HUB]; 117 struct list_head pipe_queue[R8A66597_MAX_NUM_PIPE]; 118 119 struct timer_list rh_timer; 120 struct timer_list td_timer[R8A66597_MAX_NUM_PIPE]; 121 struct timer_list interval_timer[R8A66597_MAX_NUM_PIPE]; 122 123 unsigned short address_map; 124 unsigned short timeout_map; 125 unsigned short interval_map; 126 unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE]; 127 unsigned char dma_map; 128 unsigned int max_root_hub; 129 130 struct list_head child_device; 131 unsigned long child_connect_map[4]; 132 133 unsigned bus_suspended:1; 134 unsigned irq_sense_low:1; 135 }; 136 137 static inline struct r8a66597 *hcd_to_r8a66597(struct usb_hcd *hcd) 138 { 139 return (struct r8a66597 *)(hcd->hcd_priv); 140 } 141 142 static inline struct usb_hcd *r8a66597_to_hcd(struct r8a66597 *r8a66597) 143 { 144 return container_of((void *)r8a66597, struct usb_hcd, hcd_priv); 145 } 146 147 static inline struct r8a66597_td *r8a66597_get_td(struct r8a66597 *r8a66597, 148 u16 pipenum) 149 { 150 if (unlikely(list_empty(&r8a66597->pipe_queue[pipenum]))) 151 return NULL; 152 153 return list_entry(r8a66597->pipe_queue[pipenum].next, 154 struct r8a66597_td, queue); 155 } 156 157 static inline struct urb *r8a66597_get_urb(struct r8a66597 *r8a66597, 158 u16 pipenum) 159 { 160 struct r8a66597_td *td; 161 162 td = r8a66597_get_td(r8a66597, pipenum); 163 return (td ? td->urb : NULL); 164 } 165 166 static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset) 167 { 168 return ioread16(r8a66597->reg + offset); 169 } 170 171 static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597, 172 unsigned long offset, u16 *buf, 173 int len) 174 { 175 void __iomem *fifoaddr = r8a66597->reg + offset; 176 unsigned long count; 177 178 if (r8a66597->pdata->on_chip) { 179 count = len / 4; 180 ioread32_rep(fifoaddr, buf, count); 181 182 if (len & 0x00000003) { 183 unsigned long tmp = ioread32(fifoaddr); 184 memcpy((unsigned char *)buf + count * 4, &tmp, 185 len & 0x03); 186 } 187 } else { 188 len = (len + 1) / 2; 189 ioread16_rep(fifoaddr, buf, len); 190 } 191 } 192 193 static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val, 194 unsigned long offset) 195 { 196 iowrite16(val, r8a66597->reg + offset); 197 } 198 199 static inline void r8a66597_mdfy(struct r8a66597 *r8a66597, 200 u16 val, u16 pat, unsigned long offset) 201 { 202 u16 tmp; 203 tmp = r8a66597_read(r8a66597, offset); 204 tmp = tmp & (~pat); 205 tmp = tmp | val; 206 r8a66597_write(r8a66597, tmp, offset); 207 } 208 209 #define r8a66597_bclr(r8a66597, val, offset) \ 210 r8a66597_mdfy(r8a66597, 0, val, offset) 211 #define r8a66597_bset(r8a66597, val, offset) \ 212 r8a66597_mdfy(r8a66597, val, 0, offset) 213 214 static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597, 215 struct r8a66597_pipe *pipe, u16 *buf, 216 int len) 217 { 218 void __iomem *fifoaddr = r8a66597->reg + pipe->fifoaddr; 219 unsigned long count; 220 unsigned char *pb; 221 int i; 222 223 if (r8a66597->pdata->on_chip) { 224 count = len / 4; 225 iowrite32_rep(fifoaddr, buf, count); 226 227 if (len & 0x00000003) { 228 pb = (unsigned char *)buf + count * 4; 229 for (i = 0; i < (len & 0x00000003); i++) { 230 if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND) 231 iowrite8(pb[i], fifoaddr + i); 232 else 233 iowrite8(pb[i], fifoaddr + 3 - i); 234 } 235 } 236 } else { 237 int odd = len & 0x0001; 238 239 len = len / 2; 240 iowrite16_rep(fifoaddr, buf, len); 241 if (unlikely(odd)) { 242 buf = &buf[len]; 243 if (r8a66597->pdata->wr0_shorted_to_wr1) 244 r8a66597_bclr(r8a66597, MBW_16, pipe->fifosel); 245 iowrite8((unsigned char)*buf, fifoaddr); 246 if (r8a66597->pdata->wr0_shorted_to_wr1) 247 r8a66597_bset(r8a66597, MBW_16, pipe->fifosel); 248 } 249 } 250 } 251 252 static inline unsigned long get_syscfg_reg(int port) 253 { 254 return port == 0 ? SYSCFG0 : SYSCFG1; 255 } 256 257 static inline unsigned long get_syssts_reg(int port) 258 { 259 return port == 0 ? SYSSTS0 : SYSSTS1; 260 } 261 262 static inline unsigned long get_dvstctr_reg(int port) 263 { 264 return port == 0 ? DVSTCTR0 : DVSTCTR1; 265 } 266 267 static inline unsigned long get_dmacfg_reg(int port) 268 { 269 return port == 0 ? DMA0CFG : DMA1CFG; 270 } 271 272 static inline unsigned long get_intenb_reg(int port) 273 { 274 return port == 0 ? INTENB1 : INTENB2; 275 } 276 277 static inline unsigned long get_intsts_reg(int port) 278 { 279 return port == 0 ? INTSTS1 : INTSTS2; 280 } 281 282 static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port) 283 { 284 unsigned long dvstctr_reg = get_dvstctr_reg(port); 285 286 return r8a66597_read(r8a66597, dvstctr_reg) & RHST; 287 } 288 289 static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port, 290 int power) 291 { 292 unsigned long dvstctr_reg = get_dvstctr_reg(port); 293 294 if (r8a66597->pdata->port_power) { 295 r8a66597->pdata->port_power(port, power); 296 } else { 297 if (power) 298 r8a66597_bset(r8a66597, VBOUT, dvstctr_reg); 299 else 300 r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg); 301 } 302 } 303 304 static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata) 305 { 306 u16 clock = 0; 307 308 switch (pdata->xtal) { 309 case R8A66597_PLATDATA_XTAL_12MHZ: 310 clock = XTAL12; 311 break; 312 case R8A66597_PLATDATA_XTAL_24MHZ: 313 clock = XTAL24; 314 break; 315 case R8A66597_PLATDATA_XTAL_48MHZ: 316 clock = XTAL48; 317 break; 318 default: 319 printk(KERN_ERR "r8a66597: platdata clock is wrong.\n"); 320 break; 321 } 322 323 return clock; 324 } 325 326 #define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2) 327 #define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4) 328 #define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4) 329 #define get_devadd_addr(address) (DEVADD0 + address * 2) 330 331 #define enable_irq_ready(r8a66597, pipenum) \ 332 enable_pipe_irq(r8a66597, pipenum, BRDYENB) 333 #define disable_irq_ready(r8a66597, pipenum) \ 334 disable_pipe_irq(r8a66597, pipenum, BRDYENB) 335 #define enable_irq_empty(r8a66597, pipenum) \ 336 enable_pipe_irq(r8a66597, pipenum, BEMPENB) 337 #define disable_irq_empty(r8a66597, pipenum) \ 338 disable_pipe_irq(r8a66597, pipenum, BEMPENB) 339 #define enable_irq_nrdy(r8a66597, pipenum) \ 340 enable_pipe_irq(r8a66597, pipenum, NRDYENB) 341 #define disable_irq_nrdy(r8a66597, pipenum) \ 342 disable_pipe_irq(r8a66597, pipenum, NRDYENB) 343 344 #endif /* __R8A66597_H__ */ 345 346