1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains code to reset and initialize USB host controllers. 4 * Some of it includes work-arounds for PCI hardware and BIOS quirks. 5 * It may need to run early during booting -- before USB would normally 6 * initialize -- to ensure that Linux doesn't use any legacy modes. 7 * 8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 9 * (and others) 10 */ 11 12 #include <linux/types.h> 13 #include <linux/kernel.h> 14 #include <linux/pci.h> 15 #include <linux/delay.h> 16 #include <linux/export.h> 17 #include <linux/acpi.h> 18 #include <linux/dmi.h> 19 #include "pci-quirks.h" 20 #include "xhci-ext-caps.h" 21 22 23 #define UHCI_USBLEGSUP 0xc0 /* legacy support */ 24 #define UHCI_USBCMD 0 /* command register */ 25 #define UHCI_USBINTR 4 /* interrupt register */ 26 #define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */ 27 #define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */ 28 #define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */ 29 #define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */ 30 #define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */ 31 #define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */ 32 #define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */ 33 34 #define OHCI_CONTROL 0x04 35 #define OHCI_CMDSTATUS 0x08 36 #define OHCI_INTRSTATUS 0x0c 37 #define OHCI_INTRENABLE 0x10 38 #define OHCI_INTRDISABLE 0x14 39 #define OHCI_FMINTERVAL 0x34 40 #define OHCI_HCFS (3 << 6) /* hc functional state */ 41 #define OHCI_HCR (1 << 0) /* host controller reset */ 42 #define OHCI_OCR (1 << 3) /* ownership change request */ 43 #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ 44 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ 45 #define OHCI_INTR_OC (1 << 30) /* ownership change */ 46 47 #define EHCI_HCC_PARAMS 0x08 /* extended capabilities */ 48 #define EHCI_USBCMD 0 /* command register */ 49 #define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */ 50 #define EHCI_USBSTS 4 /* status register */ 51 #define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */ 52 #define EHCI_USBINTR 8 /* interrupt register */ 53 #define EHCI_CONFIGFLAG 0x40 /* configured flag register */ 54 #define EHCI_USBLEGSUP 0 /* legacy support register */ 55 #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */ 56 #define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */ 57 #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */ 58 #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */ 59 60 /* AMD quirk use */ 61 #define AB_REG_BAR_LOW 0xe0 62 #define AB_REG_BAR_HIGH 0xe1 63 #define AB_REG_BAR_SB700 0xf0 64 #define AB_INDX(addr) ((addr) + 0x00) 65 #define AB_DATA(addr) ((addr) + 0x04) 66 #define AX_INDXC 0x30 67 #define AX_DATAC 0x34 68 69 #define PT_ADDR_INDX 0xE8 70 #define PT_READ_INDX 0xE4 71 #define PT_SIG_1_ADDR 0xA520 72 #define PT_SIG_2_ADDR 0xA521 73 #define PT_SIG_3_ADDR 0xA522 74 #define PT_SIG_4_ADDR 0xA523 75 #define PT_SIG_1_DATA 0x78 76 #define PT_SIG_2_DATA 0x56 77 #define PT_SIG_3_DATA 0x34 78 #define PT_SIG_4_DATA 0x12 79 #define PT4_P1_REG 0xB521 80 #define PT4_P2_REG 0xB522 81 #define PT2_P1_REG 0xD520 82 #define PT2_P2_REG 0xD521 83 #define PT1_P1_REG 0xD522 84 #define PT1_P2_REG 0xD523 85 86 #define NB_PCIE_INDX_ADDR 0xe0 87 #define NB_PCIE_INDX_DATA 0xe4 88 #define PCIE_P_CNTL 0x10040 89 #define BIF_NB 0x10002 90 #define NB_PIF0_PWRDOWN_0 0x01100012 91 #define NB_PIF0_PWRDOWN_1 0x01100013 92 93 #define USB_INTEL_XUSB2PR 0xD0 94 #define USB_INTEL_USB2PRM 0xD4 95 #define USB_INTEL_USB3_PSSEN 0xD8 96 #define USB_INTEL_USB3PRM 0xDC 97 98 /* ASMEDIA quirk use */ 99 #define ASMT_DATA_WRITE0_REG 0xF8 100 #define ASMT_DATA_WRITE1_REG 0xFC 101 #define ASMT_CONTROL_REG 0xE0 102 #define ASMT_CONTROL_WRITE_BIT 0x02 103 #define ASMT_WRITEREG_CMD 0x10423 104 #define ASMT_FLOWCTL_ADDR 0xFA30 105 #define ASMT_FLOWCTL_DATA 0xBA 106 #define ASMT_PSEUDO_DATA 0 107 108 /* 109 * amd_chipset_gen values represent AMD different chipset generations 110 */ 111 enum amd_chipset_gen { 112 NOT_AMD_CHIPSET = 0, 113 AMD_CHIPSET_SB600, 114 AMD_CHIPSET_SB700, 115 AMD_CHIPSET_SB800, 116 AMD_CHIPSET_HUDSON2, 117 AMD_CHIPSET_BOLTON, 118 AMD_CHIPSET_YANGTZE, 119 AMD_CHIPSET_TAISHAN, 120 AMD_CHIPSET_UNKNOWN, 121 }; 122 123 struct amd_chipset_type { 124 enum amd_chipset_gen gen; 125 u8 rev; 126 }; 127 128 static struct amd_chipset_info { 129 struct pci_dev *nb_dev; 130 struct pci_dev *smbus_dev; 131 int nb_type; 132 struct amd_chipset_type sb_type; 133 int isoc_reqs; 134 int probe_count; 135 int probe_result; 136 } amd_chipset; 137 138 static DEFINE_SPINLOCK(amd_lock); 139 140 /* 141 * amd_chipset_sb_type_init - initialize amd chipset southbridge type 142 * 143 * AMD FCH/SB generation and revision is identified by SMBus controller 144 * vendor, device and revision IDs. 145 * 146 * Returns: 1 if it is an AMD chipset, 0 otherwise. 147 */ 148 static int amd_chipset_sb_type_init(struct amd_chipset_info *pinfo) 149 { 150 u8 rev = 0; 151 pinfo->sb_type.gen = AMD_CHIPSET_UNKNOWN; 152 153 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 154 PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL); 155 if (pinfo->smbus_dev) { 156 rev = pinfo->smbus_dev->revision; 157 if (rev >= 0x10 && rev <= 0x1f) 158 pinfo->sb_type.gen = AMD_CHIPSET_SB600; 159 else if (rev >= 0x30 && rev <= 0x3f) 160 pinfo->sb_type.gen = AMD_CHIPSET_SB700; 161 else if (rev >= 0x40 && rev <= 0x4f) 162 pinfo->sb_type.gen = AMD_CHIPSET_SB800; 163 } else { 164 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 165 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 166 167 if (pinfo->smbus_dev) { 168 rev = pinfo->smbus_dev->revision; 169 if (rev >= 0x11 && rev <= 0x14) 170 pinfo->sb_type.gen = AMD_CHIPSET_HUDSON2; 171 else if (rev >= 0x15 && rev <= 0x18) 172 pinfo->sb_type.gen = AMD_CHIPSET_BOLTON; 173 else if (rev >= 0x39 && rev <= 0x3a) 174 pinfo->sb_type.gen = AMD_CHIPSET_YANGTZE; 175 } else { 176 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 177 0x145c, NULL); 178 if (pinfo->smbus_dev) { 179 rev = pinfo->smbus_dev->revision; 180 pinfo->sb_type.gen = AMD_CHIPSET_TAISHAN; 181 } else { 182 pinfo->sb_type.gen = NOT_AMD_CHIPSET; 183 return 0; 184 } 185 } 186 } 187 pinfo->sb_type.rev = rev; 188 return 1; 189 } 190 191 void sb800_prefetch(struct device *dev, int on) 192 { 193 u16 misc; 194 struct pci_dev *pdev = to_pci_dev(dev); 195 196 pci_read_config_word(pdev, 0x50, &misc); 197 if (on == 0) 198 pci_write_config_word(pdev, 0x50, misc & 0xfcff); 199 else 200 pci_write_config_word(pdev, 0x50, misc | 0x0300); 201 } 202 EXPORT_SYMBOL_GPL(sb800_prefetch); 203 204 int usb_amd_find_chipset_info(void) 205 { 206 unsigned long flags; 207 struct amd_chipset_info info; 208 int ret; 209 210 spin_lock_irqsave(&amd_lock, flags); 211 212 /* probe only once */ 213 if (amd_chipset.probe_count > 0) { 214 amd_chipset.probe_count++; 215 spin_unlock_irqrestore(&amd_lock, flags); 216 return amd_chipset.probe_result; 217 } 218 memset(&info, 0, sizeof(info)); 219 spin_unlock_irqrestore(&amd_lock, flags); 220 221 if (!amd_chipset_sb_type_init(&info)) { 222 ret = 0; 223 goto commit; 224 } 225 226 /* Below chipset generations needn't enable AMD PLL quirk */ 227 if (info.sb_type.gen == AMD_CHIPSET_UNKNOWN || 228 info.sb_type.gen == AMD_CHIPSET_SB600 || 229 info.sb_type.gen == AMD_CHIPSET_YANGTZE || 230 (info.sb_type.gen == AMD_CHIPSET_SB700 && 231 info.sb_type.rev > 0x3b)) { 232 if (info.smbus_dev) { 233 pci_dev_put(info.smbus_dev); 234 info.smbus_dev = NULL; 235 } 236 ret = 0; 237 goto commit; 238 } 239 240 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL); 241 if (info.nb_dev) { 242 info.nb_type = 1; 243 } else { 244 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL); 245 if (info.nb_dev) { 246 info.nb_type = 2; 247 } else { 248 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 249 0x9600, NULL); 250 if (info.nb_dev) 251 info.nb_type = 3; 252 } 253 } 254 255 ret = info.probe_result = 1; 256 printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n"); 257 258 commit: 259 260 spin_lock_irqsave(&amd_lock, flags); 261 if (amd_chipset.probe_count > 0) { 262 /* race - someone else was faster - drop devices */ 263 264 /* Mark that we where here */ 265 amd_chipset.probe_count++; 266 ret = amd_chipset.probe_result; 267 268 spin_unlock_irqrestore(&amd_lock, flags); 269 270 pci_dev_put(info.nb_dev); 271 pci_dev_put(info.smbus_dev); 272 273 } else { 274 /* no race - commit the result */ 275 info.probe_count++; 276 amd_chipset = info; 277 spin_unlock_irqrestore(&amd_lock, flags); 278 } 279 280 return ret; 281 } 282 EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info); 283 284 int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *pdev) 285 { 286 /* Make sure amd chipset type has already been initialized */ 287 usb_amd_find_chipset_info(); 288 if (amd_chipset.sb_type.gen == AMD_CHIPSET_YANGTZE || 289 amd_chipset.sb_type.gen == AMD_CHIPSET_TAISHAN) { 290 dev_dbg(&pdev->dev, "QUIRK: Enable AMD remote wakeup fix\n"); 291 return 1; 292 } 293 return 0; 294 } 295 EXPORT_SYMBOL_GPL(usb_hcd_amd_remote_wakeup_quirk); 296 297 bool usb_amd_hang_symptom_quirk(void) 298 { 299 u8 rev; 300 301 usb_amd_find_chipset_info(); 302 rev = amd_chipset.sb_type.rev; 303 /* SB600 and old version of SB700 have hang symptom bug */ 304 return amd_chipset.sb_type.gen == AMD_CHIPSET_SB600 || 305 (amd_chipset.sb_type.gen == AMD_CHIPSET_SB700 && 306 rev >= 0x3a && rev <= 0x3b); 307 } 308 EXPORT_SYMBOL_GPL(usb_amd_hang_symptom_quirk); 309 310 bool usb_amd_prefetch_quirk(void) 311 { 312 usb_amd_find_chipset_info(); 313 /* SB800 needs pre-fetch fix */ 314 return amd_chipset.sb_type.gen == AMD_CHIPSET_SB800; 315 } 316 EXPORT_SYMBOL_GPL(usb_amd_prefetch_quirk); 317 318 /* 319 * The hardware normally enables the A-link power management feature, which 320 * lets the system lower the power consumption in idle states. 321 * 322 * This USB quirk prevents the link going into that lower power state 323 * during isochronous transfers. 324 * 325 * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of 326 * some AMD platforms may stutter or have breaks occasionally. 327 */ 328 static void usb_amd_quirk_pll(int disable) 329 { 330 u32 addr, addr_low, addr_high, val; 331 u32 bit = disable ? 0 : 1; 332 unsigned long flags; 333 334 spin_lock_irqsave(&amd_lock, flags); 335 336 if (disable) { 337 amd_chipset.isoc_reqs++; 338 if (amd_chipset.isoc_reqs > 1) { 339 spin_unlock_irqrestore(&amd_lock, flags); 340 return; 341 } 342 } else { 343 amd_chipset.isoc_reqs--; 344 if (amd_chipset.isoc_reqs > 0) { 345 spin_unlock_irqrestore(&amd_lock, flags); 346 return; 347 } 348 } 349 350 if (amd_chipset.sb_type.gen == AMD_CHIPSET_SB800 || 351 amd_chipset.sb_type.gen == AMD_CHIPSET_HUDSON2 || 352 amd_chipset.sb_type.gen == AMD_CHIPSET_BOLTON) { 353 outb_p(AB_REG_BAR_LOW, 0xcd6); 354 addr_low = inb_p(0xcd7); 355 outb_p(AB_REG_BAR_HIGH, 0xcd6); 356 addr_high = inb_p(0xcd7); 357 addr = addr_high << 8 | addr_low; 358 359 outl_p(0x30, AB_INDX(addr)); 360 outl_p(0x40, AB_DATA(addr)); 361 outl_p(0x34, AB_INDX(addr)); 362 val = inl_p(AB_DATA(addr)); 363 } else if (amd_chipset.sb_type.gen == AMD_CHIPSET_SB700 && 364 amd_chipset.sb_type.rev <= 0x3b) { 365 pci_read_config_dword(amd_chipset.smbus_dev, 366 AB_REG_BAR_SB700, &addr); 367 outl(AX_INDXC, AB_INDX(addr)); 368 outl(0x40, AB_DATA(addr)); 369 outl(AX_DATAC, AB_INDX(addr)); 370 val = inl(AB_DATA(addr)); 371 } else { 372 spin_unlock_irqrestore(&amd_lock, flags); 373 return; 374 } 375 376 if (disable) { 377 val &= ~0x08; 378 val |= (1 << 4) | (1 << 9); 379 } else { 380 val |= 0x08; 381 val &= ~((1 << 4) | (1 << 9)); 382 } 383 outl_p(val, AB_DATA(addr)); 384 385 if (!amd_chipset.nb_dev) { 386 spin_unlock_irqrestore(&amd_lock, flags); 387 return; 388 } 389 390 if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) { 391 addr = PCIE_P_CNTL; 392 pci_write_config_dword(amd_chipset.nb_dev, 393 NB_PCIE_INDX_ADDR, addr); 394 pci_read_config_dword(amd_chipset.nb_dev, 395 NB_PCIE_INDX_DATA, &val); 396 397 val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12)); 398 val |= bit | (bit << 3) | (bit << 12); 399 val |= ((!bit) << 4) | ((!bit) << 9); 400 pci_write_config_dword(amd_chipset.nb_dev, 401 NB_PCIE_INDX_DATA, val); 402 403 addr = BIF_NB; 404 pci_write_config_dword(amd_chipset.nb_dev, 405 NB_PCIE_INDX_ADDR, addr); 406 pci_read_config_dword(amd_chipset.nb_dev, 407 NB_PCIE_INDX_DATA, &val); 408 val &= ~(1 << 8); 409 val |= bit << 8; 410 411 pci_write_config_dword(amd_chipset.nb_dev, 412 NB_PCIE_INDX_DATA, val); 413 } else if (amd_chipset.nb_type == 2) { 414 addr = NB_PIF0_PWRDOWN_0; 415 pci_write_config_dword(amd_chipset.nb_dev, 416 NB_PCIE_INDX_ADDR, addr); 417 pci_read_config_dword(amd_chipset.nb_dev, 418 NB_PCIE_INDX_DATA, &val); 419 if (disable) 420 val &= ~(0x3f << 7); 421 else 422 val |= 0x3f << 7; 423 424 pci_write_config_dword(amd_chipset.nb_dev, 425 NB_PCIE_INDX_DATA, val); 426 427 addr = NB_PIF0_PWRDOWN_1; 428 pci_write_config_dword(amd_chipset.nb_dev, 429 NB_PCIE_INDX_ADDR, addr); 430 pci_read_config_dword(amd_chipset.nb_dev, 431 NB_PCIE_INDX_DATA, &val); 432 if (disable) 433 val &= ~(0x3f << 7); 434 else 435 val |= 0x3f << 7; 436 437 pci_write_config_dword(amd_chipset.nb_dev, 438 NB_PCIE_INDX_DATA, val); 439 } 440 441 spin_unlock_irqrestore(&amd_lock, flags); 442 return; 443 } 444 445 void usb_amd_quirk_pll_disable(void) 446 { 447 usb_amd_quirk_pll(1); 448 } 449 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable); 450 451 static int usb_asmedia_wait_write(struct pci_dev *pdev) 452 { 453 unsigned long retry_count; 454 unsigned char value; 455 456 for (retry_count = 1000; retry_count > 0; --retry_count) { 457 458 pci_read_config_byte(pdev, ASMT_CONTROL_REG, &value); 459 460 if (value == 0xff) { 461 dev_err(&pdev->dev, "%s: check_ready ERROR", __func__); 462 return -EIO; 463 } 464 465 if ((value & ASMT_CONTROL_WRITE_BIT) == 0) 466 return 0; 467 468 udelay(50); 469 } 470 471 dev_warn(&pdev->dev, "%s: check_write_ready timeout", __func__); 472 return -ETIMEDOUT; 473 } 474 475 void usb_asmedia_modifyflowcontrol(struct pci_dev *pdev) 476 { 477 if (usb_asmedia_wait_write(pdev) != 0) 478 return; 479 480 /* send command and address to device */ 481 pci_write_config_dword(pdev, ASMT_DATA_WRITE0_REG, ASMT_WRITEREG_CMD); 482 pci_write_config_dword(pdev, ASMT_DATA_WRITE1_REG, ASMT_FLOWCTL_ADDR); 483 pci_write_config_byte(pdev, ASMT_CONTROL_REG, ASMT_CONTROL_WRITE_BIT); 484 485 if (usb_asmedia_wait_write(pdev) != 0) 486 return; 487 488 /* send data to device */ 489 pci_write_config_dword(pdev, ASMT_DATA_WRITE0_REG, ASMT_FLOWCTL_DATA); 490 pci_write_config_dword(pdev, ASMT_DATA_WRITE1_REG, ASMT_PSEUDO_DATA); 491 pci_write_config_byte(pdev, ASMT_CONTROL_REG, ASMT_CONTROL_WRITE_BIT); 492 } 493 EXPORT_SYMBOL_GPL(usb_asmedia_modifyflowcontrol); 494 495 void usb_amd_quirk_pll_enable(void) 496 { 497 usb_amd_quirk_pll(0); 498 } 499 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable); 500 501 void usb_amd_dev_put(void) 502 { 503 struct pci_dev *nb, *smbus; 504 unsigned long flags; 505 506 spin_lock_irqsave(&amd_lock, flags); 507 508 amd_chipset.probe_count--; 509 if (amd_chipset.probe_count > 0) { 510 spin_unlock_irqrestore(&amd_lock, flags); 511 return; 512 } 513 514 /* save them to pci_dev_put outside of spinlock */ 515 nb = amd_chipset.nb_dev; 516 smbus = amd_chipset.smbus_dev; 517 518 amd_chipset.nb_dev = NULL; 519 amd_chipset.smbus_dev = NULL; 520 amd_chipset.nb_type = 0; 521 memset(&amd_chipset.sb_type, 0, sizeof(amd_chipset.sb_type)); 522 amd_chipset.isoc_reqs = 0; 523 amd_chipset.probe_result = 0; 524 525 spin_unlock_irqrestore(&amd_lock, flags); 526 527 pci_dev_put(nb); 528 pci_dev_put(smbus); 529 } 530 EXPORT_SYMBOL_GPL(usb_amd_dev_put); 531 532 /* 533 * Check if port is disabled in BIOS on AMD Promontory host. 534 * BIOS Disabled ports may wake on connect/disconnect and need 535 * driver workaround to keep them disabled. 536 * Returns true if port is marked disabled. 537 */ 538 bool usb_amd_pt_check_port(struct device *device, int port) 539 { 540 unsigned char value, port_shift; 541 struct pci_dev *pdev; 542 u16 reg; 543 544 pdev = to_pci_dev(device); 545 pci_write_config_word(pdev, PT_ADDR_INDX, PT_SIG_1_ADDR); 546 547 pci_read_config_byte(pdev, PT_READ_INDX, &value); 548 if (value != PT_SIG_1_DATA) 549 return false; 550 551 pci_write_config_word(pdev, PT_ADDR_INDX, PT_SIG_2_ADDR); 552 553 pci_read_config_byte(pdev, PT_READ_INDX, &value); 554 if (value != PT_SIG_2_DATA) 555 return false; 556 557 pci_write_config_word(pdev, PT_ADDR_INDX, PT_SIG_3_ADDR); 558 559 pci_read_config_byte(pdev, PT_READ_INDX, &value); 560 if (value != PT_SIG_3_DATA) 561 return false; 562 563 pci_write_config_word(pdev, PT_ADDR_INDX, PT_SIG_4_ADDR); 564 565 pci_read_config_byte(pdev, PT_READ_INDX, &value); 566 if (value != PT_SIG_4_DATA) 567 return false; 568 569 /* Check disabled port setting, if bit is set port is enabled */ 570 switch (pdev->device) { 571 case 0x43b9: 572 case 0x43ba: 573 /* 574 * device is AMD_PROMONTORYA_4(0x43b9) or PROMONTORYA_3(0x43ba) 575 * PT4_P1_REG bits[7..1] represents USB2.0 ports 6 to 0 576 * PT4_P2_REG bits[6..0] represents ports 13 to 7 577 */ 578 if (port > 6) { 579 reg = PT4_P2_REG; 580 port_shift = port - 7; 581 } else { 582 reg = PT4_P1_REG; 583 port_shift = port + 1; 584 } 585 break; 586 case 0x43bb: 587 /* 588 * device is AMD_PROMONTORYA_2(0x43bb) 589 * PT2_P1_REG bits[7..5] represents USB2.0 ports 2 to 0 590 * PT2_P2_REG bits[5..0] represents ports 9 to 3 591 */ 592 if (port > 2) { 593 reg = PT2_P2_REG; 594 port_shift = port - 3; 595 } else { 596 reg = PT2_P1_REG; 597 port_shift = port + 5; 598 } 599 break; 600 case 0x43bc: 601 /* 602 * device is AMD_PROMONTORYA_1(0x43bc) 603 * PT1_P1_REG[7..4] represents USB2.0 ports 3 to 0 604 * PT1_P2_REG[5..0] represents ports 9 to 4 605 */ 606 if (port > 3) { 607 reg = PT1_P2_REG; 608 port_shift = port - 4; 609 } else { 610 reg = PT1_P1_REG; 611 port_shift = port + 4; 612 } 613 break; 614 default: 615 return false; 616 } 617 pci_write_config_word(pdev, PT_ADDR_INDX, reg); 618 pci_read_config_byte(pdev, PT_READ_INDX, &value); 619 620 return !(value & BIT(port_shift)); 621 } 622 EXPORT_SYMBOL_GPL(usb_amd_pt_check_port); 623 624 /* 625 * Make sure the controller is completely inactive, unable to 626 * generate interrupts or do DMA. 627 */ 628 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base) 629 { 630 /* Turn off PIRQ enable and SMI enable. (This also turns off the 631 * BIOS's USB Legacy Support.) Turn off all the R/WC bits too. 632 */ 633 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC); 634 635 /* Reset the HC - this will force us to get a 636 * new notification of any already connected 637 * ports due to the virtual disconnect that it 638 * implies. 639 */ 640 outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD); 641 mb(); 642 udelay(5); 643 if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET) 644 dev_warn(&pdev->dev, "HCRESET not completed yet!\n"); 645 646 /* Just to be safe, disable interrupt requests and 647 * make sure the controller is stopped. 648 */ 649 outw(0, base + UHCI_USBINTR); 650 outw(0, base + UHCI_USBCMD); 651 } 652 EXPORT_SYMBOL_GPL(uhci_reset_hc); 653 654 /* 655 * Initialize a controller that was newly discovered or has just been 656 * resumed. In either case we can't be sure of its previous state. 657 * 658 * Returns: 1 if the controller was reset, 0 otherwise. 659 */ 660 int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base) 661 { 662 u16 legsup; 663 unsigned int cmd, intr; 664 665 /* 666 * When restarting a suspended controller, we expect all the 667 * settings to be the same as we left them: 668 * 669 * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP; 670 * Controller is stopped and configured with EGSM set; 671 * No interrupts enabled except possibly Resume Detect. 672 * 673 * If any of these conditions are violated we do a complete reset. 674 */ 675 pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup); 676 if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) { 677 dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n", 678 __func__, legsup); 679 goto reset_needed; 680 } 681 682 cmd = inw(base + UHCI_USBCMD); 683 if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) || 684 !(cmd & UHCI_USBCMD_EGSM)) { 685 dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n", 686 __func__, cmd); 687 goto reset_needed; 688 } 689 690 intr = inw(base + UHCI_USBINTR); 691 if (intr & (~UHCI_USBINTR_RESUME)) { 692 dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n", 693 __func__, intr); 694 goto reset_needed; 695 } 696 return 0; 697 698 reset_needed: 699 dev_dbg(&pdev->dev, "Performing full reset\n"); 700 uhci_reset_hc(pdev, base); 701 return 1; 702 } 703 EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc); 704 705 static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask) 706 { 707 u16 cmd; 708 return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask); 709 } 710 711 #define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO) 712 #define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY) 713 714 static void quirk_usb_handoff_uhci(struct pci_dev *pdev) 715 { 716 unsigned long base = 0; 717 int i; 718 719 if (!pio_enabled(pdev)) 720 return; 721 722 for (i = 0; i < PCI_ROM_RESOURCE; i++) 723 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) { 724 base = pci_resource_start(pdev, i); 725 break; 726 } 727 728 if (base) 729 uhci_check_and_reset_hc(pdev, base); 730 } 731 732 static int mmio_resource_enabled(struct pci_dev *pdev, int idx) 733 { 734 return pci_resource_start(pdev, idx) && mmio_enabled(pdev); 735 } 736 737 static void quirk_usb_handoff_ohci(struct pci_dev *pdev) 738 { 739 void __iomem *base; 740 u32 control; 741 u32 fminterval = 0; 742 bool no_fminterval = false; 743 int cnt; 744 745 if (!mmio_resource_enabled(pdev, 0)) 746 return; 747 748 base = pci_ioremap_bar(pdev, 0); 749 if (base == NULL) 750 return; 751 752 /* 753 * ULi M5237 OHCI controller locks the whole system when accessing 754 * the OHCI_FMINTERVAL offset. 755 */ 756 if (pdev->vendor == PCI_VENDOR_ID_AL && pdev->device == 0x5237) 757 no_fminterval = true; 758 759 control = readl(base + OHCI_CONTROL); 760 761 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ 762 #ifdef __hppa__ 763 #define OHCI_CTRL_MASK (OHCI_CTRL_RWC | OHCI_CTRL_IR) 764 #else 765 #define OHCI_CTRL_MASK OHCI_CTRL_RWC 766 767 if (control & OHCI_CTRL_IR) { 768 int wait_time = 500; /* arbitrary; 5 seconds */ 769 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE); 770 writel(OHCI_OCR, base + OHCI_CMDSTATUS); 771 while (wait_time > 0 && 772 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) { 773 wait_time -= 10; 774 msleep(10); 775 } 776 if (wait_time <= 0) 777 dev_warn(&pdev->dev, 778 "OHCI: BIOS handoff failed (BIOS bug?) %08x\n", 779 readl(base + OHCI_CONTROL)); 780 } 781 #endif 782 783 /* disable interrupts */ 784 writel((u32) ~0, base + OHCI_INTRDISABLE); 785 786 /* Go into the USB_RESET state, preserving RWC (and possibly IR) */ 787 writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL); 788 readl(base + OHCI_CONTROL); 789 790 /* software reset of the controller, preserving HcFmInterval */ 791 if (!no_fminterval) 792 fminterval = readl(base + OHCI_FMINTERVAL); 793 794 writel(OHCI_HCR, base + OHCI_CMDSTATUS); 795 796 /* reset requires max 10 us delay */ 797 for (cnt = 30; cnt > 0; --cnt) { /* ... allow extra time */ 798 if ((readl(base + OHCI_CMDSTATUS) & OHCI_HCR) == 0) 799 break; 800 udelay(1); 801 } 802 803 if (!no_fminterval) 804 writel(fminterval, base + OHCI_FMINTERVAL); 805 806 /* Now the controller is safely in SUSPEND and nothing can wake it up */ 807 iounmap(base); 808 } 809 810 static const struct dmi_system_id ehci_dmi_nohandoff_table[] = { 811 { 812 /* Pegatron Lucid (ExoPC) */ 813 .matches = { 814 DMI_MATCH(DMI_BOARD_NAME, "EXOPG06411"), 815 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-CE-133"), 816 }, 817 }, 818 { 819 /* Pegatron Lucid (Ordissimo AIRIS) */ 820 .matches = { 821 DMI_MATCH(DMI_BOARD_NAME, "M11JB"), 822 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"), 823 }, 824 }, 825 { 826 /* Pegatron Lucid (Ordissimo) */ 827 .matches = { 828 DMI_MATCH(DMI_BOARD_NAME, "Ordissimo"), 829 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"), 830 }, 831 }, 832 { 833 /* HASEE E200 */ 834 .matches = { 835 DMI_MATCH(DMI_BOARD_VENDOR, "HASEE"), 836 DMI_MATCH(DMI_BOARD_NAME, "E210"), 837 DMI_MATCH(DMI_BIOS_VERSION, "6.00"), 838 }, 839 }, 840 { } 841 }; 842 843 static void ehci_bios_handoff(struct pci_dev *pdev, 844 void __iomem *op_reg_base, 845 u32 cap, u8 offset) 846 { 847 int try_handoff = 1, tried_handoff = 0; 848 849 /* 850 * The Pegatron Lucid tablet sporadically waits for 98 seconds trying 851 * the handoff on its unused controller. Skip it. 852 * 853 * The HASEE E200 hangs when the semaphore is set (bugzilla #77021). 854 */ 855 if (pdev->vendor == 0x8086 && (pdev->device == 0x283a || 856 pdev->device == 0x27cc)) { 857 if (dmi_check_system(ehci_dmi_nohandoff_table)) 858 try_handoff = 0; 859 } 860 861 if (try_handoff && (cap & EHCI_USBLEGSUP_BIOS)) { 862 dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n"); 863 864 #if 0 865 /* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on, 866 * but that seems dubious in general (the BIOS left it off intentionally) 867 * and is known to prevent some systems from booting. so we won't do this 868 * unless maybe we can determine when we're on a system that needs SMI forced. 869 */ 870 /* BIOS workaround (?): be sure the pre-Linux code 871 * receives the SMI 872 */ 873 pci_read_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, &val); 874 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 875 val | EHCI_USBLEGCTLSTS_SOOE); 876 #endif 877 878 /* some systems get upset if this semaphore is 879 * set for any other reason than forcing a BIOS 880 * handoff.. 881 */ 882 pci_write_config_byte(pdev, offset + 3, 1); 883 } 884 885 /* if boot firmware now owns EHCI, spin till it hands it over. */ 886 if (try_handoff) { 887 int msec = 1000; 888 while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) { 889 tried_handoff = 1; 890 msleep(10); 891 msec -= 10; 892 pci_read_config_dword(pdev, offset, &cap); 893 } 894 } 895 896 if (cap & EHCI_USBLEGSUP_BIOS) { 897 /* well, possibly buggy BIOS... try to shut it down, 898 * and hope nothing goes too wrong 899 */ 900 if (try_handoff) 901 dev_warn(&pdev->dev, 902 "EHCI: BIOS handoff failed (BIOS bug?) %08x\n", 903 cap); 904 pci_write_config_byte(pdev, offset + 2, 0); 905 } 906 907 /* just in case, always disable EHCI SMIs */ 908 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 0); 909 910 /* If the BIOS ever owned the controller then we can't expect 911 * any power sessions to remain intact. 912 */ 913 if (tried_handoff) 914 writel(0, op_reg_base + EHCI_CONFIGFLAG); 915 } 916 917 static void quirk_usb_disable_ehci(struct pci_dev *pdev) 918 { 919 void __iomem *base, *op_reg_base; 920 u32 hcc_params, cap, val; 921 u8 offset, cap_length; 922 int wait_time, count = 256/4; 923 924 if (!mmio_resource_enabled(pdev, 0)) 925 return; 926 927 base = pci_ioremap_bar(pdev, 0); 928 if (base == NULL) 929 return; 930 931 cap_length = readb(base); 932 op_reg_base = base + cap_length; 933 934 /* EHCI 0.96 and later may have "extended capabilities" 935 * spec section 5.1 explains the bios handoff, e.g. for 936 * booting from USB disk or using a usb keyboard 937 */ 938 hcc_params = readl(base + EHCI_HCC_PARAMS); 939 offset = (hcc_params >> 8) & 0xff; 940 while (offset && --count) { 941 pci_read_config_dword(pdev, offset, &cap); 942 943 switch (cap & 0xff) { 944 case 1: 945 ehci_bios_handoff(pdev, op_reg_base, cap, offset); 946 break; 947 case 0: /* Illegal reserved cap, set cap=0 so we exit */ 948 cap = 0; /* fall through */ 949 default: 950 dev_warn(&pdev->dev, 951 "EHCI: unrecognized capability %02x\n", 952 cap & 0xff); 953 } 954 offset = (cap >> 8) & 0xff; 955 } 956 if (!count) 957 dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n"); 958 959 /* 960 * halt EHCI & disable its interrupts in any case 961 */ 962 val = readl(op_reg_base + EHCI_USBSTS); 963 if ((val & EHCI_USBSTS_HALTED) == 0) { 964 val = readl(op_reg_base + EHCI_USBCMD); 965 val &= ~EHCI_USBCMD_RUN; 966 writel(val, op_reg_base + EHCI_USBCMD); 967 968 wait_time = 2000; 969 do { 970 writel(0x3f, op_reg_base + EHCI_USBSTS); 971 udelay(100); 972 wait_time -= 100; 973 val = readl(op_reg_base + EHCI_USBSTS); 974 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) { 975 break; 976 } 977 } while (wait_time > 0); 978 } 979 writel(0, op_reg_base + EHCI_USBINTR); 980 writel(0x3f, op_reg_base + EHCI_USBSTS); 981 982 iounmap(base); 983 } 984 985 /* 986 * handshake - spin reading a register until handshake completes 987 * @ptr: address of hc register to be read 988 * @mask: bits to look at in result of read 989 * @done: value of those bits when handshake succeeds 990 * @wait_usec: timeout in microseconds 991 * @delay_usec: delay in microseconds to wait between polling 992 * 993 * Polls a register every delay_usec microseconds. 994 * Returns 0 when the mask bits have the value done. 995 * Returns -ETIMEDOUT if this condition is not true after 996 * wait_usec microseconds have passed. 997 */ 998 static int handshake(void __iomem *ptr, u32 mask, u32 done, 999 int wait_usec, int delay_usec) 1000 { 1001 u32 result; 1002 1003 do { 1004 result = readl(ptr); 1005 result &= mask; 1006 if (result == done) 1007 return 0; 1008 udelay(delay_usec); 1009 wait_usec -= delay_usec; 1010 } while (wait_usec > 0); 1011 return -ETIMEDOUT; 1012 } 1013 1014 /* 1015 * Intel's Panther Point chipset has two host controllers (EHCI and xHCI) that 1016 * share some number of ports. These ports can be switched between either 1017 * controller. Not all of the ports under the EHCI host controller may be 1018 * switchable. 1019 * 1020 * The ports should be switched over to xHCI before PCI probes for any device 1021 * start. This avoids active devices under EHCI being disconnected during the 1022 * port switchover, which could cause loss of data on USB storage devices, or 1023 * failed boot when the root file system is on a USB mass storage device and is 1024 * enumerated under EHCI first. 1025 * 1026 * We write into the xHC's PCI configuration space in some Intel-specific 1027 * registers to switch the ports over. The USB 3.0 terminations and the USB 1028 * 2.0 data wires are switched separately. We want to enable the SuperSpeed 1029 * terminations before switching the USB 2.0 wires over, so that USB 3.0 1030 * devices connect at SuperSpeed, rather than at USB 2.0 speeds. 1031 */ 1032 void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev) 1033 { 1034 u32 ports_available; 1035 bool ehci_found = false; 1036 struct pci_dev *companion = NULL; 1037 1038 /* Sony VAIO t-series with subsystem device ID 90a8 is not capable of 1039 * switching ports from EHCI to xHCI 1040 */ 1041 if (xhci_pdev->subsystem_vendor == PCI_VENDOR_ID_SONY && 1042 xhci_pdev->subsystem_device == 0x90a8) 1043 return; 1044 1045 /* make sure an intel EHCI controller exists */ 1046 for_each_pci_dev(companion) { 1047 if (companion->class == PCI_CLASS_SERIAL_USB_EHCI && 1048 companion->vendor == PCI_VENDOR_ID_INTEL) { 1049 ehci_found = true; 1050 break; 1051 } 1052 } 1053 1054 if (!ehci_found) 1055 return; 1056 1057 /* Don't switchover the ports if the user hasn't compiled the xHCI 1058 * driver. Otherwise they will see "dead" USB ports that don't power 1059 * the devices. 1060 */ 1061 if (!IS_ENABLED(CONFIG_USB_XHCI_HCD)) { 1062 dev_warn(&xhci_pdev->dev, 1063 "CONFIG_USB_XHCI_HCD is turned off, defaulting to EHCI.\n"); 1064 dev_warn(&xhci_pdev->dev, 1065 "USB 3.0 devices will work at USB 2.0 speeds.\n"); 1066 usb_disable_xhci_ports(xhci_pdev); 1067 return; 1068 } 1069 1070 /* Read USB3PRM, the USB 3.0 Port Routing Mask Register 1071 * Indicate the ports that can be changed from OS. 1072 */ 1073 pci_read_config_dword(xhci_pdev, USB_INTEL_USB3PRM, 1074 &ports_available); 1075 1076 dev_dbg(&xhci_pdev->dev, "Configurable ports to enable SuperSpeed: 0x%x\n", 1077 ports_available); 1078 1079 /* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable 1080 * Register, to turn on SuperSpeed terminations for the 1081 * switchable ports. 1082 */ 1083 pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, 1084 ports_available); 1085 1086 pci_read_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, 1087 &ports_available); 1088 dev_dbg(&xhci_pdev->dev, 1089 "USB 3.0 ports that are now enabled under xHCI: 0x%x\n", 1090 ports_available); 1091 1092 /* Read XUSB2PRM, xHCI USB 2.0 Port Routing Mask Register 1093 * Indicate the USB 2.0 ports to be controlled by the xHCI host. 1094 */ 1095 1096 pci_read_config_dword(xhci_pdev, USB_INTEL_USB2PRM, 1097 &ports_available); 1098 1099 dev_dbg(&xhci_pdev->dev, "Configurable USB 2.0 ports to hand over to xCHI: 0x%x\n", 1100 ports_available); 1101 1102 /* Write XUSB2PR, the xHC USB 2.0 Port Routing Register, to 1103 * switch the USB 2.0 power and data lines over to the xHCI 1104 * host. 1105 */ 1106 pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, 1107 ports_available); 1108 1109 pci_read_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, 1110 &ports_available); 1111 dev_dbg(&xhci_pdev->dev, 1112 "USB 2.0 ports that are now switched over to xHCI: 0x%x\n", 1113 ports_available); 1114 } 1115 EXPORT_SYMBOL_GPL(usb_enable_intel_xhci_ports); 1116 1117 void usb_disable_xhci_ports(struct pci_dev *xhci_pdev) 1118 { 1119 pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, 0x0); 1120 pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, 0x0); 1121 } 1122 EXPORT_SYMBOL_GPL(usb_disable_xhci_ports); 1123 1124 /** 1125 * PCI Quirks for xHCI. 1126 * 1127 * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS. 1128 * It signals to the BIOS that the OS wants control of the host controller, 1129 * and then waits 1 second for the BIOS to hand over control. 1130 * If we timeout, assume the BIOS is broken and take control anyway. 1131 */ 1132 static void quirk_usb_handoff_xhci(struct pci_dev *pdev) 1133 { 1134 void __iomem *base; 1135 int ext_cap_offset; 1136 void __iomem *op_reg_base; 1137 u32 val; 1138 int timeout; 1139 int len = pci_resource_len(pdev, 0); 1140 1141 if (!mmio_resource_enabled(pdev, 0)) 1142 return; 1143 1144 base = ioremap_nocache(pci_resource_start(pdev, 0), len); 1145 if (base == NULL) 1146 return; 1147 1148 /* 1149 * Find the Legacy Support Capability register - 1150 * this is optional for xHCI host controllers. 1151 */ 1152 ext_cap_offset = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_LEGACY); 1153 1154 if (!ext_cap_offset) 1155 goto hc_init; 1156 1157 if ((ext_cap_offset + sizeof(val)) > len) { 1158 /* We're reading garbage from the controller */ 1159 dev_warn(&pdev->dev, "xHCI controller failing to respond"); 1160 goto iounmap; 1161 } 1162 val = readl(base + ext_cap_offset); 1163 1164 /* Auto handoff never worked for these devices. Force it and continue */ 1165 if ((pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) || 1166 (pdev->vendor == PCI_VENDOR_ID_RENESAS 1167 && pdev->device == 0x0014)) { 1168 val = (val | XHCI_HC_OS_OWNED) & ~XHCI_HC_BIOS_OWNED; 1169 writel(val, base + ext_cap_offset); 1170 } 1171 1172 /* If the BIOS owns the HC, signal that the OS wants it, and wait */ 1173 if (val & XHCI_HC_BIOS_OWNED) { 1174 writel(val | XHCI_HC_OS_OWNED, base + ext_cap_offset); 1175 1176 /* Wait for 1 second with 10 microsecond polling interval */ 1177 timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED, 1178 0, 1000000, 10); 1179 1180 /* Assume a buggy BIOS and take HC ownership anyway */ 1181 if (timeout) { 1182 dev_warn(&pdev->dev, 1183 "xHCI BIOS handoff failed (BIOS bug ?) %08x\n", 1184 val); 1185 writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset); 1186 } 1187 } 1188 1189 val = readl(base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET); 1190 /* Mask off (turn off) any enabled SMIs */ 1191 val &= XHCI_LEGACY_DISABLE_SMI; 1192 /* Mask all SMI events bits, RW1C */ 1193 val |= XHCI_LEGACY_SMI_EVENTS; 1194 /* Disable any BIOS SMIs and clear all SMI events*/ 1195 writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET); 1196 1197 hc_init: 1198 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 1199 usb_enable_intel_xhci_ports(pdev); 1200 1201 op_reg_base = base + XHCI_HC_LENGTH(readl(base)); 1202 1203 /* Wait for the host controller to be ready before writing any 1204 * operational or runtime registers. Wait 5 seconds and no more. 1205 */ 1206 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0, 1207 5000000, 10); 1208 /* Assume a buggy HC and start HC initialization anyway */ 1209 if (timeout) { 1210 val = readl(op_reg_base + XHCI_STS_OFFSET); 1211 dev_warn(&pdev->dev, 1212 "xHCI HW not ready after 5 sec (HC bug?) status = 0x%x\n", 1213 val); 1214 } 1215 1216 /* Send the halt and disable interrupts command */ 1217 val = readl(op_reg_base + XHCI_CMD_OFFSET); 1218 val &= ~(XHCI_CMD_RUN | XHCI_IRQS); 1219 writel(val, op_reg_base + XHCI_CMD_OFFSET); 1220 1221 /* Wait for the HC to halt - poll every 125 usec (one microframe). */ 1222 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1, 1223 XHCI_MAX_HALT_USEC, 125); 1224 if (timeout) { 1225 val = readl(op_reg_base + XHCI_STS_OFFSET); 1226 dev_warn(&pdev->dev, 1227 "xHCI HW did not halt within %d usec status = 0x%x\n", 1228 XHCI_MAX_HALT_USEC, val); 1229 } 1230 1231 iounmap: 1232 iounmap(base); 1233 } 1234 1235 static void quirk_usb_early_handoff(struct pci_dev *pdev) 1236 { 1237 /* Skip Netlogic mips SoC's internal PCI USB controller. 1238 * This device does not need/support EHCI/OHCI handoff 1239 */ 1240 if (pdev->vendor == 0x184e) /* vendor Netlogic */ 1241 return; 1242 if (pdev->class != PCI_CLASS_SERIAL_USB_UHCI && 1243 pdev->class != PCI_CLASS_SERIAL_USB_OHCI && 1244 pdev->class != PCI_CLASS_SERIAL_USB_EHCI && 1245 pdev->class != PCI_CLASS_SERIAL_USB_XHCI) 1246 return; 1247 1248 if (pci_enable_device(pdev) < 0) { 1249 dev_warn(&pdev->dev, 1250 "Can't enable PCI device, BIOS handoff failed.\n"); 1251 return; 1252 } 1253 if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI) 1254 quirk_usb_handoff_uhci(pdev); 1255 else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI) 1256 quirk_usb_handoff_ohci(pdev); 1257 else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI) 1258 quirk_usb_disable_ehci(pdev); 1259 else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI) 1260 quirk_usb_handoff_xhci(pdev); 1261 pci_disable_device(pdev); 1262 } 1263 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1264 PCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff); 1265