1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains code to reset and initialize USB host controllers. 4 * Some of it includes work-arounds for PCI hardware and BIOS quirks. 5 * It may need to run early during booting -- before USB would normally 6 * initialize -- to ensure that Linux doesn't use any legacy modes. 7 * 8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 9 * (and others) 10 */ 11 12 #include <linux/types.h> 13 #include <linux/kernel.h> 14 #include <linux/pci.h> 15 #include <linux/delay.h> 16 #include <linux/export.h> 17 #include <linux/acpi.h> 18 #include <linux/dmi.h> 19 #include "pci-quirks.h" 20 #include "xhci-ext-caps.h" 21 22 23 #define UHCI_USBLEGSUP 0xc0 /* legacy support */ 24 #define UHCI_USBCMD 0 /* command register */ 25 #define UHCI_USBINTR 4 /* interrupt register */ 26 #define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */ 27 #define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */ 28 #define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */ 29 #define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */ 30 #define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */ 31 #define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */ 32 #define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */ 33 34 #define OHCI_CONTROL 0x04 35 #define OHCI_CMDSTATUS 0x08 36 #define OHCI_INTRSTATUS 0x0c 37 #define OHCI_INTRENABLE 0x10 38 #define OHCI_INTRDISABLE 0x14 39 #define OHCI_FMINTERVAL 0x34 40 #define OHCI_HCFS (3 << 6) /* hc functional state */ 41 #define OHCI_HCR (1 << 0) /* host controller reset */ 42 #define OHCI_OCR (1 << 3) /* ownership change request */ 43 #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ 44 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ 45 #define OHCI_INTR_OC (1 << 30) /* ownership change */ 46 47 #define EHCI_HCC_PARAMS 0x08 /* extended capabilities */ 48 #define EHCI_USBCMD 0 /* command register */ 49 #define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */ 50 #define EHCI_USBSTS 4 /* status register */ 51 #define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */ 52 #define EHCI_USBINTR 8 /* interrupt register */ 53 #define EHCI_CONFIGFLAG 0x40 /* configured flag register */ 54 #define EHCI_USBLEGSUP 0 /* legacy support register */ 55 #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */ 56 #define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */ 57 #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */ 58 #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */ 59 60 /* AMD quirk use */ 61 #define AB_REG_BAR_LOW 0xe0 62 #define AB_REG_BAR_HIGH 0xe1 63 #define AB_REG_BAR_SB700 0xf0 64 #define AB_INDX(addr) ((addr) + 0x00) 65 #define AB_DATA(addr) ((addr) + 0x04) 66 #define AX_INDXC 0x30 67 #define AX_DATAC 0x34 68 69 #define NB_PCIE_INDX_ADDR 0xe0 70 #define NB_PCIE_INDX_DATA 0xe4 71 #define PCIE_P_CNTL 0x10040 72 #define BIF_NB 0x10002 73 #define NB_PIF0_PWRDOWN_0 0x01100012 74 #define NB_PIF0_PWRDOWN_1 0x01100013 75 76 #define USB_INTEL_XUSB2PR 0xD0 77 #define USB_INTEL_USB2PRM 0xD4 78 #define USB_INTEL_USB3_PSSEN 0xD8 79 #define USB_INTEL_USB3PRM 0xDC 80 81 /* ASMEDIA quirk use */ 82 #define ASMT_DATA_WRITE0_REG 0xF8 83 #define ASMT_DATA_WRITE1_REG 0xFC 84 #define ASMT_CONTROL_REG 0xE0 85 #define ASMT_CONTROL_WRITE_BIT 0x02 86 #define ASMT_WRITEREG_CMD 0x10423 87 #define ASMT_FLOWCTL_ADDR 0xFA30 88 #define ASMT_FLOWCTL_DATA 0xBA 89 #define ASMT_PSEUDO_DATA 0 90 91 /* 92 * amd_chipset_gen values represent AMD different chipset generations 93 */ 94 enum amd_chipset_gen { 95 NOT_AMD_CHIPSET = 0, 96 AMD_CHIPSET_SB600, 97 AMD_CHIPSET_SB700, 98 AMD_CHIPSET_SB800, 99 AMD_CHIPSET_HUDSON2, 100 AMD_CHIPSET_BOLTON, 101 AMD_CHIPSET_YANGTZE, 102 AMD_CHIPSET_TAISHAN, 103 AMD_CHIPSET_UNKNOWN, 104 }; 105 106 struct amd_chipset_type { 107 enum amd_chipset_gen gen; 108 u8 rev; 109 }; 110 111 static struct amd_chipset_info { 112 struct pci_dev *nb_dev; 113 struct pci_dev *smbus_dev; 114 int nb_type; 115 struct amd_chipset_type sb_type; 116 int isoc_reqs; 117 int probe_count; 118 int probe_result; 119 } amd_chipset; 120 121 static DEFINE_SPINLOCK(amd_lock); 122 123 /* 124 * amd_chipset_sb_type_init - initialize amd chipset southbridge type 125 * 126 * AMD FCH/SB generation and revision is identified by SMBus controller 127 * vendor, device and revision IDs. 128 * 129 * Returns: 1 if it is an AMD chipset, 0 otherwise. 130 */ 131 static int amd_chipset_sb_type_init(struct amd_chipset_info *pinfo) 132 { 133 u8 rev = 0; 134 pinfo->sb_type.gen = AMD_CHIPSET_UNKNOWN; 135 136 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 137 PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL); 138 if (pinfo->smbus_dev) { 139 rev = pinfo->smbus_dev->revision; 140 if (rev >= 0x10 && rev <= 0x1f) 141 pinfo->sb_type.gen = AMD_CHIPSET_SB600; 142 else if (rev >= 0x30 && rev <= 0x3f) 143 pinfo->sb_type.gen = AMD_CHIPSET_SB700; 144 else if (rev >= 0x40 && rev <= 0x4f) 145 pinfo->sb_type.gen = AMD_CHIPSET_SB800; 146 } else { 147 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 148 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 149 150 if (pinfo->smbus_dev) { 151 rev = pinfo->smbus_dev->revision; 152 if (rev >= 0x11 && rev <= 0x14) 153 pinfo->sb_type.gen = AMD_CHIPSET_HUDSON2; 154 else if (rev >= 0x15 && rev <= 0x18) 155 pinfo->sb_type.gen = AMD_CHIPSET_BOLTON; 156 else if (rev >= 0x39 && rev <= 0x3a) 157 pinfo->sb_type.gen = AMD_CHIPSET_YANGTZE; 158 } else { 159 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 160 0x145c, NULL); 161 if (pinfo->smbus_dev) { 162 rev = pinfo->smbus_dev->revision; 163 pinfo->sb_type.gen = AMD_CHIPSET_TAISHAN; 164 } else { 165 pinfo->sb_type.gen = NOT_AMD_CHIPSET; 166 return 0; 167 } 168 } 169 } 170 pinfo->sb_type.rev = rev; 171 return 1; 172 } 173 174 void sb800_prefetch(struct device *dev, int on) 175 { 176 u16 misc; 177 struct pci_dev *pdev = to_pci_dev(dev); 178 179 pci_read_config_word(pdev, 0x50, &misc); 180 if (on == 0) 181 pci_write_config_word(pdev, 0x50, misc & 0xfcff); 182 else 183 pci_write_config_word(pdev, 0x50, misc | 0x0300); 184 } 185 EXPORT_SYMBOL_GPL(sb800_prefetch); 186 187 int usb_amd_find_chipset_info(void) 188 { 189 unsigned long flags; 190 struct amd_chipset_info info; 191 int ret; 192 193 spin_lock_irqsave(&amd_lock, flags); 194 195 /* probe only once */ 196 if (amd_chipset.probe_count > 0) { 197 amd_chipset.probe_count++; 198 spin_unlock_irqrestore(&amd_lock, flags); 199 return amd_chipset.probe_result; 200 } 201 memset(&info, 0, sizeof(info)); 202 spin_unlock_irqrestore(&amd_lock, flags); 203 204 if (!amd_chipset_sb_type_init(&info)) { 205 ret = 0; 206 goto commit; 207 } 208 209 /* Below chipset generations needn't enable AMD PLL quirk */ 210 if (info.sb_type.gen == AMD_CHIPSET_UNKNOWN || 211 info.sb_type.gen == AMD_CHIPSET_SB600 || 212 info.sb_type.gen == AMD_CHIPSET_YANGTZE || 213 (info.sb_type.gen == AMD_CHIPSET_SB700 && 214 info.sb_type.rev > 0x3b)) { 215 if (info.smbus_dev) { 216 pci_dev_put(info.smbus_dev); 217 info.smbus_dev = NULL; 218 } 219 ret = 0; 220 goto commit; 221 } 222 223 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL); 224 if (info.nb_dev) { 225 info.nb_type = 1; 226 } else { 227 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL); 228 if (info.nb_dev) { 229 info.nb_type = 2; 230 } else { 231 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 232 0x9600, NULL); 233 if (info.nb_dev) 234 info.nb_type = 3; 235 } 236 } 237 238 ret = info.probe_result = 1; 239 printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n"); 240 241 commit: 242 243 spin_lock_irqsave(&amd_lock, flags); 244 if (amd_chipset.probe_count > 0) { 245 /* race - someone else was faster - drop devices */ 246 247 /* Mark that we where here */ 248 amd_chipset.probe_count++; 249 ret = amd_chipset.probe_result; 250 251 spin_unlock_irqrestore(&amd_lock, flags); 252 253 pci_dev_put(info.nb_dev); 254 pci_dev_put(info.smbus_dev); 255 256 } else { 257 /* no race - commit the result */ 258 info.probe_count++; 259 amd_chipset = info; 260 spin_unlock_irqrestore(&amd_lock, flags); 261 } 262 263 return ret; 264 } 265 EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info); 266 267 int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *pdev) 268 { 269 /* Make sure amd chipset type has already been initialized */ 270 usb_amd_find_chipset_info(); 271 if (amd_chipset.sb_type.gen == AMD_CHIPSET_YANGTZE || 272 amd_chipset.sb_type.gen == AMD_CHIPSET_TAISHAN) { 273 dev_dbg(&pdev->dev, "QUIRK: Enable AMD remote wakeup fix\n"); 274 return 1; 275 } 276 return 0; 277 } 278 EXPORT_SYMBOL_GPL(usb_hcd_amd_remote_wakeup_quirk); 279 280 bool usb_amd_hang_symptom_quirk(void) 281 { 282 u8 rev; 283 284 usb_amd_find_chipset_info(); 285 rev = amd_chipset.sb_type.rev; 286 /* SB600 and old version of SB700 have hang symptom bug */ 287 return amd_chipset.sb_type.gen == AMD_CHIPSET_SB600 || 288 (amd_chipset.sb_type.gen == AMD_CHIPSET_SB700 && 289 rev >= 0x3a && rev <= 0x3b); 290 } 291 EXPORT_SYMBOL_GPL(usb_amd_hang_symptom_quirk); 292 293 bool usb_amd_prefetch_quirk(void) 294 { 295 usb_amd_find_chipset_info(); 296 /* SB800 needs pre-fetch fix */ 297 return amd_chipset.sb_type.gen == AMD_CHIPSET_SB800; 298 } 299 EXPORT_SYMBOL_GPL(usb_amd_prefetch_quirk); 300 301 /* 302 * The hardware normally enables the A-link power management feature, which 303 * lets the system lower the power consumption in idle states. 304 * 305 * This USB quirk prevents the link going into that lower power state 306 * during isochronous transfers. 307 * 308 * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of 309 * some AMD platforms may stutter or have breaks occasionally. 310 */ 311 static void usb_amd_quirk_pll(int disable) 312 { 313 u32 addr, addr_low, addr_high, val; 314 u32 bit = disable ? 0 : 1; 315 unsigned long flags; 316 317 spin_lock_irqsave(&amd_lock, flags); 318 319 if (disable) { 320 amd_chipset.isoc_reqs++; 321 if (amd_chipset.isoc_reqs > 1) { 322 spin_unlock_irqrestore(&amd_lock, flags); 323 return; 324 } 325 } else { 326 amd_chipset.isoc_reqs--; 327 if (amd_chipset.isoc_reqs > 0) { 328 spin_unlock_irqrestore(&amd_lock, flags); 329 return; 330 } 331 } 332 333 if (amd_chipset.sb_type.gen == AMD_CHIPSET_SB800 || 334 amd_chipset.sb_type.gen == AMD_CHIPSET_HUDSON2 || 335 amd_chipset.sb_type.gen == AMD_CHIPSET_BOLTON) { 336 outb_p(AB_REG_BAR_LOW, 0xcd6); 337 addr_low = inb_p(0xcd7); 338 outb_p(AB_REG_BAR_HIGH, 0xcd6); 339 addr_high = inb_p(0xcd7); 340 addr = addr_high << 8 | addr_low; 341 342 outl_p(0x30, AB_INDX(addr)); 343 outl_p(0x40, AB_DATA(addr)); 344 outl_p(0x34, AB_INDX(addr)); 345 val = inl_p(AB_DATA(addr)); 346 } else if (amd_chipset.sb_type.gen == AMD_CHIPSET_SB700 && 347 amd_chipset.sb_type.rev <= 0x3b) { 348 pci_read_config_dword(amd_chipset.smbus_dev, 349 AB_REG_BAR_SB700, &addr); 350 outl(AX_INDXC, AB_INDX(addr)); 351 outl(0x40, AB_DATA(addr)); 352 outl(AX_DATAC, AB_INDX(addr)); 353 val = inl(AB_DATA(addr)); 354 } else { 355 spin_unlock_irqrestore(&amd_lock, flags); 356 return; 357 } 358 359 if (disable) { 360 val &= ~0x08; 361 val |= (1 << 4) | (1 << 9); 362 } else { 363 val |= 0x08; 364 val &= ~((1 << 4) | (1 << 9)); 365 } 366 outl_p(val, AB_DATA(addr)); 367 368 if (!amd_chipset.nb_dev) { 369 spin_unlock_irqrestore(&amd_lock, flags); 370 return; 371 } 372 373 if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) { 374 addr = PCIE_P_CNTL; 375 pci_write_config_dword(amd_chipset.nb_dev, 376 NB_PCIE_INDX_ADDR, addr); 377 pci_read_config_dword(amd_chipset.nb_dev, 378 NB_PCIE_INDX_DATA, &val); 379 380 val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12)); 381 val |= bit | (bit << 3) | (bit << 12); 382 val |= ((!bit) << 4) | ((!bit) << 9); 383 pci_write_config_dword(amd_chipset.nb_dev, 384 NB_PCIE_INDX_DATA, val); 385 386 addr = BIF_NB; 387 pci_write_config_dword(amd_chipset.nb_dev, 388 NB_PCIE_INDX_ADDR, addr); 389 pci_read_config_dword(amd_chipset.nb_dev, 390 NB_PCIE_INDX_DATA, &val); 391 val &= ~(1 << 8); 392 val |= bit << 8; 393 394 pci_write_config_dword(amd_chipset.nb_dev, 395 NB_PCIE_INDX_DATA, val); 396 } else if (amd_chipset.nb_type == 2) { 397 addr = NB_PIF0_PWRDOWN_0; 398 pci_write_config_dword(amd_chipset.nb_dev, 399 NB_PCIE_INDX_ADDR, addr); 400 pci_read_config_dword(amd_chipset.nb_dev, 401 NB_PCIE_INDX_DATA, &val); 402 if (disable) 403 val &= ~(0x3f << 7); 404 else 405 val |= 0x3f << 7; 406 407 pci_write_config_dword(amd_chipset.nb_dev, 408 NB_PCIE_INDX_DATA, val); 409 410 addr = NB_PIF0_PWRDOWN_1; 411 pci_write_config_dword(amd_chipset.nb_dev, 412 NB_PCIE_INDX_ADDR, addr); 413 pci_read_config_dword(amd_chipset.nb_dev, 414 NB_PCIE_INDX_DATA, &val); 415 if (disable) 416 val &= ~(0x3f << 7); 417 else 418 val |= 0x3f << 7; 419 420 pci_write_config_dword(amd_chipset.nb_dev, 421 NB_PCIE_INDX_DATA, val); 422 } 423 424 spin_unlock_irqrestore(&amd_lock, flags); 425 return; 426 } 427 428 void usb_amd_quirk_pll_disable(void) 429 { 430 usb_amd_quirk_pll(1); 431 } 432 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable); 433 434 static int usb_asmedia_wait_write(struct pci_dev *pdev) 435 { 436 unsigned long retry_count; 437 unsigned char value; 438 439 for (retry_count = 1000; retry_count > 0; --retry_count) { 440 441 pci_read_config_byte(pdev, ASMT_CONTROL_REG, &value); 442 443 if (value == 0xff) { 444 dev_err(&pdev->dev, "%s: check_ready ERROR", __func__); 445 return -EIO; 446 } 447 448 if ((value & ASMT_CONTROL_WRITE_BIT) == 0) 449 return 0; 450 451 udelay(50); 452 } 453 454 dev_warn(&pdev->dev, "%s: check_write_ready timeout", __func__); 455 return -ETIMEDOUT; 456 } 457 458 void usb_asmedia_modifyflowcontrol(struct pci_dev *pdev) 459 { 460 if (usb_asmedia_wait_write(pdev) != 0) 461 return; 462 463 /* send command and address to device */ 464 pci_write_config_dword(pdev, ASMT_DATA_WRITE0_REG, ASMT_WRITEREG_CMD); 465 pci_write_config_dword(pdev, ASMT_DATA_WRITE1_REG, ASMT_FLOWCTL_ADDR); 466 pci_write_config_byte(pdev, ASMT_CONTROL_REG, ASMT_CONTROL_WRITE_BIT); 467 468 if (usb_asmedia_wait_write(pdev) != 0) 469 return; 470 471 /* send data to device */ 472 pci_write_config_dword(pdev, ASMT_DATA_WRITE0_REG, ASMT_FLOWCTL_DATA); 473 pci_write_config_dword(pdev, ASMT_DATA_WRITE1_REG, ASMT_PSEUDO_DATA); 474 pci_write_config_byte(pdev, ASMT_CONTROL_REG, ASMT_CONTROL_WRITE_BIT); 475 } 476 EXPORT_SYMBOL_GPL(usb_asmedia_modifyflowcontrol); 477 478 void usb_amd_quirk_pll_enable(void) 479 { 480 usb_amd_quirk_pll(0); 481 } 482 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable); 483 484 void usb_amd_dev_put(void) 485 { 486 struct pci_dev *nb, *smbus; 487 unsigned long flags; 488 489 spin_lock_irqsave(&amd_lock, flags); 490 491 amd_chipset.probe_count--; 492 if (amd_chipset.probe_count > 0) { 493 spin_unlock_irqrestore(&amd_lock, flags); 494 return; 495 } 496 497 /* save them to pci_dev_put outside of spinlock */ 498 nb = amd_chipset.nb_dev; 499 smbus = amd_chipset.smbus_dev; 500 501 amd_chipset.nb_dev = NULL; 502 amd_chipset.smbus_dev = NULL; 503 amd_chipset.nb_type = 0; 504 memset(&amd_chipset.sb_type, 0, sizeof(amd_chipset.sb_type)); 505 amd_chipset.isoc_reqs = 0; 506 amd_chipset.probe_result = 0; 507 508 spin_unlock_irqrestore(&amd_lock, flags); 509 510 pci_dev_put(nb); 511 pci_dev_put(smbus); 512 } 513 EXPORT_SYMBOL_GPL(usb_amd_dev_put); 514 515 /* 516 * Make sure the controller is completely inactive, unable to 517 * generate interrupts or do DMA. 518 */ 519 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base) 520 { 521 /* Turn off PIRQ enable and SMI enable. (This also turns off the 522 * BIOS's USB Legacy Support.) Turn off all the R/WC bits too. 523 */ 524 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC); 525 526 /* Reset the HC - this will force us to get a 527 * new notification of any already connected 528 * ports due to the virtual disconnect that it 529 * implies. 530 */ 531 outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD); 532 mb(); 533 udelay(5); 534 if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET) 535 dev_warn(&pdev->dev, "HCRESET not completed yet!\n"); 536 537 /* Just to be safe, disable interrupt requests and 538 * make sure the controller is stopped. 539 */ 540 outw(0, base + UHCI_USBINTR); 541 outw(0, base + UHCI_USBCMD); 542 } 543 EXPORT_SYMBOL_GPL(uhci_reset_hc); 544 545 /* 546 * Initialize a controller that was newly discovered or has just been 547 * resumed. In either case we can't be sure of its previous state. 548 * 549 * Returns: 1 if the controller was reset, 0 otherwise. 550 */ 551 int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base) 552 { 553 u16 legsup; 554 unsigned int cmd, intr; 555 556 /* 557 * When restarting a suspended controller, we expect all the 558 * settings to be the same as we left them: 559 * 560 * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP; 561 * Controller is stopped and configured with EGSM set; 562 * No interrupts enabled except possibly Resume Detect. 563 * 564 * If any of these conditions are violated we do a complete reset. 565 */ 566 pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup); 567 if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) { 568 dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n", 569 __func__, legsup); 570 goto reset_needed; 571 } 572 573 cmd = inw(base + UHCI_USBCMD); 574 if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) || 575 !(cmd & UHCI_USBCMD_EGSM)) { 576 dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n", 577 __func__, cmd); 578 goto reset_needed; 579 } 580 581 intr = inw(base + UHCI_USBINTR); 582 if (intr & (~UHCI_USBINTR_RESUME)) { 583 dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n", 584 __func__, intr); 585 goto reset_needed; 586 } 587 return 0; 588 589 reset_needed: 590 dev_dbg(&pdev->dev, "Performing full reset\n"); 591 uhci_reset_hc(pdev, base); 592 return 1; 593 } 594 EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc); 595 596 static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask) 597 { 598 u16 cmd; 599 return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask); 600 } 601 602 #define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO) 603 #define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY) 604 605 static void quirk_usb_handoff_uhci(struct pci_dev *pdev) 606 { 607 unsigned long base = 0; 608 int i; 609 610 if (!pio_enabled(pdev)) 611 return; 612 613 for (i = 0; i < PCI_ROM_RESOURCE; i++) 614 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) { 615 base = pci_resource_start(pdev, i); 616 break; 617 } 618 619 if (base) 620 uhci_check_and_reset_hc(pdev, base); 621 } 622 623 static int mmio_resource_enabled(struct pci_dev *pdev, int idx) 624 { 625 return pci_resource_start(pdev, idx) && mmio_enabled(pdev); 626 } 627 628 static void quirk_usb_handoff_ohci(struct pci_dev *pdev) 629 { 630 void __iomem *base; 631 u32 control; 632 u32 fminterval = 0; 633 bool no_fminterval = false; 634 int cnt; 635 636 if (!mmio_resource_enabled(pdev, 0)) 637 return; 638 639 base = pci_ioremap_bar(pdev, 0); 640 if (base == NULL) 641 return; 642 643 /* 644 * ULi M5237 OHCI controller locks the whole system when accessing 645 * the OHCI_FMINTERVAL offset. 646 */ 647 if (pdev->vendor == PCI_VENDOR_ID_AL && pdev->device == 0x5237) 648 no_fminterval = true; 649 650 control = readl(base + OHCI_CONTROL); 651 652 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ 653 #ifdef __hppa__ 654 #define OHCI_CTRL_MASK (OHCI_CTRL_RWC | OHCI_CTRL_IR) 655 #else 656 #define OHCI_CTRL_MASK OHCI_CTRL_RWC 657 658 if (control & OHCI_CTRL_IR) { 659 int wait_time = 500; /* arbitrary; 5 seconds */ 660 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE); 661 writel(OHCI_OCR, base + OHCI_CMDSTATUS); 662 while (wait_time > 0 && 663 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) { 664 wait_time -= 10; 665 msleep(10); 666 } 667 if (wait_time <= 0) 668 dev_warn(&pdev->dev, 669 "OHCI: BIOS handoff failed (BIOS bug?) %08x\n", 670 readl(base + OHCI_CONTROL)); 671 } 672 #endif 673 674 /* disable interrupts */ 675 writel((u32) ~0, base + OHCI_INTRDISABLE); 676 677 /* Reset the USB bus, if the controller isn't already in RESET */ 678 if (control & OHCI_HCFS) { 679 /* Go into RESET, preserving RWC (and possibly IR) */ 680 writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL); 681 readl(base + OHCI_CONTROL); 682 683 /* drive bus reset for at least 50 ms (7.1.7.5) */ 684 msleep(50); 685 } 686 687 /* software reset of the controller, preserving HcFmInterval */ 688 if (!no_fminterval) 689 fminterval = readl(base + OHCI_FMINTERVAL); 690 691 writel(OHCI_HCR, base + OHCI_CMDSTATUS); 692 693 /* reset requires max 10 us delay */ 694 for (cnt = 30; cnt > 0; --cnt) { /* ... allow extra time */ 695 if ((readl(base + OHCI_CMDSTATUS) & OHCI_HCR) == 0) 696 break; 697 udelay(1); 698 } 699 700 if (!no_fminterval) 701 writel(fminterval, base + OHCI_FMINTERVAL); 702 703 /* Now the controller is safely in SUSPEND and nothing can wake it up */ 704 iounmap(base); 705 } 706 707 static const struct dmi_system_id ehci_dmi_nohandoff_table[] = { 708 { 709 /* Pegatron Lucid (ExoPC) */ 710 .matches = { 711 DMI_MATCH(DMI_BOARD_NAME, "EXOPG06411"), 712 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-CE-133"), 713 }, 714 }, 715 { 716 /* Pegatron Lucid (Ordissimo AIRIS) */ 717 .matches = { 718 DMI_MATCH(DMI_BOARD_NAME, "M11JB"), 719 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"), 720 }, 721 }, 722 { 723 /* Pegatron Lucid (Ordissimo) */ 724 .matches = { 725 DMI_MATCH(DMI_BOARD_NAME, "Ordissimo"), 726 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"), 727 }, 728 }, 729 { 730 /* HASEE E200 */ 731 .matches = { 732 DMI_MATCH(DMI_BOARD_VENDOR, "HASEE"), 733 DMI_MATCH(DMI_BOARD_NAME, "E210"), 734 DMI_MATCH(DMI_BIOS_VERSION, "6.00"), 735 }, 736 }, 737 { } 738 }; 739 740 static void ehci_bios_handoff(struct pci_dev *pdev, 741 void __iomem *op_reg_base, 742 u32 cap, u8 offset) 743 { 744 int try_handoff = 1, tried_handoff = 0; 745 746 /* 747 * The Pegatron Lucid tablet sporadically waits for 98 seconds trying 748 * the handoff on its unused controller. Skip it. 749 * 750 * The HASEE E200 hangs when the semaphore is set (bugzilla #77021). 751 */ 752 if (pdev->vendor == 0x8086 && (pdev->device == 0x283a || 753 pdev->device == 0x27cc)) { 754 if (dmi_check_system(ehci_dmi_nohandoff_table)) 755 try_handoff = 0; 756 } 757 758 if (try_handoff && (cap & EHCI_USBLEGSUP_BIOS)) { 759 dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n"); 760 761 #if 0 762 /* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on, 763 * but that seems dubious in general (the BIOS left it off intentionally) 764 * and is known to prevent some systems from booting. so we won't do this 765 * unless maybe we can determine when we're on a system that needs SMI forced. 766 */ 767 /* BIOS workaround (?): be sure the pre-Linux code 768 * receives the SMI 769 */ 770 pci_read_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, &val); 771 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 772 val | EHCI_USBLEGCTLSTS_SOOE); 773 #endif 774 775 /* some systems get upset if this semaphore is 776 * set for any other reason than forcing a BIOS 777 * handoff.. 778 */ 779 pci_write_config_byte(pdev, offset + 3, 1); 780 } 781 782 /* if boot firmware now owns EHCI, spin till it hands it over. */ 783 if (try_handoff) { 784 int msec = 1000; 785 while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) { 786 tried_handoff = 1; 787 msleep(10); 788 msec -= 10; 789 pci_read_config_dword(pdev, offset, &cap); 790 } 791 } 792 793 if (cap & EHCI_USBLEGSUP_BIOS) { 794 /* well, possibly buggy BIOS... try to shut it down, 795 * and hope nothing goes too wrong 796 */ 797 if (try_handoff) 798 dev_warn(&pdev->dev, 799 "EHCI: BIOS handoff failed (BIOS bug?) %08x\n", 800 cap); 801 pci_write_config_byte(pdev, offset + 2, 0); 802 } 803 804 /* just in case, always disable EHCI SMIs */ 805 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 0); 806 807 /* If the BIOS ever owned the controller then we can't expect 808 * any power sessions to remain intact. 809 */ 810 if (tried_handoff) 811 writel(0, op_reg_base + EHCI_CONFIGFLAG); 812 } 813 814 static void quirk_usb_disable_ehci(struct pci_dev *pdev) 815 { 816 void __iomem *base, *op_reg_base; 817 u32 hcc_params, cap, val; 818 u8 offset, cap_length; 819 int wait_time, count = 256/4; 820 821 if (!mmio_resource_enabled(pdev, 0)) 822 return; 823 824 base = pci_ioremap_bar(pdev, 0); 825 if (base == NULL) 826 return; 827 828 cap_length = readb(base); 829 op_reg_base = base + cap_length; 830 831 /* EHCI 0.96 and later may have "extended capabilities" 832 * spec section 5.1 explains the bios handoff, e.g. for 833 * booting from USB disk or using a usb keyboard 834 */ 835 hcc_params = readl(base + EHCI_HCC_PARAMS); 836 offset = (hcc_params >> 8) & 0xff; 837 while (offset && --count) { 838 pci_read_config_dword(pdev, offset, &cap); 839 840 switch (cap & 0xff) { 841 case 1: 842 ehci_bios_handoff(pdev, op_reg_base, cap, offset); 843 break; 844 case 0: /* Illegal reserved cap, set cap=0 so we exit */ 845 cap = 0; /* fall through */ 846 default: 847 dev_warn(&pdev->dev, 848 "EHCI: unrecognized capability %02x\n", 849 cap & 0xff); 850 } 851 offset = (cap >> 8) & 0xff; 852 } 853 if (!count) 854 dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n"); 855 856 /* 857 * halt EHCI & disable its interrupts in any case 858 */ 859 val = readl(op_reg_base + EHCI_USBSTS); 860 if ((val & EHCI_USBSTS_HALTED) == 0) { 861 val = readl(op_reg_base + EHCI_USBCMD); 862 val &= ~EHCI_USBCMD_RUN; 863 writel(val, op_reg_base + EHCI_USBCMD); 864 865 wait_time = 2000; 866 do { 867 writel(0x3f, op_reg_base + EHCI_USBSTS); 868 udelay(100); 869 wait_time -= 100; 870 val = readl(op_reg_base + EHCI_USBSTS); 871 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) { 872 break; 873 } 874 } while (wait_time > 0); 875 } 876 writel(0, op_reg_base + EHCI_USBINTR); 877 writel(0x3f, op_reg_base + EHCI_USBSTS); 878 879 iounmap(base); 880 } 881 882 /* 883 * handshake - spin reading a register until handshake completes 884 * @ptr: address of hc register to be read 885 * @mask: bits to look at in result of read 886 * @done: value of those bits when handshake succeeds 887 * @wait_usec: timeout in microseconds 888 * @delay_usec: delay in microseconds to wait between polling 889 * 890 * Polls a register every delay_usec microseconds. 891 * Returns 0 when the mask bits have the value done. 892 * Returns -ETIMEDOUT if this condition is not true after 893 * wait_usec microseconds have passed. 894 */ 895 static int handshake(void __iomem *ptr, u32 mask, u32 done, 896 int wait_usec, int delay_usec) 897 { 898 u32 result; 899 900 do { 901 result = readl(ptr); 902 result &= mask; 903 if (result == done) 904 return 0; 905 udelay(delay_usec); 906 wait_usec -= delay_usec; 907 } while (wait_usec > 0); 908 return -ETIMEDOUT; 909 } 910 911 /* 912 * Intel's Panther Point chipset has two host controllers (EHCI and xHCI) that 913 * share some number of ports. These ports can be switched between either 914 * controller. Not all of the ports under the EHCI host controller may be 915 * switchable. 916 * 917 * The ports should be switched over to xHCI before PCI probes for any device 918 * start. This avoids active devices under EHCI being disconnected during the 919 * port switchover, which could cause loss of data on USB storage devices, or 920 * failed boot when the root file system is on a USB mass storage device and is 921 * enumerated under EHCI first. 922 * 923 * We write into the xHC's PCI configuration space in some Intel-specific 924 * registers to switch the ports over. The USB 3.0 terminations and the USB 925 * 2.0 data wires are switched separately. We want to enable the SuperSpeed 926 * terminations before switching the USB 2.0 wires over, so that USB 3.0 927 * devices connect at SuperSpeed, rather than at USB 2.0 speeds. 928 */ 929 void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev) 930 { 931 u32 ports_available; 932 bool ehci_found = false; 933 struct pci_dev *companion = NULL; 934 935 /* Sony VAIO t-series with subsystem device ID 90a8 is not capable of 936 * switching ports from EHCI to xHCI 937 */ 938 if (xhci_pdev->subsystem_vendor == PCI_VENDOR_ID_SONY && 939 xhci_pdev->subsystem_device == 0x90a8) 940 return; 941 942 /* make sure an intel EHCI controller exists */ 943 for_each_pci_dev(companion) { 944 if (companion->class == PCI_CLASS_SERIAL_USB_EHCI && 945 companion->vendor == PCI_VENDOR_ID_INTEL) { 946 ehci_found = true; 947 break; 948 } 949 } 950 951 if (!ehci_found) 952 return; 953 954 /* Don't switchover the ports if the user hasn't compiled the xHCI 955 * driver. Otherwise they will see "dead" USB ports that don't power 956 * the devices. 957 */ 958 if (!IS_ENABLED(CONFIG_USB_XHCI_HCD)) { 959 dev_warn(&xhci_pdev->dev, 960 "CONFIG_USB_XHCI_HCD is turned off, defaulting to EHCI.\n"); 961 dev_warn(&xhci_pdev->dev, 962 "USB 3.0 devices will work at USB 2.0 speeds.\n"); 963 usb_disable_xhci_ports(xhci_pdev); 964 return; 965 } 966 967 /* Read USB3PRM, the USB 3.0 Port Routing Mask Register 968 * Indicate the ports that can be changed from OS. 969 */ 970 pci_read_config_dword(xhci_pdev, USB_INTEL_USB3PRM, 971 &ports_available); 972 973 dev_dbg(&xhci_pdev->dev, "Configurable ports to enable SuperSpeed: 0x%x\n", 974 ports_available); 975 976 /* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable 977 * Register, to turn on SuperSpeed terminations for the 978 * switchable ports. 979 */ 980 pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, 981 ports_available); 982 983 pci_read_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, 984 &ports_available); 985 dev_dbg(&xhci_pdev->dev, 986 "USB 3.0 ports that are now enabled under xHCI: 0x%x\n", 987 ports_available); 988 989 /* Read XUSB2PRM, xHCI USB 2.0 Port Routing Mask Register 990 * Indicate the USB 2.0 ports to be controlled by the xHCI host. 991 */ 992 993 pci_read_config_dword(xhci_pdev, USB_INTEL_USB2PRM, 994 &ports_available); 995 996 dev_dbg(&xhci_pdev->dev, "Configurable USB 2.0 ports to hand over to xCHI: 0x%x\n", 997 ports_available); 998 999 /* Write XUSB2PR, the xHC USB 2.0 Port Routing Register, to 1000 * switch the USB 2.0 power and data lines over to the xHCI 1001 * host. 1002 */ 1003 pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, 1004 ports_available); 1005 1006 pci_read_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, 1007 &ports_available); 1008 dev_dbg(&xhci_pdev->dev, 1009 "USB 2.0 ports that are now switched over to xHCI: 0x%x\n", 1010 ports_available); 1011 } 1012 EXPORT_SYMBOL_GPL(usb_enable_intel_xhci_ports); 1013 1014 void usb_disable_xhci_ports(struct pci_dev *xhci_pdev) 1015 { 1016 pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, 0x0); 1017 pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, 0x0); 1018 } 1019 EXPORT_SYMBOL_GPL(usb_disable_xhci_ports); 1020 1021 /** 1022 * PCI Quirks for xHCI. 1023 * 1024 * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS. 1025 * It signals to the BIOS that the OS wants control of the host controller, 1026 * and then waits 1 second for the BIOS to hand over control. 1027 * If we timeout, assume the BIOS is broken and take control anyway. 1028 */ 1029 static void quirk_usb_handoff_xhci(struct pci_dev *pdev) 1030 { 1031 void __iomem *base; 1032 int ext_cap_offset; 1033 void __iomem *op_reg_base; 1034 u32 val; 1035 int timeout; 1036 int len = pci_resource_len(pdev, 0); 1037 1038 if (!mmio_resource_enabled(pdev, 0)) 1039 return; 1040 1041 base = ioremap_nocache(pci_resource_start(pdev, 0), len); 1042 if (base == NULL) 1043 return; 1044 1045 /* 1046 * Find the Legacy Support Capability register - 1047 * this is optional for xHCI host controllers. 1048 */ 1049 ext_cap_offset = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_LEGACY); 1050 1051 if (!ext_cap_offset) 1052 goto hc_init; 1053 1054 if ((ext_cap_offset + sizeof(val)) > len) { 1055 /* We're reading garbage from the controller */ 1056 dev_warn(&pdev->dev, "xHCI controller failing to respond"); 1057 goto iounmap; 1058 } 1059 val = readl(base + ext_cap_offset); 1060 1061 /* Auto handoff never worked for these devices. Force it and continue */ 1062 if ((pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) || 1063 (pdev->vendor == PCI_VENDOR_ID_RENESAS 1064 && pdev->device == 0x0014)) { 1065 val = (val | XHCI_HC_OS_OWNED) & ~XHCI_HC_BIOS_OWNED; 1066 writel(val, base + ext_cap_offset); 1067 } 1068 1069 /* If the BIOS owns the HC, signal that the OS wants it, and wait */ 1070 if (val & XHCI_HC_BIOS_OWNED) { 1071 writel(val | XHCI_HC_OS_OWNED, base + ext_cap_offset); 1072 1073 /* Wait for 1 second with 10 microsecond polling interval */ 1074 timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED, 1075 0, 1000000, 10); 1076 1077 /* Assume a buggy BIOS and take HC ownership anyway */ 1078 if (timeout) { 1079 dev_warn(&pdev->dev, 1080 "xHCI BIOS handoff failed (BIOS bug ?) %08x\n", 1081 val); 1082 writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset); 1083 } 1084 } 1085 1086 val = readl(base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET); 1087 /* Mask off (turn off) any enabled SMIs */ 1088 val &= XHCI_LEGACY_DISABLE_SMI; 1089 /* Mask all SMI events bits, RW1C */ 1090 val |= XHCI_LEGACY_SMI_EVENTS; 1091 /* Disable any BIOS SMIs and clear all SMI events*/ 1092 writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET); 1093 1094 hc_init: 1095 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 1096 usb_enable_intel_xhci_ports(pdev); 1097 1098 op_reg_base = base + XHCI_HC_LENGTH(readl(base)); 1099 1100 /* Wait for the host controller to be ready before writing any 1101 * operational or runtime registers. Wait 5 seconds and no more. 1102 */ 1103 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0, 1104 5000000, 10); 1105 /* Assume a buggy HC and start HC initialization anyway */ 1106 if (timeout) { 1107 val = readl(op_reg_base + XHCI_STS_OFFSET); 1108 dev_warn(&pdev->dev, 1109 "xHCI HW not ready after 5 sec (HC bug?) status = 0x%x\n", 1110 val); 1111 } 1112 1113 /* Send the halt and disable interrupts command */ 1114 val = readl(op_reg_base + XHCI_CMD_OFFSET); 1115 val &= ~(XHCI_CMD_RUN | XHCI_IRQS); 1116 writel(val, op_reg_base + XHCI_CMD_OFFSET); 1117 1118 /* Wait for the HC to halt - poll every 125 usec (one microframe). */ 1119 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1, 1120 XHCI_MAX_HALT_USEC, 125); 1121 if (timeout) { 1122 val = readl(op_reg_base + XHCI_STS_OFFSET); 1123 dev_warn(&pdev->dev, 1124 "xHCI HW did not halt within %d usec status = 0x%x\n", 1125 XHCI_MAX_HALT_USEC, val); 1126 } 1127 1128 iounmap: 1129 iounmap(base); 1130 } 1131 1132 static void quirk_usb_early_handoff(struct pci_dev *pdev) 1133 { 1134 /* Skip Netlogic mips SoC's internal PCI USB controller. 1135 * This device does not need/support EHCI/OHCI handoff 1136 */ 1137 if (pdev->vendor == 0x184e) /* vendor Netlogic */ 1138 return; 1139 if (pdev->class != PCI_CLASS_SERIAL_USB_UHCI && 1140 pdev->class != PCI_CLASS_SERIAL_USB_OHCI && 1141 pdev->class != PCI_CLASS_SERIAL_USB_EHCI && 1142 pdev->class != PCI_CLASS_SERIAL_USB_XHCI) 1143 return; 1144 1145 if (pci_enable_device(pdev) < 0) { 1146 dev_warn(&pdev->dev, 1147 "Can't enable PCI device, BIOS handoff failed.\n"); 1148 return; 1149 } 1150 if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI) 1151 quirk_usb_handoff_uhci(pdev); 1152 else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI) 1153 quirk_usb_handoff_ohci(pdev); 1154 else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI) 1155 quirk_usb_disable_ehci(pdev); 1156 else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI) 1157 quirk_usb_handoff_xhci(pdev); 1158 pci_disable_device(pdev); 1159 } 1160 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1161 PCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff); 1162 1163 bool usb_xhci_needs_pci_reset(struct pci_dev *pdev) 1164 { 1165 /* 1166 * Our dear uPD72020{1,2} friend only partially resets when 1167 * asked to via the XHCI interface, and may end up doing DMA 1168 * at the wrong addresses, as it keeps the top 32bit of some 1169 * addresses from its previous programming under obscure 1170 * circumstances. 1171 * Give it a good wack at probe time. Unfortunately, this 1172 * needs to happen before we've had a chance to discover any 1173 * quirk, or the system will be in a rather bad state. 1174 */ 1175 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 1176 (pdev->device == 0x0014 || pdev->device == 0x0015)) 1177 return true; 1178 1179 return false; 1180 } 1181 EXPORT_SYMBOL_GPL(usb_xhci_needs_pci_reset); 1182