1 /* 2 * This file contains code to reset and initialize USB host controllers. 3 * Some of it includes work-arounds for PCI hardware and BIOS quirks. 4 * It may need to run early during booting -- before USB would normally 5 * initialize -- to ensure that Linux doesn't use any legacy modes. 6 * 7 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 8 * (and others) 9 */ 10 11 #include <linux/types.h> 12 #include <linux/kernel.h> 13 #include <linux/pci.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/acpi.h> 17 #include <linux/dmi.h> 18 #include "pci-quirks.h" 19 #include "xhci-ext-caps.h" 20 21 22 #define UHCI_USBLEGSUP 0xc0 /* legacy support */ 23 #define UHCI_USBCMD 0 /* command register */ 24 #define UHCI_USBINTR 4 /* interrupt register */ 25 #define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */ 26 #define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */ 27 #define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */ 28 #define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */ 29 #define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */ 30 #define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */ 31 #define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */ 32 33 #define OHCI_CONTROL 0x04 34 #define OHCI_CMDSTATUS 0x08 35 #define OHCI_INTRSTATUS 0x0c 36 #define OHCI_INTRENABLE 0x10 37 #define OHCI_INTRDISABLE 0x14 38 #define OHCI_OCR (1 << 3) /* ownership change request */ 39 #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ 40 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ 41 #define OHCI_INTR_OC (1 << 30) /* ownership change */ 42 43 #define EHCI_HCC_PARAMS 0x08 /* extended capabilities */ 44 #define EHCI_USBCMD 0 /* command register */ 45 #define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */ 46 #define EHCI_USBSTS 4 /* status register */ 47 #define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */ 48 #define EHCI_USBINTR 8 /* interrupt register */ 49 #define EHCI_CONFIGFLAG 0x40 /* configured flag register */ 50 #define EHCI_USBLEGSUP 0 /* legacy support register */ 51 #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */ 52 #define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */ 53 #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */ 54 #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */ 55 56 /* AMD quirk use */ 57 #define AB_REG_BAR_LOW 0xe0 58 #define AB_REG_BAR_HIGH 0xe1 59 #define AB_REG_BAR_SB700 0xf0 60 #define AB_INDX(addr) ((addr) + 0x00) 61 #define AB_DATA(addr) ((addr) + 0x04) 62 #define AX_INDXC 0x30 63 #define AX_DATAC 0x34 64 65 #define NB_PCIE_INDX_ADDR 0xe0 66 #define NB_PCIE_INDX_DATA 0xe4 67 #define PCIE_P_CNTL 0x10040 68 #define BIF_NB 0x10002 69 #define NB_PIF0_PWRDOWN_0 0x01100012 70 #define NB_PIF0_PWRDOWN_1 0x01100013 71 72 static struct amd_chipset_info { 73 struct pci_dev *nb_dev; 74 struct pci_dev *smbus_dev; 75 int nb_type; 76 int sb_type; 77 int isoc_reqs; 78 int probe_count; 79 int probe_result; 80 } amd_chipset; 81 82 static DEFINE_SPINLOCK(amd_lock); 83 84 int usb_amd_find_chipset_info(void) 85 { 86 u8 rev = 0; 87 unsigned long flags; 88 struct amd_chipset_info info; 89 int ret; 90 91 spin_lock_irqsave(&amd_lock, flags); 92 93 /* probe only once */ 94 if (amd_chipset.probe_count > 0) { 95 amd_chipset.probe_count++; 96 spin_unlock_irqrestore(&amd_lock, flags); 97 return amd_chipset.probe_result; 98 } 99 memset(&info, 0, sizeof(info)); 100 spin_unlock_irqrestore(&amd_lock, flags); 101 102 info.smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 0x4385, NULL); 103 if (info.smbus_dev) { 104 rev = info.smbus_dev->revision; 105 if (rev >= 0x40) 106 info.sb_type = 1; 107 else if (rev >= 0x30 && rev <= 0x3b) 108 info.sb_type = 3; 109 } else { 110 info.smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 111 0x780b, NULL); 112 if (!info.smbus_dev) { 113 ret = 0; 114 goto commit; 115 } 116 117 rev = info.smbus_dev->revision; 118 if (rev >= 0x11 && rev <= 0x18) 119 info.sb_type = 2; 120 } 121 122 if (info.sb_type == 0) { 123 if (info.smbus_dev) { 124 pci_dev_put(info.smbus_dev); 125 info.smbus_dev = NULL; 126 } 127 ret = 0; 128 goto commit; 129 } 130 131 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL); 132 if (info.nb_dev) { 133 info.nb_type = 1; 134 } else { 135 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL); 136 if (info.nb_dev) { 137 info.nb_type = 2; 138 } else { 139 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 140 0x9600, NULL); 141 if (info.nb_dev) 142 info.nb_type = 3; 143 } 144 } 145 146 ret = info.probe_result = 1; 147 printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n"); 148 149 commit: 150 151 spin_lock_irqsave(&amd_lock, flags); 152 if (amd_chipset.probe_count > 0) { 153 /* race - someone else was faster - drop devices */ 154 155 /* Mark that we where here */ 156 amd_chipset.probe_count++; 157 ret = amd_chipset.probe_result; 158 159 spin_unlock_irqrestore(&amd_lock, flags); 160 161 if (info.nb_dev) 162 pci_dev_put(info.nb_dev); 163 if (info.smbus_dev) 164 pci_dev_put(info.smbus_dev); 165 166 } else { 167 /* no race - commit the result */ 168 info.probe_count++; 169 amd_chipset = info; 170 spin_unlock_irqrestore(&amd_lock, flags); 171 } 172 173 return ret; 174 } 175 EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info); 176 177 /* 178 * The hardware normally enables the A-link power management feature, which 179 * lets the system lower the power consumption in idle states. 180 * 181 * This USB quirk prevents the link going into that lower power state 182 * during isochronous transfers. 183 * 184 * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of 185 * some AMD platforms may stutter or have breaks occasionally. 186 */ 187 static void usb_amd_quirk_pll(int disable) 188 { 189 u32 addr, addr_low, addr_high, val; 190 u32 bit = disable ? 0 : 1; 191 unsigned long flags; 192 193 spin_lock_irqsave(&amd_lock, flags); 194 195 if (disable) { 196 amd_chipset.isoc_reqs++; 197 if (amd_chipset.isoc_reqs > 1) { 198 spin_unlock_irqrestore(&amd_lock, flags); 199 return; 200 } 201 } else { 202 amd_chipset.isoc_reqs--; 203 if (amd_chipset.isoc_reqs > 0) { 204 spin_unlock_irqrestore(&amd_lock, flags); 205 return; 206 } 207 } 208 209 if (amd_chipset.sb_type == 1 || amd_chipset.sb_type == 2) { 210 outb_p(AB_REG_BAR_LOW, 0xcd6); 211 addr_low = inb_p(0xcd7); 212 outb_p(AB_REG_BAR_HIGH, 0xcd6); 213 addr_high = inb_p(0xcd7); 214 addr = addr_high << 8 | addr_low; 215 216 outl_p(0x30, AB_INDX(addr)); 217 outl_p(0x40, AB_DATA(addr)); 218 outl_p(0x34, AB_INDX(addr)); 219 val = inl_p(AB_DATA(addr)); 220 } else if (amd_chipset.sb_type == 3) { 221 pci_read_config_dword(amd_chipset.smbus_dev, 222 AB_REG_BAR_SB700, &addr); 223 outl(AX_INDXC, AB_INDX(addr)); 224 outl(0x40, AB_DATA(addr)); 225 outl(AX_DATAC, AB_INDX(addr)); 226 val = inl(AB_DATA(addr)); 227 } else { 228 spin_unlock_irqrestore(&amd_lock, flags); 229 return; 230 } 231 232 if (disable) { 233 val &= ~0x08; 234 val |= (1 << 4) | (1 << 9); 235 } else { 236 val |= 0x08; 237 val &= ~((1 << 4) | (1 << 9)); 238 } 239 outl_p(val, AB_DATA(addr)); 240 241 if (!amd_chipset.nb_dev) { 242 spin_unlock_irqrestore(&amd_lock, flags); 243 return; 244 } 245 246 if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) { 247 addr = PCIE_P_CNTL; 248 pci_write_config_dword(amd_chipset.nb_dev, 249 NB_PCIE_INDX_ADDR, addr); 250 pci_read_config_dword(amd_chipset.nb_dev, 251 NB_PCIE_INDX_DATA, &val); 252 253 val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12)); 254 val |= bit | (bit << 3) | (bit << 12); 255 val |= ((!bit) << 4) | ((!bit) << 9); 256 pci_write_config_dword(amd_chipset.nb_dev, 257 NB_PCIE_INDX_DATA, val); 258 259 addr = BIF_NB; 260 pci_write_config_dword(amd_chipset.nb_dev, 261 NB_PCIE_INDX_ADDR, addr); 262 pci_read_config_dword(amd_chipset.nb_dev, 263 NB_PCIE_INDX_DATA, &val); 264 val &= ~(1 << 8); 265 val |= bit << 8; 266 267 pci_write_config_dword(amd_chipset.nb_dev, 268 NB_PCIE_INDX_DATA, val); 269 } else if (amd_chipset.nb_type == 2) { 270 addr = NB_PIF0_PWRDOWN_0; 271 pci_write_config_dword(amd_chipset.nb_dev, 272 NB_PCIE_INDX_ADDR, addr); 273 pci_read_config_dword(amd_chipset.nb_dev, 274 NB_PCIE_INDX_DATA, &val); 275 if (disable) 276 val &= ~(0x3f << 7); 277 else 278 val |= 0x3f << 7; 279 280 pci_write_config_dword(amd_chipset.nb_dev, 281 NB_PCIE_INDX_DATA, val); 282 283 addr = NB_PIF0_PWRDOWN_1; 284 pci_write_config_dword(amd_chipset.nb_dev, 285 NB_PCIE_INDX_ADDR, addr); 286 pci_read_config_dword(amd_chipset.nb_dev, 287 NB_PCIE_INDX_DATA, &val); 288 if (disable) 289 val &= ~(0x3f << 7); 290 else 291 val |= 0x3f << 7; 292 293 pci_write_config_dword(amd_chipset.nb_dev, 294 NB_PCIE_INDX_DATA, val); 295 } 296 297 spin_unlock_irqrestore(&amd_lock, flags); 298 return; 299 } 300 301 void usb_amd_quirk_pll_disable(void) 302 { 303 usb_amd_quirk_pll(1); 304 } 305 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable); 306 307 void usb_amd_quirk_pll_enable(void) 308 { 309 usb_amd_quirk_pll(0); 310 } 311 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable); 312 313 void usb_amd_dev_put(void) 314 { 315 struct pci_dev *nb, *smbus; 316 unsigned long flags; 317 318 spin_lock_irqsave(&amd_lock, flags); 319 320 amd_chipset.probe_count--; 321 if (amd_chipset.probe_count > 0) { 322 spin_unlock_irqrestore(&amd_lock, flags); 323 return; 324 } 325 326 /* save them to pci_dev_put outside of spinlock */ 327 nb = amd_chipset.nb_dev; 328 smbus = amd_chipset.smbus_dev; 329 330 amd_chipset.nb_dev = NULL; 331 amd_chipset.smbus_dev = NULL; 332 amd_chipset.nb_type = 0; 333 amd_chipset.sb_type = 0; 334 amd_chipset.isoc_reqs = 0; 335 amd_chipset.probe_result = 0; 336 337 spin_unlock_irqrestore(&amd_lock, flags); 338 339 if (nb) 340 pci_dev_put(nb); 341 if (smbus) 342 pci_dev_put(smbus); 343 } 344 EXPORT_SYMBOL_GPL(usb_amd_dev_put); 345 346 /* 347 * Make sure the controller is completely inactive, unable to 348 * generate interrupts or do DMA. 349 */ 350 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base) 351 { 352 /* Turn off PIRQ enable and SMI enable. (This also turns off the 353 * BIOS's USB Legacy Support.) Turn off all the R/WC bits too. 354 */ 355 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC); 356 357 /* Reset the HC - this will force us to get a 358 * new notification of any already connected 359 * ports due to the virtual disconnect that it 360 * implies. 361 */ 362 outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD); 363 mb(); 364 udelay(5); 365 if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET) 366 dev_warn(&pdev->dev, "HCRESET not completed yet!\n"); 367 368 /* Just to be safe, disable interrupt requests and 369 * make sure the controller is stopped. 370 */ 371 outw(0, base + UHCI_USBINTR); 372 outw(0, base + UHCI_USBCMD); 373 } 374 EXPORT_SYMBOL_GPL(uhci_reset_hc); 375 376 /* 377 * Initialize a controller that was newly discovered or has just been 378 * resumed. In either case we can't be sure of its previous state. 379 * 380 * Returns: 1 if the controller was reset, 0 otherwise. 381 */ 382 int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base) 383 { 384 u16 legsup; 385 unsigned int cmd, intr; 386 387 /* 388 * When restarting a suspended controller, we expect all the 389 * settings to be the same as we left them: 390 * 391 * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP; 392 * Controller is stopped and configured with EGSM set; 393 * No interrupts enabled except possibly Resume Detect. 394 * 395 * If any of these conditions are violated we do a complete reset. 396 */ 397 pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup); 398 if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) { 399 dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n", 400 __func__, legsup); 401 goto reset_needed; 402 } 403 404 cmd = inw(base + UHCI_USBCMD); 405 if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) || 406 !(cmd & UHCI_USBCMD_EGSM)) { 407 dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n", 408 __func__, cmd); 409 goto reset_needed; 410 } 411 412 intr = inw(base + UHCI_USBINTR); 413 if (intr & (~UHCI_USBINTR_RESUME)) { 414 dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n", 415 __func__, intr); 416 goto reset_needed; 417 } 418 return 0; 419 420 reset_needed: 421 dev_dbg(&pdev->dev, "Performing full reset\n"); 422 uhci_reset_hc(pdev, base); 423 return 1; 424 } 425 EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc); 426 427 static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask) 428 { 429 u16 cmd; 430 return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask); 431 } 432 433 #define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO) 434 #define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY) 435 436 static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev) 437 { 438 unsigned long base = 0; 439 int i; 440 441 if (!pio_enabled(pdev)) 442 return; 443 444 for (i = 0; i < PCI_ROM_RESOURCE; i++) 445 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) { 446 base = pci_resource_start(pdev, i); 447 break; 448 } 449 450 if (base) 451 uhci_check_and_reset_hc(pdev, base); 452 } 453 454 static int __devinit mmio_resource_enabled(struct pci_dev *pdev, int idx) 455 { 456 return pci_resource_start(pdev, idx) && mmio_enabled(pdev); 457 } 458 459 static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev) 460 { 461 void __iomem *base; 462 u32 control; 463 464 if (!mmio_resource_enabled(pdev, 0)) 465 return; 466 467 base = pci_ioremap_bar(pdev, 0); 468 if (base == NULL) 469 return; 470 471 control = readl(base + OHCI_CONTROL); 472 473 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ 474 #ifdef __hppa__ 475 #define OHCI_CTRL_MASK (OHCI_CTRL_RWC | OHCI_CTRL_IR) 476 #else 477 #define OHCI_CTRL_MASK OHCI_CTRL_RWC 478 479 if (control & OHCI_CTRL_IR) { 480 int wait_time = 500; /* arbitrary; 5 seconds */ 481 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE); 482 writel(OHCI_OCR, base + OHCI_CMDSTATUS); 483 while (wait_time > 0 && 484 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) { 485 wait_time -= 10; 486 msleep(10); 487 } 488 if (wait_time <= 0) 489 dev_warn(&pdev->dev, "OHCI: BIOS handoff failed" 490 " (BIOS bug?) %08x\n", 491 readl(base + OHCI_CONTROL)); 492 } 493 #endif 494 495 /* reset controller, preserving RWC (and possibly IR) */ 496 writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL); 497 498 /* 499 * disable interrupts 500 */ 501 writel(~(u32)0, base + OHCI_INTRDISABLE); 502 writel(~(u32)0, base + OHCI_INTRSTATUS); 503 504 iounmap(base); 505 } 506 507 static void __devinit ehci_bios_handoff(struct pci_dev *pdev, 508 void __iomem *op_reg_base, 509 u32 cap, u8 offset) 510 { 511 int try_handoff = 1, tried_handoff = 0; 512 513 /* The Pegatron Lucid (ExoPC) tablet sporadically waits for 90 514 * seconds trying the handoff on its unused controller. Skip 515 * it. */ 516 if (pdev->vendor == 0x8086 && pdev->device == 0x283a) { 517 const char *dmi_bn = dmi_get_system_info(DMI_BOARD_NAME); 518 const char *dmi_bv = dmi_get_system_info(DMI_BIOS_VERSION); 519 if (dmi_bn && !strcmp(dmi_bn, "EXOPG06411") && 520 dmi_bv && !strcmp(dmi_bv, "Lucid-CE-133")) 521 try_handoff = 0; 522 } 523 524 if (try_handoff && (cap & EHCI_USBLEGSUP_BIOS)) { 525 dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n"); 526 527 #if 0 528 /* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on, 529 * but that seems dubious in general (the BIOS left it off intentionally) 530 * and is known to prevent some systems from booting. so we won't do this 531 * unless maybe we can determine when we're on a system that needs SMI forced. 532 */ 533 /* BIOS workaround (?): be sure the pre-Linux code 534 * receives the SMI 535 */ 536 pci_read_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, &val); 537 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 538 val | EHCI_USBLEGCTLSTS_SOOE); 539 #endif 540 541 /* some systems get upset if this semaphore is 542 * set for any other reason than forcing a BIOS 543 * handoff.. 544 */ 545 pci_write_config_byte(pdev, offset + 3, 1); 546 } 547 548 /* if boot firmware now owns EHCI, spin till it hands it over. */ 549 if (try_handoff) { 550 int msec = 1000; 551 while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) { 552 tried_handoff = 1; 553 msleep(10); 554 msec -= 10; 555 pci_read_config_dword(pdev, offset, &cap); 556 } 557 } 558 559 if (cap & EHCI_USBLEGSUP_BIOS) { 560 /* well, possibly buggy BIOS... try to shut it down, 561 * and hope nothing goes too wrong 562 */ 563 if (try_handoff) 564 dev_warn(&pdev->dev, "EHCI: BIOS handoff failed" 565 " (BIOS bug?) %08x\n", cap); 566 pci_write_config_byte(pdev, offset + 2, 0); 567 } 568 569 /* just in case, always disable EHCI SMIs */ 570 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 0); 571 572 /* If the BIOS ever owned the controller then we can't expect 573 * any power sessions to remain intact. 574 */ 575 if (tried_handoff) 576 writel(0, op_reg_base + EHCI_CONFIGFLAG); 577 } 578 579 static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev) 580 { 581 void __iomem *base, *op_reg_base; 582 u32 hcc_params, cap, val; 583 u8 offset, cap_length; 584 int wait_time, delta, count = 256/4; 585 586 if (!mmio_resource_enabled(pdev, 0)) 587 return; 588 589 base = pci_ioremap_bar(pdev, 0); 590 if (base == NULL) 591 return; 592 593 cap_length = readb(base); 594 op_reg_base = base + cap_length; 595 596 /* EHCI 0.96 and later may have "extended capabilities" 597 * spec section 5.1 explains the bios handoff, e.g. for 598 * booting from USB disk or using a usb keyboard 599 */ 600 hcc_params = readl(base + EHCI_HCC_PARAMS); 601 offset = (hcc_params >> 8) & 0xff; 602 while (offset && --count) { 603 pci_read_config_dword(pdev, offset, &cap); 604 605 switch (cap & 0xff) { 606 case 1: 607 ehci_bios_handoff(pdev, op_reg_base, cap, offset); 608 break; 609 case 0: /* Illegal reserved cap, set cap=0 so we exit */ 610 cap = 0; /* then fallthrough... */ 611 default: 612 dev_warn(&pdev->dev, "EHCI: unrecognized capability " 613 "%02x\n", cap & 0xff); 614 } 615 offset = (cap >> 8) & 0xff; 616 } 617 if (!count) 618 dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n"); 619 620 /* 621 * halt EHCI & disable its interrupts in any case 622 */ 623 val = readl(op_reg_base + EHCI_USBSTS); 624 if ((val & EHCI_USBSTS_HALTED) == 0) { 625 val = readl(op_reg_base + EHCI_USBCMD); 626 val &= ~EHCI_USBCMD_RUN; 627 writel(val, op_reg_base + EHCI_USBCMD); 628 629 wait_time = 2000; 630 delta = 100; 631 do { 632 writel(0x3f, op_reg_base + EHCI_USBSTS); 633 udelay(delta); 634 wait_time -= delta; 635 val = readl(op_reg_base + EHCI_USBSTS); 636 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) { 637 break; 638 } 639 } while (wait_time > 0); 640 } 641 writel(0, op_reg_base + EHCI_USBINTR); 642 writel(0x3f, op_reg_base + EHCI_USBSTS); 643 644 iounmap(base); 645 } 646 647 /* 648 * handshake - spin reading a register until handshake completes 649 * @ptr: address of hc register to be read 650 * @mask: bits to look at in result of read 651 * @done: value of those bits when handshake succeeds 652 * @wait_usec: timeout in microseconds 653 * @delay_usec: delay in microseconds to wait between polling 654 * 655 * Polls a register every delay_usec microseconds. 656 * Returns 0 when the mask bits have the value done. 657 * Returns -ETIMEDOUT if this condition is not true after 658 * wait_usec microseconds have passed. 659 */ 660 static int handshake(void __iomem *ptr, u32 mask, u32 done, 661 int wait_usec, int delay_usec) 662 { 663 u32 result; 664 665 do { 666 result = readl(ptr); 667 result &= mask; 668 if (result == done) 669 return 0; 670 udelay(delay_usec); 671 wait_usec -= delay_usec; 672 } while (wait_usec > 0); 673 return -ETIMEDOUT; 674 } 675 676 /** 677 * PCI Quirks for xHCI. 678 * 679 * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS. 680 * It signals to the BIOS that the OS wants control of the host controller, 681 * and then waits 5 seconds for the BIOS to hand over control. 682 * If we timeout, assume the BIOS is broken and take control anyway. 683 */ 684 static void __devinit quirk_usb_handoff_xhci(struct pci_dev *pdev) 685 { 686 void __iomem *base; 687 int ext_cap_offset; 688 void __iomem *op_reg_base; 689 u32 val; 690 int timeout; 691 692 if (!mmio_resource_enabled(pdev, 0)) 693 return; 694 695 base = ioremap_nocache(pci_resource_start(pdev, 0), 696 pci_resource_len(pdev, 0)); 697 if (base == NULL) 698 return; 699 700 /* 701 * Find the Legacy Support Capability register - 702 * this is optional for xHCI host controllers. 703 */ 704 ext_cap_offset = xhci_find_next_cap_offset(base, XHCI_HCC_PARAMS_OFFSET); 705 do { 706 if (!ext_cap_offset) 707 /* We've reached the end of the extended capabilities */ 708 goto hc_init; 709 val = readl(base + ext_cap_offset); 710 if (XHCI_EXT_CAPS_ID(val) == XHCI_EXT_CAPS_LEGACY) 711 break; 712 ext_cap_offset = xhci_find_next_cap_offset(base, ext_cap_offset); 713 } while (1); 714 715 /* If the BIOS owns the HC, signal that the OS wants it, and wait */ 716 if (val & XHCI_HC_BIOS_OWNED) { 717 writel(val & XHCI_HC_OS_OWNED, base + ext_cap_offset); 718 719 /* Wait for 5 seconds with 10 microsecond polling interval */ 720 timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED, 721 0, 5000, 10); 722 723 /* Assume a buggy BIOS and take HC ownership anyway */ 724 if (timeout) { 725 dev_warn(&pdev->dev, "xHCI BIOS handoff failed" 726 " (BIOS bug ?) %08x\n", val); 727 writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset); 728 } 729 } 730 731 /* Disable any BIOS SMIs */ 732 writel(XHCI_LEGACY_DISABLE_SMI, 733 base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET); 734 735 hc_init: 736 op_reg_base = base + XHCI_HC_LENGTH(readl(base)); 737 738 /* Wait for the host controller to be ready before writing any 739 * operational or runtime registers. Wait 5 seconds and no more. 740 */ 741 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0, 742 5000, 10); 743 /* Assume a buggy HC and start HC initialization anyway */ 744 if (timeout) { 745 val = readl(op_reg_base + XHCI_STS_OFFSET); 746 dev_warn(&pdev->dev, 747 "xHCI HW not ready after 5 sec (HC bug?) " 748 "status = 0x%x\n", val); 749 } 750 751 /* Send the halt and disable interrupts command */ 752 val = readl(op_reg_base + XHCI_CMD_OFFSET); 753 val &= ~(XHCI_CMD_RUN | XHCI_IRQS); 754 writel(val, op_reg_base + XHCI_CMD_OFFSET); 755 756 /* Wait for the HC to halt - poll every 125 usec (one microframe). */ 757 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1, 758 XHCI_MAX_HALT_USEC, 125); 759 if (timeout) { 760 val = readl(op_reg_base + XHCI_STS_OFFSET); 761 dev_warn(&pdev->dev, 762 "xHCI HW did not halt within %d usec " 763 "status = 0x%x\n", XHCI_MAX_HALT_USEC, val); 764 } 765 766 iounmap(base); 767 } 768 769 static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev) 770 { 771 if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI) 772 quirk_usb_handoff_uhci(pdev); 773 else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI) 774 quirk_usb_handoff_ohci(pdev); 775 else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI) 776 quirk_usb_disable_ehci(pdev); 777 else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI) 778 quirk_usb_handoff_xhci(pdev); 779 } 780 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff); 781