1 /* 2 * OHCI HCD (Host Controller Driver) for USB. 3 * 4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net> 6 * (C) Copyright 2002 Hewlett-Packard Company 7 * 8 * Bus Glue for pxa27x 9 * 10 * Written by Christopher Hoover <ch@hpl.hp.com> 11 * Based on fragments of previous driver by Russell King et al. 12 * 13 * Modified for LH7A404 from ohci-sa1111.c 14 * by Durgesh Pattamatta <pattamattad@sharpsec.com> 15 * 16 * Modified for pxa27x from ohci-lh7a404.c 17 * by Nick Bane <nick@cecomputing.co.uk> 26-8-2004 18 * 19 * This file is licenced under the GPL. 20 */ 21 22 #include <linux/clk.h> 23 #include <linux/device.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/io.h> 26 #include <linux/kernel.h> 27 #include <linux/module.h> 28 #include <linux/of_platform.h> 29 #include <linux/of_gpio.h> 30 #include <linux/platform_data/usb-ohci-pxa27x.h> 31 #include <linux/platform_data/usb-pxa3xx-ulpi.h> 32 #include <linux/platform_device.h> 33 #include <linux/regulator/consumer.h> 34 #include <linux/signal.h> 35 #include <linux/usb.h> 36 #include <linux/usb/hcd.h> 37 #include <linux/usb/otg.h> 38 39 #include <mach/hardware.h> 40 41 #include "ohci.h" 42 43 #define DRIVER_DESC "OHCI PXA27x/PXA3x driver" 44 45 /* 46 * UHC: USB Host Controller (OHCI-like) register definitions 47 */ 48 #define UHCREV (0x0000) /* UHC HCI Spec Revision */ 49 #define UHCHCON (0x0004) /* UHC Host Control Register */ 50 #define UHCCOMS (0x0008) /* UHC Command Status Register */ 51 #define UHCINTS (0x000C) /* UHC Interrupt Status Register */ 52 #define UHCINTE (0x0010) /* UHC Interrupt Enable */ 53 #define UHCINTD (0x0014) /* UHC Interrupt Disable */ 54 #define UHCHCCA (0x0018) /* UHC Host Controller Comm. Area */ 55 #define UHCPCED (0x001C) /* UHC Period Current Endpt Descr */ 56 #define UHCCHED (0x0020) /* UHC Control Head Endpt Descr */ 57 #define UHCCCED (0x0024) /* UHC Control Current Endpt Descr */ 58 #define UHCBHED (0x0028) /* UHC Bulk Head Endpt Descr */ 59 #define UHCBCED (0x002C) /* UHC Bulk Current Endpt Descr */ 60 #define UHCDHEAD (0x0030) /* UHC Done Head */ 61 #define UHCFMI (0x0034) /* UHC Frame Interval */ 62 #define UHCFMR (0x0038) /* UHC Frame Remaining */ 63 #define UHCFMN (0x003C) /* UHC Frame Number */ 64 #define UHCPERS (0x0040) /* UHC Periodic Start */ 65 #define UHCLS (0x0044) /* UHC Low Speed Threshold */ 66 67 #define UHCRHDA (0x0048) /* UHC Root Hub Descriptor A */ 68 #define UHCRHDA_NOCP (1 << 12) /* No over current protection */ 69 #define UHCRHDA_OCPM (1 << 11) /* Over Current Protection Mode */ 70 #define UHCRHDA_POTPGT(x) \ 71 (((x) & 0xff) << 24) /* Power On To Power Good Time */ 72 73 #define UHCRHDB (0x004C) /* UHC Root Hub Descriptor B */ 74 #define UHCRHS (0x0050) /* UHC Root Hub Status */ 75 #define UHCRHPS1 (0x0054) /* UHC Root Hub Port 1 Status */ 76 #define UHCRHPS2 (0x0058) /* UHC Root Hub Port 2 Status */ 77 #define UHCRHPS3 (0x005C) /* UHC Root Hub Port 3 Status */ 78 79 #define UHCSTAT (0x0060) /* UHC Status Register */ 80 #define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */ 81 #define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/ 82 #define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/ 83 #define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */ 84 #define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */ 85 #define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */ 86 #define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */ 87 #define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */ 88 #define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */ 89 90 #define UHCHR (0x0064) /* UHC Reset Register */ 91 #define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */ 92 #define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */ 93 #define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */ 94 #define UHCHR_PCPL (1 << 7) /* Power control polarity low */ 95 #define UHCHR_PSPL (1 << 6) /* Power sense polarity low */ 96 #define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */ 97 #define UHCHR_UIT (1 << 4) /* USB Interrupt Test */ 98 #define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */ 99 #define UHCHR_CGR (1 << 2) /* Clock Generation Reset */ 100 #define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */ 101 #define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */ 102 103 #define UHCHIE (0x0068) /* UHC Interrupt Enable Register*/ 104 #define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */ 105 #define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */ 106 #define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */ 107 #define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */ 108 #define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort 109 Interrupt Enable*/ 110 #define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */ 111 #define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */ 112 113 #define UHCHIT (0x006C) /* UHC Interrupt Test register */ 114 115 #define PXA_UHC_MAX_PORTNUM 3 116 117 static const char hcd_name[] = "ohci-pxa27x"; 118 119 static struct hc_driver __read_mostly ohci_pxa27x_hc_driver; 120 121 struct pxa27x_ohci { 122 struct clk *clk; 123 void __iomem *mmio_base; 124 struct regulator *vbus[3]; 125 bool vbus_enabled[3]; 126 }; 127 128 #define to_pxa27x_ohci(hcd) (struct pxa27x_ohci *)(hcd_to_ohci(hcd)->priv) 129 130 /* 131 PMM_NPS_MODE -- PMM Non-power switching mode 132 Ports are powered continuously. 133 134 PMM_GLOBAL_MODE -- PMM global switching mode 135 All ports are powered at the same time. 136 137 PMM_PERPORT_MODE -- PMM per port switching mode 138 Ports are powered individually. 139 */ 140 static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *pxa_ohci, int mode) 141 { 142 uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA); 143 uint32_t uhcrhdb = __raw_readl(pxa_ohci->mmio_base + UHCRHDB); 144 145 switch (mode) { 146 case PMM_NPS_MODE: 147 uhcrhda |= RH_A_NPS; 148 break; 149 case PMM_GLOBAL_MODE: 150 uhcrhda &= ~(RH_A_NPS & RH_A_PSM); 151 break; 152 case PMM_PERPORT_MODE: 153 uhcrhda &= ~(RH_A_NPS); 154 uhcrhda |= RH_A_PSM; 155 156 /* Set port power control mask bits, only 3 ports. */ 157 uhcrhdb |= (0x7<<17); 158 break; 159 default: 160 printk( KERN_ERR 161 "Invalid mode %d, set to non-power switch mode.\n", 162 mode ); 163 164 uhcrhda |= RH_A_NPS; 165 } 166 167 __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA); 168 __raw_writel(uhcrhdb, pxa_ohci->mmio_base + UHCRHDB); 169 return 0; 170 } 171 172 static int pxa27x_ohci_set_vbus_power(struct pxa27x_ohci *pxa_ohci, 173 unsigned int port, bool enable) 174 { 175 struct regulator *vbus = pxa_ohci->vbus[port]; 176 int ret = 0; 177 178 if (IS_ERR_OR_NULL(vbus)) 179 return 0; 180 181 if (enable && !pxa_ohci->vbus_enabled[port]) 182 ret = regulator_enable(vbus); 183 else if (!enable && pxa_ohci->vbus_enabled[port]) 184 ret = regulator_disable(vbus); 185 186 if (ret < 0) 187 return ret; 188 189 pxa_ohci->vbus_enabled[port] = enable; 190 191 return 0; 192 } 193 194 static int pxa27x_ohci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 195 u16 wIndex, char *buf, u16 wLength) 196 { 197 struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd); 198 int ret; 199 200 switch (typeReq) { 201 case SetPortFeature: 202 case ClearPortFeature: 203 if (!wIndex || wIndex > 3) 204 return -EPIPE; 205 206 if (wValue != USB_PORT_FEAT_POWER) 207 break; 208 209 ret = pxa27x_ohci_set_vbus_power(pxa_ohci, wIndex - 1, 210 typeReq == SetPortFeature); 211 if (ret) 212 return ret; 213 break; 214 } 215 216 return ohci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength); 217 } 218 /*-------------------------------------------------------------------------*/ 219 220 static inline void pxa27x_setup_hc(struct pxa27x_ohci *pxa_ohci, 221 struct pxaohci_platform_data *inf) 222 { 223 uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR); 224 uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA); 225 226 if (inf->flags & ENABLE_PORT1) 227 uhchr &= ~UHCHR_SSEP1; 228 229 if (inf->flags & ENABLE_PORT2) 230 uhchr &= ~UHCHR_SSEP2; 231 232 if (inf->flags & ENABLE_PORT3) 233 uhchr &= ~UHCHR_SSEP3; 234 235 if (inf->flags & POWER_CONTROL_LOW) 236 uhchr |= UHCHR_PCPL; 237 238 if (inf->flags & POWER_SENSE_LOW) 239 uhchr |= UHCHR_PSPL; 240 241 if (inf->flags & NO_OC_PROTECTION) 242 uhcrhda |= UHCRHDA_NOCP; 243 else 244 uhcrhda &= ~UHCRHDA_NOCP; 245 246 if (inf->flags & OC_MODE_PERPORT) 247 uhcrhda |= UHCRHDA_OCPM; 248 else 249 uhcrhda &= ~UHCRHDA_OCPM; 250 251 if (inf->power_on_delay) { 252 uhcrhda &= ~UHCRHDA_POTPGT(0xff); 253 uhcrhda |= UHCRHDA_POTPGT(inf->power_on_delay / 2); 254 } 255 256 __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR); 257 __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA); 258 } 259 260 static inline void pxa27x_reset_hc(struct pxa27x_ohci *pxa_ohci) 261 { 262 uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR); 263 264 __raw_writel(uhchr | UHCHR_FHR, pxa_ohci->mmio_base + UHCHR); 265 udelay(11); 266 __raw_writel(uhchr & ~UHCHR_FHR, pxa_ohci->mmio_base + UHCHR); 267 } 268 269 #ifdef CONFIG_PXA27x 270 extern void pxa27x_clear_otgph(void); 271 #else 272 #define pxa27x_clear_otgph() do {} while (0) 273 #endif 274 275 static int pxa27x_start_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev) 276 { 277 int retval; 278 struct pxaohci_platform_data *inf; 279 uint32_t uhchr; 280 struct usb_hcd *hcd = dev_get_drvdata(dev); 281 282 inf = dev_get_platdata(dev); 283 284 retval = clk_prepare_enable(pxa_ohci->clk); 285 if (retval) 286 return retval; 287 288 pxa27x_reset_hc(pxa_ohci); 289 290 uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) | UHCHR_FSBIR; 291 __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR); 292 293 while (__raw_readl(pxa_ohci->mmio_base + UHCHR) & UHCHR_FSBIR) 294 cpu_relax(); 295 296 pxa27x_setup_hc(pxa_ohci, inf); 297 298 if (inf->init) 299 retval = inf->init(dev); 300 301 if (retval < 0) { 302 clk_disable_unprepare(pxa_ohci->clk); 303 return retval; 304 } 305 306 if (cpu_is_pxa3xx()) 307 pxa3xx_u2d_start_hc(&hcd->self); 308 309 uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) & ~UHCHR_SSE; 310 __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR); 311 __raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, pxa_ohci->mmio_base + UHCHIE); 312 313 /* Clear any OTG Pin Hold */ 314 pxa27x_clear_otgph(); 315 return 0; 316 } 317 318 static void pxa27x_stop_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev) 319 { 320 struct pxaohci_platform_data *inf; 321 struct usb_hcd *hcd = dev_get_drvdata(dev); 322 uint32_t uhccoms; 323 324 inf = dev_get_platdata(dev); 325 326 if (cpu_is_pxa3xx()) 327 pxa3xx_u2d_stop_hc(&hcd->self); 328 329 if (inf->exit) 330 inf->exit(dev); 331 332 pxa27x_reset_hc(pxa_ohci); 333 334 /* Host Controller Reset */ 335 uhccoms = __raw_readl(pxa_ohci->mmio_base + UHCCOMS) | 0x01; 336 __raw_writel(uhccoms, pxa_ohci->mmio_base + UHCCOMS); 337 udelay(10); 338 339 clk_disable_unprepare(pxa_ohci->clk); 340 } 341 342 #ifdef CONFIG_OF 343 static const struct of_device_id pxa_ohci_dt_ids[] = { 344 { .compatible = "marvell,pxa-ohci" }, 345 { } 346 }; 347 348 MODULE_DEVICE_TABLE(of, pxa_ohci_dt_ids); 349 350 static int ohci_pxa_of_init(struct platform_device *pdev) 351 { 352 struct device_node *np = pdev->dev.of_node; 353 struct pxaohci_platform_data *pdata; 354 u32 tmp; 355 int ret; 356 357 if (!np) 358 return 0; 359 360 /* Right now device-tree probed devices don't get dma_mask set. 361 * Since shared usb code relies on it, set it here for now. 362 * Once we have dma capability bindings this can go away. 363 */ 364 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 365 if (ret) 366 return ret; 367 368 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 369 if (!pdata) 370 return -ENOMEM; 371 372 if (of_property_read_bool(np, "marvell,enable-port1")) 373 pdata->flags |= ENABLE_PORT1; 374 if (of_property_read_bool(np, "marvell,enable-port2")) 375 pdata->flags |= ENABLE_PORT2; 376 if (of_property_read_bool(np, "marvell,enable-port3")) 377 pdata->flags |= ENABLE_PORT3; 378 if (of_property_read_bool(np, "marvell,port-sense-low")) 379 pdata->flags |= POWER_SENSE_LOW; 380 if (of_property_read_bool(np, "marvell,power-control-low")) 381 pdata->flags |= POWER_CONTROL_LOW; 382 if (of_property_read_bool(np, "marvell,no-oc-protection")) 383 pdata->flags |= NO_OC_PROTECTION; 384 if (of_property_read_bool(np, "marvell,oc-mode-perport")) 385 pdata->flags |= OC_MODE_PERPORT; 386 if (!of_property_read_u32(np, "marvell,power-on-delay", &tmp)) 387 pdata->power_on_delay = tmp; 388 if (!of_property_read_u32(np, "marvell,port-mode", &tmp)) 389 pdata->port_mode = tmp; 390 if (!of_property_read_u32(np, "marvell,power-budget", &tmp)) 391 pdata->power_budget = tmp; 392 393 pdev->dev.platform_data = pdata; 394 395 return 0; 396 } 397 #else 398 static int ohci_pxa_of_init(struct platform_device *pdev) 399 { 400 return 0; 401 } 402 #endif 403 404 /*-------------------------------------------------------------------------*/ 405 406 /* configure so an HC device and id are always provided */ 407 /* always called with process context; sleeping is OK */ 408 409 410 /** 411 * ohci_hcd_pxa27x_probe - initialize pxa27x-based HCDs 412 * Context: !in_interrupt() 413 * 414 * Allocates basic resources for this USB host controller, and 415 * then invokes the start() method for the HCD associated with it 416 * through the hotplug entry's driver_data. 417 * 418 */ 419 static int ohci_hcd_pxa27x_probe(struct platform_device *pdev) 420 { 421 int retval, irq; 422 struct usb_hcd *hcd; 423 struct pxaohci_platform_data *inf; 424 struct pxa27x_ohci *pxa_ohci; 425 struct ohci_hcd *ohci; 426 struct resource *r; 427 struct clk *usb_clk; 428 unsigned int i; 429 430 retval = ohci_pxa_of_init(pdev); 431 if (retval) 432 return retval; 433 434 inf = dev_get_platdata(&pdev->dev); 435 436 if (!inf) 437 return -ENODEV; 438 439 irq = platform_get_irq(pdev, 0); 440 if (irq < 0) { 441 pr_err("no resource of IORESOURCE_IRQ"); 442 return irq; 443 } 444 445 usb_clk = devm_clk_get(&pdev->dev, NULL); 446 if (IS_ERR(usb_clk)) 447 return PTR_ERR(usb_clk); 448 449 hcd = usb_create_hcd(&ohci_pxa27x_hc_driver, &pdev->dev, "pxa27x"); 450 if (!hcd) 451 return -ENOMEM; 452 453 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 454 hcd->regs = devm_ioremap_resource(&pdev->dev, r); 455 if (IS_ERR(hcd->regs)) { 456 retval = PTR_ERR(hcd->regs); 457 goto err; 458 } 459 hcd->rsrc_start = r->start; 460 hcd->rsrc_len = resource_size(r); 461 462 /* initialize "struct pxa27x_ohci" */ 463 pxa_ohci = to_pxa27x_ohci(hcd); 464 pxa_ohci->clk = usb_clk; 465 pxa_ohci->mmio_base = (void __iomem *)hcd->regs; 466 467 for (i = 0; i < 3; ++i) { 468 char name[6]; 469 470 if (!(inf->flags & (ENABLE_PORT1 << i))) 471 continue; 472 473 sprintf(name, "vbus%u", i + 1); 474 pxa_ohci->vbus[i] = devm_regulator_get(&pdev->dev, name); 475 } 476 477 retval = pxa27x_start_hc(pxa_ohci, &pdev->dev); 478 if (retval < 0) { 479 pr_debug("pxa27x_start_hc failed"); 480 goto err; 481 } 482 483 /* Select Power Management Mode */ 484 pxa27x_ohci_select_pmm(pxa_ohci, inf->port_mode); 485 486 if (inf->power_budget) 487 hcd->power_budget = inf->power_budget; 488 489 /* The value of NDP in roothub_a is incorrect on this hardware */ 490 ohci = hcd_to_ohci(hcd); 491 ohci->num_ports = 3; 492 493 retval = usb_add_hcd(hcd, irq, 0); 494 if (retval == 0) { 495 device_wakeup_enable(hcd->self.controller); 496 return retval; 497 } 498 499 pxa27x_stop_hc(pxa_ohci, &pdev->dev); 500 err: 501 usb_put_hcd(hcd); 502 return retval; 503 } 504 505 506 /* may be called without controller electrically present */ 507 /* may be called with controller, bus, and devices active */ 508 509 /** 510 * ohci_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs 511 * @dev: USB Host Controller being removed 512 * Context: !in_interrupt() 513 * 514 * Reverses the effect of ohci_hcd_pxa27x_probe(), first invoking 515 * the HCD's stop() method. It is always called from a thread 516 * context, normally "rmmod", "apmd", or something similar. 517 * 518 */ 519 static int ohci_hcd_pxa27x_remove(struct platform_device *pdev) 520 { 521 struct usb_hcd *hcd = platform_get_drvdata(pdev); 522 struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd); 523 unsigned int i; 524 525 usb_remove_hcd(hcd); 526 pxa27x_stop_hc(pxa_ohci, &pdev->dev); 527 528 for (i = 0; i < 3; ++i) 529 pxa27x_ohci_set_vbus_power(pxa_ohci, i, false); 530 531 usb_put_hcd(hcd); 532 return 0; 533 } 534 535 /*-------------------------------------------------------------------------*/ 536 537 #ifdef CONFIG_PM 538 static int ohci_hcd_pxa27x_drv_suspend(struct device *dev) 539 { 540 struct usb_hcd *hcd = dev_get_drvdata(dev); 541 struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd); 542 struct ohci_hcd *ohci = hcd_to_ohci(hcd); 543 bool do_wakeup = device_may_wakeup(dev); 544 int ret; 545 546 547 if (time_before(jiffies, ohci->next_statechange)) 548 msleep(5); 549 ohci->next_statechange = jiffies; 550 551 ret = ohci_suspend(hcd, do_wakeup); 552 if (ret) 553 return ret; 554 555 pxa27x_stop_hc(pxa_ohci, dev); 556 return ret; 557 } 558 559 static int ohci_hcd_pxa27x_drv_resume(struct device *dev) 560 { 561 struct usb_hcd *hcd = dev_get_drvdata(dev); 562 struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd); 563 struct pxaohci_platform_data *inf = dev_get_platdata(dev); 564 struct ohci_hcd *ohci = hcd_to_ohci(hcd); 565 int status; 566 567 if (time_before(jiffies, ohci->next_statechange)) 568 msleep(5); 569 ohci->next_statechange = jiffies; 570 571 status = pxa27x_start_hc(pxa_ohci, dev); 572 if (status < 0) 573 return status; 574 575 /* Select Power Management Mode */ 576 pxa27x_ohci_select_pmm(pxa_ohci, inf->port_mode); 577 578 ohci_resume(hcd, false); 579 return 0; 580 } 581 582 static const struct dev_pm_ops ohci_hcd_pxa27x_pm_ops = { 583 .suspend = ohci_hcd_pxa27x_drv_suspend, 584 .resume = ohci_hcd_pxa27x_drv_resume, 585 }; 586 #endif 587 588 static struct platform_driver ohci_hcd_pxa27x_driver = { 589 .probe = ohci_hcd_pxa27x_probe, 590 .remove = ohci_hcd_pxa27x_remove, 591 .shutdown = usb_hcd_platform_shutdown, 592 .driver = { 593 .name = "pxa27x-ohci", 594 .of_match_table = of_match_ptr(pxa_ohci_dt_ids), 595 #ifdef CONFIG_PM 596 .pm = &ohci_hcd_pxa27x_pm_ops, 597 #endif 598 }, 599 }; 600 601 static const struct ohci_driver_overrides pxa27x_overrides __initconst = { 602 .extra_priv_size = sizeof(struct pxa27x_ohci), 603 }; 604 605 static int __init ohci_pxa27x_init(void) 606 { 607 if (usb_disabled()) 608 return -ENODEV; 609 610 pr_info("%s: " DRIVER_DESC "\n", hcd_name); 611 612 ohci_init_driver(&ohci_pxa27x_hc_driver, &pxa27x_overrides); 613 ohci_pxa27x_hc_driver.hub_control = pxa27x_ohci_hub_control; 614 615 return platform_driver_register(&ohci_hcd_pxa27x_driver); 616 } 617 module_init(ohci_pxa27x_init); 618 619 static void __exit ohci_pxa27x_cleanup(void) 620 { 621 platform_driver_unregister(&ohci_hcd_pxa27x_driver); 622 } 623 module_exit(ohci_pxa27x_cleanup); 624 625 MODULE_DESCRIPTION(DRIVER_DESC); 626 MODULE_LICENSE("GPL"); 627 MODULE_ALIAS("platform:pxa27x-ohci"); 628