xref: /openbmc/linux/drivers/usb/host/ohci-pxa27x.c (revision c4f7ac64)
1 // SPDX-License-Identifier: GPL-1.0+
2 /*
3  * OHCI HCD (Host Controller Driver) for USB.
4  *
5  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
6  * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
7  * (C) Copyright 2002 Hewlett-Packard Company
8  *
9  * Bus Glue for pxa27x
10  *
11  * Written by Christopher Hoover <ch@hpl.hp.com>
12  * Based on fragments of previous driver by Russell King et al.
13  *
14  * Modified for LH7A404 from ohci-sa1111.c
15  *  by Durgesh Pattamatta <pattamattad@sharpsec.com>
16  *
17  * Modified for pxa27x from ohci-lh7a404.c
18  *  by Nick Bane <nick@cecomputing.co.uk> 26-8-2004
19  *
20  * This file is licenced under the GPL.
21  */
22 
23 #include <linux/clk.h>
24 #include <linux/device.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/io.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/of_platform.h>
30 #include <linux/of_gpio.h>
31 #include <linux/platform_data/usb-ohci-pxa27x.h>
32 #include <linux/platform_data/usb-pxa3xx-ulpi.h>
33 #include <linux/platform_device.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/signal.h>
36 #include <linux/usb.h>
37 #include <linux/usb/hcd.h>
38 #include <linux/usb/otg.h>
39 
40 #include <mach/hardware.h>
41 
42 #include "ohci.h"
43 
44 #define DRIVER_DESC "OHCI PXA27x/PXA3x driver"
45 
46 /*
47  * UHC: USB Host Controller (OHCI-like) register definitions
48  */
49 #define UHCREV		(0x0000) /* UHC HCI Spec Revision */
50 #define UHCHCON		(0x0004) /* UHC Host Control Register */
51 #define UHCCOMS		(0x0008) /* UHC Command Status Register */
52 #define UHCINTS		(0x000C) /* UHC Interrupt Status Register */
53 #define UHCINTE		(0x0010) /* UHC Interrupt Enable */
54 #define UHCINTD		(0x0014) /* UHC Interrupt Disable */
55 #define UHCHCCA		(0x0018) /* UHC Host Controller Comm. Area */
56 #define UHCPCED		(0x001C) /* UHC Period Current Endpt Descr */
57 #define UHCCHED		(0x0020) /* UHC Control Head Endpt Descr */
58 #define UHCCCED		(0x0024) /* UHC Control Current Endpt Descr */
59 #define UHCBHED		(0x0028) /* UHC Bulk Head Endpt Descr */
60 #define UHCBCED		(0x002C) /* UHC Bulk Current Endpt Descr */
61 #define UHCDHEAD	(0x0030) /* UHC Done Head */
62 #define UHCFMI		(0x0034) /* UHC Frame Interval */
63 #define UHCFMR		(0x0038) /* UHC Frame Remaining */
64 #define UHCFMN		(0x003C) /* UHC Frame Number */
65 #define UHCPERS		(0x0040) /* UHC Periodic Start */
66 #define UHCLS		(0x0044) /* UHC Low Speed Threshold */
67 
68 #define UHCRHDA		(0x0048) /* UHC Root Hub Descriptor A */
69 #define UHCRHDA_NOCP	(1 << 12)	/* No over current protection */
70 #define UHCRHDA_OCPM	(1 << 11)	/* Over Current Protection Mode */
71 #define UHCRHDA_POTPGT(x) \
72 			(((x) & 0xff) << 24) /* Power On To Power Good Time */
73 
74 #define UHCRHDB		(0x004C) /* UHC Root Hub Descriptor B */
75 #define UHCRHS		(0x0050) /* UHC Root Hub Status */
76 #define UHCRHPS1	(0x0054) /* UHC Root Hub Port 1 Status */
77 #define UHCRHPS2	(0x0058) /* UHC Root Hub Port 2 Status */
78 #define UHCRHPS3	(0x005C) /* UHC Root Hub Port 3 Status */
79 
80 #define UHCSTAT		(0x0060) /* UHC Status Register */
81 #define UHCSTAT_UPS3	(1 << 16)	/* USB Power Sense Port3 */
82 #define UHCSTAT_SBMAI	(1 << 15)	/* System Bus Master Abort Interrupt*/
83 #define UHCSTAT_SBTAI	(1 << 14)	/* System Bus Target Abort Interrupt*/
84 #define UHCSTAT_UPRI	(1 << 13)	/* USB Port Resume Interrupt */
85 #define UHCSTAT_UPS2	(1 << 12)	/* USB Power Sense Port 2 */
86 #define UHCSTAT_UPS1	(1 << 11)	/* USB Power Sense Port 1 */
87 #define UHCSTAT_HTA	(1 << 10)	/* HCI Target Abort */
88 #define UHCSTAT_HBA	(1 << 8)	/* HCI Buffer Active */
89 #define UHCSTAT_RWUE	(1 << 7)	/* HCI Remote Wake Up Event */
90 
91 #define UHCHR           (0x0064) /* UHC Reset Register */
92 #define UHCHR_SSEP3	(1 << 11)	/* Sleep Standby Enable for Port3 */
93 #define UHCHR_SSEP2	(1 << 10)	/* Sleep Standby Enable for Port2 */
94 #define UHCHR_SSEP1	(1 << 9)	/* Sleep Standby Enable for Port1 */
95 #define UHCHR_PCPL	(1 << 7)	/* Power control polarity low */
96 #define UHCHR_PSPL	(1 << 6)	/* Power sense polarity low */
97 #define UHCHR_SSE	(1 << 5)	/* Sleep Standby Enable */
98 #define UHCHR_UIT	(1 << 4)	/* USB Interrupt Test */
99 #define UHCHR_SSDC	(1 << 3)	/* Simulation Scale Down Clock */
100 #define UHCHR_CGR	(1 << 2)	/* Clock Generation Reset */
101 #define UHCHR_FHR	(1 << 1)	/* Force Host Controller Reset */
102 #define UHCHR_FSBIR	(1 << 0)	/* Force System Bus Iface Reset */
103 
104 #define UHCHIE          (0x0068) /* UHC Interrupt Enable Register*/
105 #define UHCHIE_UPS3IE	(1 << 14)	/* Power Sense Port3 IntEn */
106 #define UHCHIE_UPRIE	(1 << 13)	/* Port Resume IntEn */
107 #define UHCHIE_UPS2IE	(1 << 12)	/* Power Sense Port2 IntEn */
108 #define UHCHIE_UPS1IE	(1 << 11)	/* Power Sense Port1 IntEn */
109 #define UHCHIE_TAIE	(1 << 10)	/* HCI Interface Transfer Abort
110 					   Interrupt Enable*/
111 #define UHCHIE_HBAIE	(1 << 8)	/* HCI Buffer Active IntEn */
112 #define UHCHIE_RWIE	(1 << 7)	/* Remote Wake-up IntEn */
113 
114 #define UHCHIT          (0x006C) /* UHC Interrupt Test register */
115 
116 #define PXA_UHC_MAX_PORTNUM    3
117 
118 static const char hcd_name[] = "ohci-pxa27x";
119 
120 static struct hc_driver __read_mostly ohci_pxa27x_hc_driver;
121 
122 struct pxa27x_ohci {
123 	struct clk	*clk;
124 	void __iomem	*mmio_base;
125 	struct regulator *vbus[3];
126 	bool		vbus_enabled[3];
127 };
128 
129 #define to_pxa27x_ohci(hcd)	(struct pxa27x_ohci *)(hcd_to_ohci(hcd)->priv)
130 
131 /*
132   PMM_NPS_MODE -- PMM Non-power switching mode
133       Ports are powered continuously.
134 
135   PMM_GLOBAL_MODE -- PMM global switching mode
136       All ports are powered at the same time.
137 
138   PMM_PERPORT_MODE -- PMM per port switching mode
139       Ports are powered individually.
140  */
141 static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *pxa_ohci, int mode)
142 {
143 	uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);
144 	uint32_t uhcrhdb = __raw_readl(pxa_ohci->mmio_base + UHCRHDB);
145 
146 	switch (mode) {
147 	case PMM_NPS_MODE:
148 		uhcrhda |= RH_A_NPS;
149 		break;
150 	case PMM_GLOBAL_MODE:
151 		uhcrhda &= ~(RH_A_NPS | RH_A_PSM);
152 		break;
153 	case PMM_PERPORT_MODE:
154 		uhcrhda &= ~(RH_A_NPS);
155 		uhcrhda |= RH_A_PSM;
156 
157 		/* Set port power control mask bits, only 3 ports. */
158 		uhcrhdb |= (0x7<<17);
159 		break;
160 	default:
161 		printk( KERN_ERR
162 			"Invalid mode %d, set to non-power switch mode.\n",
163 			mode );
164 
165 		uhcrhda |= RH_A_NPS;
166 	}
167 
168 	__raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);
169 	__raw_writel(uhcrhdb, pxa_ohci->mmio_base + UHCRHDB);
170 	return 0;
171 }
172 
173 static int pxa27x_ohci_set_vbus_power(struct pxa27x_ohci *pxa_ohci,
174 				      unsigned int port, bool enable)
175 {
176 	struct regulator *vbus = pxa_ohci->vbus[port];
177 	int ret = 0;
178 
179 	if (IS_ERR_OR_NULL(vbus))
180 		return 0;
181 
182 	if (enable && !pxa_ohci->vbus_enabled[port])
183 		ret = regulator_enable(vbus);
184 	else if (!enable && pxa_ohci->vbus_enabled[port])
185 		ret = regulator_disable(vbus);
186 
187 	if (ret < 0)
188 		return ret;
189 
190 	pxa_ohci->vbus_enabled[port] = enable;
191 
192 	return 0;
193 }
194 
195 static int pxa27x_ohci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
196 				   u16 wIndex, char *buf, u16 wLength)
197 {
198 	struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
199 	int ret;
200 
201 	switch (typeReq) {
202 	case SetPortFeature:
203 	case ClearPortFeature:
204 		if (!wIndex || wIndex > 3)
205 			return -EPIPE;
206 
207 		if (wValue != USB_PORT_FEAT_POWER)
208 			break;
209 
210 		ret = pxa27x_ohci_set_vbus_power(pxa_ohci, wIndex - 1,
211 						 typeReq == SetPortFeature);
212 		if (ret)
213 			return ret;
214 		break;
215 	}
216 
217 	return ohci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
218 }
219 /*-------------------------------------------------------------------------*/
220 
221 static inline void pxa27x_setup_hc(struct pxa27x_ohci *pxa_ohci,
222 				   struct pxaohci_platform_data *inf)
223 {
224 	uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);
225 	uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);
226 
227 	if (inf->flags & ENABLE_PORT1)
228 		uhchr &= ~UHCHR_SSEP1;
229 
230 	if (inf->flags & ENABLE_PORT2)
231 		uhchr &= ~UHCHR_SSEP2;
232 
233 	if (inf->flags & ENABLE_PORT3)
234 		uhchr &= ~UHCHR_SSEP3;
235 
236 	if (inf->flags & POWER_CONTROL_LOW)
237 		uhchr |= UHCHR_PCPL;
238 
239 	if (inf->flags & POWER_SENSE_LOW)
240 		uhchr |= UHCHR_PSPL;
241 
242 	if (inf->flags & NO_OC_PROTECTION)
243 		uhcrhda |= UHCRHDA_NOCP;
244 	else
245 		uhcrhda &= ~UHCRHDA_NOCP;
246 
247 	if (inf->flags & OC_MODE_PERPORT)
248 		uhcrhda |= UHCRHDA_OCPM;
249 	else
250 		uhcrhda &= ~UHCRHDA_OCPM;
251 
252 	if (inf->power_on_delay) {
253 		uhcrhda &= ~UHCRHDA_POTPGT(0xff);
254 		uhcrhda |= UHCRHDA_POTPGT(inf->power_on_delay / 2);
255 	}
256 
257 	__raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
258 	__raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);
259 }
260 
261 static inline void pxa27x_reset_hc(struct pxa27x_ohci *pxa_ohci)
262 {
263 	uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);
264 
265 	__raw_writel(uhchr | UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);
266 	udelay(11);
267 	__raw_writel(uhchr & ~UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);
268 }
269 
270 #ifdef CONFIG_PXA27x
271 extern void pxa27x_clear_otgph(void);
272 #else
273 #define pxa27x_clear_otgph()	do {} while (0)
274 #endif
275 
276 static int pxa27x_start_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev)
277 {
278 	int retval;
279 	struct pxaohci_platform_data *inf;
280 	uint32_t uhchr;
281 	struct usb_hcd *hcd = dev_get_drvdata(dev);
282 
283 	inf = dev_get_platdata(dev);
284 
285 	retval = clk_prepare_enable(pxa_ohci->clk);
286 	if (retval)
287 		return retval;
288 
289 	pxa27x_reset_hc(pxa_ohci);
290 
291 	uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) | UHCHR_FSBIR;
292 	__raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
293 
294 	while (__raw_readl(pxa_ohci->mmio_base + UHCHR) & UHCHR_FSBIR)
295 		cpu_relax();
296 
297 	pxa27x_setup_hc(pxa_ohci, inf);
298 
299 	if (inf->init)
300 		retval = inf->init(dev);
301 
302 	if (retval < 0) {
303 		clk_disable_unprepare(pxa_ohci->clk);
304 		return retval;
305 	}
306 
307 	if (cpu_is_pxa3xx())
308 		pxa3xx_u2d_start_hc(&hcd->self);
309 
310 	uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
311 	__raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
312 	__raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, pxa_ohci->mmio_base + UHCHIE);
313 
314 	/* Clear any OTG Pin Hold */
315 	pxa27x_clear_otgph();
316 	return 0;
317 }
318 
319 static void pxa27x_stop_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev)
320 {
321 	struct pxaohci_platform_data *inf;
322 	struct usb_hcd *hcd = dev_get_drvdata(dev);
323 	uint32_t uhccoms;
324 
325 	inf = dev_get_platdata(dev);
326 
327 	if (cpu_is_pxa3xx())
328 		pxa3xx_u2d_stop_hc(&hcd->self);
329 
330 	if (inf->exit)
331 		inf->exit(dev);
332 
333 	pxa27x_reset_hc(pxa_ohci);
334 
335 	/* Host Controller Reset */
336 	uhccoms = __raw_readl(pxa_ohci->mmio_base + UHCCOMS) | 0x01;
337 	__raw_writel(uhccoms, pxa_ohci->mmio_base + UHCCOMS);
338 	udelay(10);
339 
340 	clk_disable_unprepare(pxa_ohci->clk);
341 }
342 
343 #ifdef CONFIG_OF
344 static const struct of_device_id pxa_ohci_dt_ids[] = {
345 	{ .compatible = "marvell,pxa-ohci" },
346 	{ }
347 };
348 
349 MODULE_DEVICE_TABLE(of, pxa_ohci_dt_ids);
350 
351 static int ohci_pxa_of_init(struct platform_device *pdev)
352 {
353 	struct device_node *np = pdev->dev.of_node;
354 	struct pxaohci_platform_data *pdata;
355 	u32 tmp;
356 	int ret;
357 
358 	if (!np)
359 		return 0;
360 
361 	/* Right now device-tree probed devices don't get dma_mask set.
362 	 * Since shared usb code relies on it, set it here for now.
363 	 * Once we have dma capability bindings this can go away.
364 	 */
365 	ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
366 	if (ret)
367 		return ret;
368 
369 	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
370 	if (!pdata)
371 		return -ENOMEM;
372 
373 	if (of_property_read_bool(np, "marvell,enable-port1"))
374 		pdata->flags |= ENABLE_PORT1;
375 	if (of_property_read_bool(np, "marvell,enable-port2"))
376 		pdata->flags |= ENABLE_PORT2;
377 	if (of_property_read_bool(np, "marvell,enable-port3"))
378 		pdata->flags |= ENABLE_PORT3;
379 	if (of_property_read_bool(np, "marvell,port-sense-low"))
380 		pdata->flags |= POWER_SENSE_LOW;
381 	if (of_property_read_bool(np, "marvell,power-control-low"))
382 		pdata->flags |= POWER_CONTROL_LOW;
383 	if (of_property_read_bool(np, "marvell,no-oc-protection"))
384 		pdata->flags |= NO_OC_PROTECTION;
385 	if (of_property_read_bool(np, "marvell,oc-mode-perport"))
386 		pdata->flags |= OC_MODE_PERPORT;
387 	if (!of_property_read_u32(np, "marvell,power-on-delay", &tmp))
388 		pdata->power_on_delay = tmp;
389 	if (!of_property_read_u32(np, "marvell,port-mode", &tmp))
390 		pdata->port_mode = tmp;
391 	if (!of_property_read_u32(np, "marvell,power-budget", &tmp))
392 		pdata->power_budget = tmp;
393 
394 	pdev->dev.platform_data = pdata;
395 
396 	return 0;
397 }
398 #else
399 static int ohci_pxa_of_init(struct platform_device *pdev)
400 {
401 	return 0;
402 }
403 #endif
404 
405 /*-------------------------------------------------------------------------*/
406 
407 /* configure so an HC device and id are always provided */
408 /* always called with process context; sleeping is OK */
409 
410 
411 /**
412  * ohci_hcd_pxa27x_probe - initialize pxa27x-based HCDs
413  * @pdev:	USB Host controller to probe
414  *
415  * Context: task context, might sleep
416  *
417  * Allocates basic resources for this USB host controller, and
418  * then invokes the start() method for the HCD associated with it
419  * through the hotplug entry's driver_data.
420  */
421 static int ohci_hcd_pxa27x_probe(struct platform_device *pdev)
422 {
423 	int retval, irq;
424 	struct usb_hcd *hcd;
425 	struct pxaohci_platform_data *inf;
426 	struct pxa27x_ohci *pxa_ohci;
427 	struct ohci_hcd *ohci;
428 	struct resource *r;
429 	struct clk *usb_clk;
430 	unsigned int i;
431 
432 	retval = ohci_pxa_of_init(pdev);
433 	if (retval)
434 		return retval;
435 
436 	inf = dev_get_platdata(&pdev->dev);
437 
438 	if (!inf)
439 		return -ENODEV;
440 
441 	irq = platform_get_irq(pdev, 0);
442 	if (irq < 0) {
443 		pr_err("no resource of IORESOURCE_IRQ");
444 		return irq;
445 	}
446 
447 	usb_clk = devm_clk_get(&pdev->dev, NULL);
448 	if (IS_ERR(usb_clk))
449 		return PTR_ERR(usb_clk);
450 
451 	hcd = usb_create_hcd(&ohci_pxa27x_hc_driver, &pdev->dev, "pxa27x");
452 	if (!hcd)
453 		return -ENOMEM;
454 
455 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
456 	hcd->regs = devm_ioremap_resource(&pdev->dev, r);
457 	if (IS_ERR(hcd->regs)) {
458 		retval = PTR_ERR(hcd->regs);
459 		goto err;
460 	}
461 	hcd->rsrc_start = r->start;
462 	hcd->rsrc_len = resource_size(r);
463 
464 	/* initialize "struct pxa27x_ohci" */
465 	pxa_ohci = to_pxa27x_ohci(hcd);
466 	pxa_ohci->clk = usb_clk;
467 	pxa_ohci->mmio_base = (void __iomem *)hcd->regs;
468 
469 	for (i = 0; i < 3; ++i) {
470 		char name[6];
471 
472 		if (!(inf->flags & (ENABLE_PORT1 << i)))
473 			continue;
474 
475 		sprintf(name, "vbus%u", i + 1);
476 		pxa_ohci->vbus[i] = devm_regulator_get(&pdev->dev, name);
477 	}
478 
479 	retval = pxa27x_start_hc(pxa_ohci, &pdev->dev);
480 	if (retval < 0) {
481 		pr_debug("pxa27x_start_hc failed");
482 		goto err;
483 	}
484 
485 	/* Select Power Management Mode */
486 	pxa27x_ohci_select_pmm(pxa_ohci, inf->port_mode);
487 
488 	if (inf->power_budget)
489 		hcd->power_budget = inf->power_budget;
490 
491 	/* The value of NDP in roothub_a is incorrect on this hardware */
492 	ohci = hcd_to_ohci(hcd);
493 	ohci->num_ports = 3;
494 
495 	retval = usb_add_hcd(hcd, irq, 0);
496 	if (retval == 0) {
497 		device_wakeup_enable(hcd->self.controller);
498 		return retval;
499 	}
500 
501 	pxa27x_stop_hc(pxa_ohci, &pdev->dev);
502  err:
503 	usb_put_hcd(hcd);
504 	return retval;
505 }
506 
507 
508 /* may be called without controller electrically present */
509 /* may be called with controller, bus, and devices active */
510 
511 /**
512  * ohci_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs
513  * @pdev: USB Host Controller being removed
514  *
515  * Context: task context, might sleep
516  *
517  * Reverses the effect of ohci_hcd_pxa27x_probe(), first invoking
518  * the HCD's stop() method.  It is always called from a thread
519  * context, normally "rmmod", "apmd", or something similar.
520  */
521 static int ohci_hcd_pxa27x_remove(struct platform_device *pdev)
522 {
523 	struct usb_hcd *hcd = platform_get_drvdata(pdev);
524 	struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
525 	unsigned int i;
526 
527 	usb_remove_hcd(hcd);
528 	pxa27x_stop_hc(pxa_ohci, &pdev->dev);
529 
530 	for (i = 0; i < 3; ++i)
531 		pxa27x_ohci_set_vbus_power(pxa_ohci, i, false);
532 
533 	usb_put_hcd(hcd);
534 	return 0;
535 }
536 
537 /*-------------------------------------------------------------------------*/
538 
539 #ifdef CONFIG_PM
540 static int ohci_hcd_pxa27x_drv_suspend(struct device *dev)
541 {
542 	struct usb_hcd *hcd = dev_get_drvdata(dev);
543 	struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
544 	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
545 	bool do_wakeup = device_may_wakeup(dev);
546 	int ret;
547 
548 
549 	if (time_before(jiffies, ohci->next_statechange))
550 		msleep(5);
551 	ohci->next_statechange = jiffies;
552 
553 	ret = ohci_suspend(hcd, do_wakeup);
554 	if (ret)
555 		return ret;
556 
557 	pxa27x_stop_hc(pxa_ohci, dev);
558 	return ret;
559 }
560 
561 static int ohci_hcd_pxa27x_drv_resume(struct device *dev)
562 {
563 	struct usb_hcd *hcd = dev_get_drvdata(dev);
564 	struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
565 	struct pxaohci_platform_data *inf = dev_get_platdata(dev);
566 	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
567 	int status;
568 
569 	if (time_before(jiffies, ohci->next_statechange))
570 		msleep(5);
571 	ohci->next_statechange = jiffies;
572 
573 	status = pxa27x_start_hc(pxa_ohci, dev);
574 	if (status < 0)
575 		return status;
576 
577 	/* Select Power Management Mode */
578 	pxa27x_ohci_select_pmm(pxa_ohci, inf->port_mode);
579 
580 	ohci_resume(hcd, false);
581 	return 0;
582 }
583 
584 static const struct dev_pm_ops ohci_hcd_pxa27x_pm_ops = {
585 	.suspend	= ohci_hcd_pxa27x_drv_suspend,
586 	.resume		= ohci_hcd_pxa27x_drv_resume,
587 };
588 #endif
589 
590 static struct platform_driver ohci_hcd_pxa27x_driver = {
591 	.probe		= ohci_hcd_pxa27x_probe,
592 	.remove		= ohci_hcd_pxa27x_remove,
593 	.shutdown	= usb_hcd_platform_shutdown,
594 	.driver		= {
595 		.name	= "pxa27x-ohci",
596 		.of_match_table = of_match_ptr(pxa_ohci_dt_ids),
597 #ifdef CONFIG_PM
598 		.pm	= &ohci_hcd_pxa27x_pm_ops,
599 #endif
600 	},
601 };
602 
603 static const struct ohci_driver_overrides pxa27x_overrides __initconst = {
604 	.extra_priv_size =      sizeof(struct pxa27x_ohci),
605 };
606 
607 static int __init ohci_pxa27x_init(void)
608 {
609 	if (usb_disabled())
610 		return -ENODEV;
611 
612 	pr_info("%s: " DRIVER_DESC "\n", hcd_name);
613 
614 	ohci_init_driver(&ohci_pxa27x_hc_driver, &pxa27x_overrides);
615 	ohci_pxa27x_hc_driver.hub_control = pxa27x_ohci_hub_control;
616 
617 	return platform_driver_register(&ohci_hcd_pxa27x_driver);
618 }
619 module_init(ohci_pxa27x_init);
620 
621 static void __exit ohci_pxa27x_cleanup(void)
622 {
623 	platform_driver_unregister(&ohci_hcd_pxa27x_driver);
624 }
625 module_exit(ohci_pxa27x_cleanup);
626 
627 MODULE_DESCRIPTION(DRIVER_DESC);
628 MODULE_LICENSE("GPL");
629 MODULE_ALIAS("platform:pxa27x-ohci");
630