1 /* 2 * OHCI HCD (Host Controller Driver) for USB. 3 * 4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net> 6 * (C) Copyright 2002 Hewlett-Packard Company 7 * 8 * Bus Glue for pxa27x 9 * 10 * Written by Christopher Hoover <ch@hpl.hp.com> 11 * Based on fragments of previous driver by Russell King et al. 12 * 13 * Modified for LH7A404 from ohci-sa1111.c 14 * by Durgesh Pattamatta <pattamattad@sharpsec.com> 15 * 16 * Modified for pxa27x from ohci-lh7a404.c 17 * by Nick Bane <nick@cecomputing.co.uk> 26-8-2004 18 * 19 * This file is licenced under the GPL. 20 */ 21 22 #include <linux/device.h> 23 #include <linux/signal.h> 24 #include <linux/platform_device.h> 25 #include <linux/clk.h> 26 #include <mach/ohci.h> 27 28 /* 29 * UHC: USB Host Controller (OHCI-like) register definitions 30 */ 31 #define UHCREV (0x0000) /* UHC HCI Spec Revision */ 32 #define UHCHCON (0x0004) /* UHC Host Control Register */ 33 #define UHCCOMS (0x0008) /* UHC Command Status Register */ 34 #define UHCINTS (0x000C) /* UHC Interrupt Status Register */ 35 #define UHCINTE (0x0010) /* UHC Interrupt Enable */ 36 #define UHCINTD (0x0014) /* UHC Interrupt Disable */ 37 #define UHCHCCA (0x0018) /* UHC Host Controller Comm. Area */ 38 #define UHCPCED (0x001C) /* UHC Period Current Endpt Descr */ 39 #define UHCCHED (0x0020) /* UHC Control Head Endpt Descr */ 40 #define UHCCCED (0x0024) /* UHC Control Current Endpt Descr */ 41 #define UHCBHED (0x0028) /* UHC Bulk Head Endpt Descr */ 42 #define UHCBCED (0x002C) /* UHC Bulk Current Endpt Descr */ 43 #define UHCDHEAD (0x0030) /* UHC Done Head */ 44 #define UHCFMI (0x0034) /* UHC Frame Interval */ 45 #define UHCFMR (0x0038) /* UHC Frame Remaining */ 46 #define UHCFMN (0x003C) /* UHC Frame Number */ 47 #define UHCPERS (0x0040) /* UHC Periodic Start */ 48 #define UHCLS (0x0044) /* UHC Low Speed Threshold */ 49 50 #define UHCRHDA (0x0048) /* UHC Root Hub Descriptor A */ 51 #define UHCRHDA_NOCP (1 << 12) /* No over current protection */ 52 #define UHCRHDA_OCPM (1 << 11) /* Over Current Protection Mode */ 53 #define UHCRHDA_POTPGT(x) \ 54 (((x) & 0xff) << 24) /* Power On To Power Good Time */ 55 56 #define UHCRHDB (0x004C) /* UHC Root Hub Descriptor B */ 57 #define UHCRHS (0x0050) /* UHC Root Hub Status */ 58 #define UHCRHPS1 (0x0054) /* UHC Root Hub Port 1 Status */ 59 #define UHCRHPS2 (0x0058) /* UHC Root Hub Port 2 Status */ 60 #define UHCRHPS3 (0x005C) /* UHC Root Hub Port 3 Status */ 61 62 #define UHCSTAT (0x0060) /* UHC Status Register */ 63 #define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */ 64 #define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/ 65 #define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/ 66 #define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */ 67 #define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */ 68 #define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */ 69 #define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */ 70 #define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */ 71 #define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */ 72 73 #define UHCHR (0x0064) /* UHC Reset Register */ 74 #define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */ 75 #define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */ 76 #define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */ 77 #define UHCHR_PCPL (1 << 7) /* Power control polarity low */ 78 #define UHCHR_PSPL (1 << 6) /* Power sense polarity low */ 79 #define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */ 80 #define UHCHR_UIT (1 << 4) /* USB Interrupt Test */ 81 #define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */ 82 #define UHCHR_CGR (1 << 2) /* Clock Generation Reset */ 83 #define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */ 84 #define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */ 85 86 #define UHCHIE (0x0068) /* UHC Interrupt Enable Register*/ 87 #define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */ 88 #define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */ 89 #define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */ 90 #define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */ 91 #define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort 92 Interrupt Enable*/ 93 #define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */ 94 #define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */ 95 96 #define UHCHIT (0x006C) /* UHC Interrupt Test register */ 97 98 #define PXA_UHC_MAX_PORTNUM 3 99 100 struct pxa27x_ohci { 101 /* must be 1st member here for hcd_to_ohci() to work */ 102 struct ohci_hcd ohci; 103 104 struct device *dev; 105 struct clk *clk; 106 void __iomem *mmio_base; 107 }; 108 109 #define to_pxa27x_ohci(hcd) (struct pxa27x_ohci *)hcd_to_ohci(hcd) 110 111 /* 112 PMM_NPS_MODE -- PMM Non-power switching mode 113 Ports are powered continuously. 114 115 PMM_GLOBAL_MODE -- PMM global switching mode 116 All ports are powered at the same time. 117 118 PMM_PERPORT_MODE -- PMM per port switching mode 119 Ports are powered individually. 120 */ 121 static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *ohci, int mode) 122 { 123 uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA); 124 uint32_t uhcrhdb = __raw_readl(ohci->mmio_base + UHCRHDB); 125 126 switch (mode) { 127 case PMM_NPS_MODE: 128 uhcrhda |= RH_A_NPS; 129 break; 130 case PMM_GLOBAL_MODE: 131 uhcrhda &= ~(RH_A_NPS & RH_A_PSM); 132 break; 133 case PMM_PERPORT_MODE: 134 uhcrhda &= ~(RH_A_NPS); 135 uhcrhda |= RH_A_PSM; 136 137 /* Set port power control mask bits, only 3 ports. */ 138 uhcrhdb |= (0x7<<17); 139 break; 140 default: 141 printk( KERN_ERR 142 "Invalid mode %d, set to non-power switch mode.\n", 143 mode ); 144 145 uhcrhda |= RH_A_NPS; 146 } 147 148 __raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA); 149 __raw_writel(uhcrhdb, ohci->mmio_base + UHCRHDB); 150 return 0; 151 } 152 153 extern int usb_disabled(void); 154 155 /*-------------------------------------------------------------------------*/ 156 157 static inline void pxa27x_setup_hc(struct pxa27x_ohci *ohci, 158 struct pxaohci_platform_data *inf) 159 { 160 uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR); 161 uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA); 162 163 if (inf->flags & ENABLE_PORT1) 164 uhchr &= ~UHCHR_SSEP1; 165 166 if (inf->flags & ENABLE_PORT2) 167 uhchr &= ~UHCHR_SSEP2; 168 169 if (inf->flags & ENABLE_PORT3) 170 uhchr &= ~UHCHR_SSEP3; 171 172 if (inf->flags & POWER_CONTROL_LOW) 173 uhchr |= UHCHR_PCPL; 174 175 if (inf->flags & POWER_SENSE_LOW) 176 uhchr |= UHCHR_PSPL; 177 178 if (inf->flags & NO_OC_PROTECTION) 179 uhcrhda |= UHCRHDA_NOCP; 180 181 if (inf->flags & OC_MODE_PERPORT) 182 uhcrhda |= UHCRHDA_OCPM; 183 184 if (inf->power_on_delay) { 185 uhcrhda &= ~UHCRHDA_POTPGT(0xff); 186 uhcrhda |= UHCRHDA_POTPGT(inf->power_on_delay / 2); 187 } 188 189 __raw_writel(uhchr, ohci->mmio_base + UHCHR); 190 __raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA); 191 } 192 193 static inline void pxa27x_reset_hc(struct pxa27x_ohci *ohci) 194 { 195 uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR); 196 197 __raw_writel(uhchr | UHCHR_FHR, ohci->mmio_base + UHCHR); 198 udelay(11); 199 __raw_writel(uhchr & ~UHCHR_FHR, ohci->mmio_base + UHCHR); 200 } 201 202 #ifdef CONFIG_CPU_PXA27x 203 extern void pxa27x_clear_otgph(void); 204 #else 205 #define pxa27x_clear_otgph() do {} while (0) 206 #endif 207 208 static int pxa27x_start_hc(struct pxa27x_ohci *ohci, struct device *dev) 209 { 210 int retval = 0; 211 struct pxaohci_platform_data *inf; 212 uint32_t uhchr; 213 214 inf = dev->platform_data; 215 216 clk_enable(ohci->clk); 217 218 pxa27x_reset_hc(ohci); 219 220 uhchr = __raw_readl(ohci->mmio_base + UHCHR) | UHCHR_FSBIR; 221 __raw_writel(uhchr, ohci->mmio_base + UHCHR); 222 223 while (__raw_readl(ohci->mmio_base + UHCHR) & UHCHR_FSBIR) 224 cpu_relax(); 225 226 pxa27x_setup_hc(ohci, inf); 227 228 if (inf->init) 229 retval = inf->init(dev); 230 231 if (retval < 0) 232 return retval; 233 234 uhchr = __raw_readl(ohci->mmio_base + UHCHR) & ~UHCHR_SSE; 235 __raw_writel(uhchr, ohci->mmio_base + UHCHR); 236 __raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, ohci->mmio_base + UHCHIE); 237 238 /* Clear any OTG Pin Hold */ 239 pxa27x_clear_otgph(); 240 return 0; 241 } 242 243 static void pxa27x_stop_hc(struct pxa27x_ohci *ohci, struct device *dev) 244 { 245 struct pxaohci_platform_data *inf; 246 uint32_t uhccoms; 247 248 inf = dev->platform_data; 249 250 if (inf->exit) 251 inf->exit(dev); 252 253 pxa27x_reset_hc(ohci); 254 255 /* Host Controller Reset */ 256 uhccoms = __raw_readl(ohci->mmio_base + UHCCOMS) | 0x01; 257 __raw_writel(uhccoms, ohci->mmio_base + UHCCOMS); 258 udelay(10); 259 260 clk_disable(ohci->clk); 261 } 262 263 264 /*-------------------------------------------------------------------------*/ 265 266 /* configure so an HC device and id are always provided */ 267 /* always called with process context; sleeping is OK */ 268 269 270 /** 271 * usb_hcd_pxa27x_probe - initialize pxa27x-based HCDs 272 * Context: !in_interrupt() 273 * 274 * Allocates basic resources for this USB host controller, and 275 * then invokes the start() method for the HCD associated with it 276 * through the hotplug entry's driver_data. 277 * 278 */ 279 int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device *pdev) 280 { 281 int retval, irq; 282 struct usb_hcd *hcd; 283 struct pxaohci_platform_data *inf; 284 struct pxa27x_ohci *ohci; 285 struct resource *r; 286 struct clk *usb_clk; 287 288 inf = pdev->dev.platform_data; 289 290 if (!inf) 291 return -ENODEV; 292 293 irq = platform_get_irq(pdev, 0); 294 if (irq < 0) { 295 pr_err("no resource of IORESOURCE_IRQ"); 296 return -ENXIO; 297 } 298 299 usb_clk = clk_get(&pdev->dev, NULL); 300 if (IS_ERR(usb_clk)) 301 return PTR_ERR(usb_clk); 302 303 hcd = usb_create_hcd (driver, &pdev->dev, "pxa27x"); 304 if (!hcd) 305 return -ENOMEM; 306 307 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 308 if (!r) { 309 pr_err("no resource of IORESOURCE_MEM"); 310 retval = -ENXIO; 311 goto err1; 312 } 313 314 hcd->rsrc_start = r->start; 315 hcd->rsrc_len = resource_size(r); 316 317 if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { 318 pr_debug("request_mem_region failed"); 319 retval = -EBUSY; 320 goto err1; 321 } 322 323 hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); 324 if (!hcd->regs) { 325 pr_debug("ioremap failed"); 326 retval = -ENOMEM; 327 goto err2; 328 } 329 330 /* initialize "struct pxa27x_ohci" */ 331 ohci = (struct pxa27x_ohci *)hcd_to_ohci(hcd); 332 ohci->dev = &pdev->dev; 333 ohci->clk = usb_clk; 334 ohci->mmio_base = (void __iomem *)hcd->regs; 335 336 if ((retval = pxa27x_start_hc(ohci, &pdev->dev)) < 0) { 337 pr_debug("pxa27x_start_hc failed"); 338 goto err3; 339 } 340 341 /* Select Power Management Mode */ 342 pxa27x_ohci_select_pmm(ohci, inf->port_mode); 343 344 if (inf->power_budget) 345 hcd->power_budget = inf->power_budget; 346 347 ohci_hcd_init(hcd_to_ohci(hcd)); 348 349 retval = usb_add_hcd(hcd, irq, IRQF_DISABLED); 350 if (retval == 0) 351 return retval; 352 353 pxa27x_stop_hc(ohci, &pdev->dev); 354 err3: 355 iounmap(hcd->regs); 356 err2: 357 release_mem_region(hcd->rsrc_start, hcd->rsrc_len); 358 err1: 359 usb_put_hcd(hcd); 360 clk_put(usb_clk); 361 return retval; 362 } 363 364 365 /* may be called without controller electrically present */ 366 /* may be called with controller, bus, and devices active */ 367 368 /** 369 * usb_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs 370 * @dev: USB Host Controller being removed 371 * Context: !in_interrupt() 372 * 373 * Reverses the effect of usb_hcd_pxa27x_probe(), first invoking 374 * the HCD's stop() method. It is always called from a thread 375 * context, normally "rmmod", "apmd", or something similar. 376 * 377 */ 378 void usb_hcd_pxa27x_remove (struct usb_hcd *hcd, struct platform_device *pdev) 379 { 380 struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd); 381 382 usb_remove_hcd(hcd); 383 pxa27x_stop_hc(ohci, &pdev->dev); 384 iounmap(hcd->regs); 385 release_mem_region(hcd->rsrc_start, hcd->rsrc_len); 386 usb_put_hcd(hcd); 387 clk_put(ohci->clk); 388 } 389 390 /*-------------------------------------------------------------------------*/ 391 392 static int __devinit 393 ohci_pxa27x_start (struct usb_hcd *hcd) 394 { 395 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 396 int ret; 397 398 ohci_dbg (ohci, "ohci_pxa27x_start, ohci:%p", ohci); 399 400 /* The value of NDP in roothub_a is incorrect on this hardware */ 401 ohci->num_ports = 3; 402 403 if ((ret = ohci_init(ohci)) < 0) 404 return ret; 405 406 if ((ret = ohci_run (ohci)) < 0) { 407 err ("can't start %s", hcd->self.bus_name); 408 ohci_stop (hcd); 409 return ret; 410 } 411 412 return 0; 413 } 414 415 /*-------------------------------------------------------------------------*/ 416 417 static const struct hc_driver ohci_pxa27x_hc_driver = { 418 .description = hcd_name, 419 .product_desc = "PXA27x OHCI", 420 .hcd_priv_size = sizeof(struct pxa27x_ohci), 421 422 /* 423 * generic hardware linkage 424 */ 425 .irq = ohci_irq, 426 .flags = HCD_USB11 | HCD_MEMORY, 427 428 /* 429 * basic lifecycle operations 430 */ 431 .start = ohci_pxa27x_start, 432 .stop = ohci_stop, 433 .shutdown = ohci_shutdown, 434 435 /* 436 * managing i/o requests and associated device resources 437 */ 438 .urb_enqueue = ohci_urb_enqueue, 439 .urb_dequeue = ohci_urb_dequeue, 440 .endpoint_disable = ohci_endpoint_disable, 441 442 /* 443 * scheduling support 444 */ 445 .get_frame_number = ohci_get_frame, 446 447 /* 448 * root hub support 449 */ 450 .hub_status_data = ohci_hub_status_data, 451 .hub_control = ohci_hub_control, 452 #ifdef CONFIG_PM 453 .bus_suspend = ohci_bus_suspend, 454 .bus_resume = ohci_bus_resume, 455 #endif 456 .start_port_reset = ohci_start_port_reset, 457 }; 458 459 /*-------------------------------------------------------------------------*/ 460 461 static int ohci_hcd_pxa27x_drv_probe(struct platform_device *pdev) 462 { 463 pr_debug ("In ohci_hcd_pxa27x_drv_probe"); 464 465 if (usb_disabled()) 466 return -ENODEV; 467 468 return usb_hcd_pxa27x_probe(&ohci_pxa27x_hc_driver, pdev); 469 } 470 471 static int ohci_hcd_pxa27x_drv_remove(struct platform_device *pdev) 472 { 473 struct usb_hcd *hcd = platform_get_drvdata(pdev); 474 475 usb_hcd_pxa27x_remove(hcd, pdev); 476 platform_set_drvdata(pdev, NULL); 477 return 0; 478 } 479 480 #ifdef CONFIG_PM 481 static int ohci_hcd_pxa27x_drv_suspend(struct platform_device *pdev, pm_message_t state) 482 { 483 struct usb_hcd *hcd = platform_get_drvdata(pdev); 484 struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd); 485 486 if (time_before(jiffies, ohci->ohci.next_statechange)) 487 msleep(5); 488 ohci->ohci.next_statechange = jiffies; 489 490 pxa27x_stop_hc(ohci, &pdev->dev); 491 hcd->state = HC_STATE_SUSPENDED; 492 493 return 0; 494 } 495 496 static int ohci_hcd_pxa27x_drv_resume(struct platform_device *pdev) 497 { 498 struct usb_hcd *hcd = platform_get_drvdata(pdev); 499 struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd); 500 int status; 501 502 if (time_before(jiffies, ohci->ohci.next_statechange)) 503 msleep(5); 504 ohci->ohci.next_statechange = jiffies; 505 506 if ((status = pxa27x_start_hc(ohci, &pdev->dev)) < 0) 507 return status; 508 509 ohci_finish_controller_resume(hcd); 510 return 0; 511 } 512 #endif 513 514 /* work with hotplug and coldplug */ 515 MODULE_ALIAS("platform:pxa27x-ohci"); 516 517 static struct platform_driver ohci_hcd_pxa27x_driver = { 518 .probe = ohci_hcd_pxa27x_drv_probe, 519 .remove = ohci_hcd_pxa27x_drv_remove, 520 .shutdown = usb_hcd_platform_shutdown, 521 #ifdef CONFIG_PM 522 .suspend = ohci_hcd_pxa27x_drv_suspend, 523 .resume = ohci_hcd_pxa27x_drv_resume, 524 #endif 525 .driver = { 526 .name = "pxa27x-ohci", 527 .owner = THIS_MODULE, 528 }, 529 }; 530 531