1 /* 2 * OHCI HCD (Host Controller Driver) for USB. 3 * 4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net> 6 * (C) Copyright 2002 Hewlett-Packard Company 7 * 8 * Bus Glue for pxa27x 9 * 10 * Written by Christopher Hoover <ch@hpl.hp.com> 11 * Based on fragments of previous driver by Russell King et al. 12 * 13 * Modified for LH7A404 from ohci-sa1111.c 14 * by Durgesh Pattamatta <pattamattad@sharpsec.com> 15 * 16 * Modified for pxa27x from ohci-lh7a404.c 17 * by Nick Bane <nick@cecomputing.co.uk> 26-8-2004 18 * 19 * This file is licenced under the GPL. 20 */ 21 22 #include <linux/clk.h> 23 #include <linux/device.h> 24 #include <linux/io.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/of_platform.h> 28 #include <linux/of_gpio.h> 29 #include <linux/platform_data/usb-ohci-pxa27x.h> 30 #include <linux/platform_data/usb-pxa3xx-ulpi.h> 31 #include <linux/platform_device.h> 32 #include <linux/signal.h> 33 #include <linux/usb.h> 34 #include <linux/usb/hcd.h> 35 #include <linux/usb/otg.h> 36 37 #include <mach/hardware.h> 38 39 #include "ohci.h" 40 41 #define DRIVER_DESC "OHCI PXA27x/PXA3x driver" 42 43 /* 44 * UHC: USB Host Controller (OHCI-like) register definitions 45 */ 46 #define UHCREV (0x0000) /* UHC HCI Spec Revision */ 47 #define UHCHCON (0x0004) /* UHC Host Control Register */ 48 #define UHCCOMS (0x0008) /* UHC Command Status Register */ 49 #define UHCINTS (0x000C) /* UHC Interrupt Status Register */ 50 #define UHCINTE (0x0010) /* UHC Interrupt Enable */ 51 #define UHCINTD (0x0014) /* UHC Interrupt Disable */ 52 #define UHCHCCA (0x0018) /* UHC Host Controller Comm. Area */ 53 #define UHCPCED (0x001C) /* UHC Period Current Endpt Descr */ 54 #define UHCCHED (0x0020) /* UHC Control Head Endpt Descr */ 55 #define UHCCCED (0x0024) /* UHC Control Current Endpt Descr */ 56 #define UHCBHED (0x0028) /* UHC Bulk Head Endpt Descr */ 57 #define UHCBCED (0x002C) /* UHC Bulk Current Endpt Descr */ 58 #define UHCDHEAD (0x0030) /* UHC Done Head */ 59 #define UHCFMI (0x0034) /* UHC Frame Interval */ 60 #define UHCFMR (0x0038) /* UHC Frame Remaining */ 61 #define UHCFMN (0x003C) /* UHC Frame Number */ 62 #define UHCPERS (0x0040) /* UHC Periodic Start */ 63 #define UHCLS (0x0044) /* UHC Low Speed Threshold */ 64 65 #define UHCRHDA (0x0048) /* UHC Root Hub Descriptor A */ 66 #define UHCRHDA_NOCP (1 << 12) /* No over current protection */ 67 #define UHCRHDA_OCPM (1 << 11) /* Over Current Protection Mode */ 68 #define UHCRHDA_POTPGT(x) \ 69 (((x) & 0xff) << 24) /* Power On To Power Good Time */ 70 71 #define UHCRHDB (0x004C) /* UHC Root Hub Descriptor B */ 72 #define UHCRHS (0x0050) /* UHC Root Hub Status */ 73 #define UHCRHPS1 (0x0054) /* UHC Root Hub Port 1 Status */ 74 #define UHCRHPS2 (0x0058) /* UHC Root Hub Port 2 Status */ 75 #define UHCRHPS3 (0x005C) /* UHC Root Hub Port 3 Status */ 76 77 #define UHCSTAT (0x0060) /* UHC Status Register */ 78 #define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */ 79 #define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/ 80 #define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/ 81 #define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */ 82 #define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */ 83 #define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */ 84 #define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */ 85 #define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */ 86 #define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */ 87 88 #define UHCHR (0x0064) /* UHC Reset Register */ 89 #define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */ 90 #define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */ 91 #define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */ 92 #define UHCHR_PCPL (1 << 7) /* Power control polarity low */ 93 #define UHCHR_PSPL (1 << 6) /* Power sense polarity low */ 94 #define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */ 95 #define UHCHR_UIT (1 << 4) /* USB Interrupt Test */ 96 #define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */ 97 #define UHCHR_CGR (1 << 2) /* Clock Generation Reset */ 98 #define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */ 99 #define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */ 100 101 #define UHCHIE (0x0068) /* UHC Interrupt Enable Register*/ 102 #define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */ 103 #define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */ 104 #define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */ 105 #define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */ 106 #define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort 107 Interrupt Enable*/ 108 #define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */ 109 #define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */ 110 111 #define UHCHIT (0x006C) /* UHC Interrupt Test register */ 112 113 #define PXA_UHC_MAX_PORTNUM 3 114 115 static const char hcd_name[] = "ohci-pxa27x"; 116 117 static struct hc_driver __read_mostly ohci_pxa27x_hc_driver; 118 119 struct pxa27x_ohci { 120 struct clk *clk; 121 void __iomem *mmio_base; 122 }; 123 124 #define to_pxa27x_ohci(hcd) (struct pxa27x_ohci *)(hcd_to_ohci(hcd)->priv) 125 126 /* 127 PMM_NPS_MODE -- PMM Non-power switching mode 128 Ports are powered continuously. 129 130 PMM_GLOBAL_MODE -- PMM global switching mode 131 All ports are powered at the same time. 132 133 PMM_PERPORT_MODE -- PMM per port switching mode 134 Ports are powered individually. 135 */ 136 static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *pxa_ohci, int mode) 137 { 138 uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA); 139 uint32_t uhcrhdb = __raw_readl(pxa_ohci->mmio_base + UHCRHDB); 140 141 switch (mode) { 142 case PMM_NPS_MODE: 143 uhcrhda |= RH_A_NPS; 144 break; 145 case PMM_GLOBAL_MODE: 146 uhcrhda &= ~(RH_A_NPS & RH_A_PSM); 147 break; 148 case PMM_PERPORT_MODE: 149 uhcrhda &= ~(RH_A_NPS); 150 uhcrhda |= RH_A_PSM; 151 152 /* Set port power control mask bits, only 3 ports. */ 153 uhcrhdb |= (0x7<<17); 154 break; 155 default: 156 printk( KERN_ERR 157 "Invalid mode %d, set to non-power switch mode.\n", 158 mode ); 159 160 uhcrhda |= RH_A_NPS; 161 } 162 163 __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA); 164 __raw_writel(uhcrhdb, pxa_ohci->mmio_base + UHCRHDB); 165 return 0; 166 } 167 168 /*-------------------------------------------------------------------------*/ 169 170 static inline void pxa27x_setup_hc(struct pxa27x_ohci *pxa_ohci, 171 struct pxaohci_platform_data *inf) 172 { 173 uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR); 174 uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA); 175 176 if (inf->flags & ENABLE_PORT1) 177 uhchr &= ~UHCHR_SSEP1; 178 179 if (inf->flags & ENABLE_PORT2) 180 uhchr &= ~UHCHR_SSEP2; 181 182 if (inf->flags & ENABLE_PORT3) 183 uhchr &= ~UHCHR_SSEP3; 184 185 if (inf->flags & POWER_CONTROL_LOW) 186 uhchr |= UHCHR_PCPL; 187 188 if (inf->flags & POWER_SENSE_LOW) 189 uhchr |= UHCHR_PSPL; 190 191 if (inf->flags & NO_OC_PROTECTION) 192 uhcrhda |= UHCRHDA_NOCP; 193 else 194 uhcrhda &= ~UHCRHDA_NOCP; 195 196 if (inf->flags & OC_MODE_PERPORT) 197 uhcrhda |= UHCRHDA_OCPM; 198 else 199 uhcrhda &= ~UHCRHDA_OCPM; 200 201 if (inf->power_on_delay) { 202 uhcrhda &= ~UHCRHDA_POTPGT(0xff); 203 uhcrhda |= UHCRHDA_POTPGT(inf->power_on_delay / 2); 204 } 205 206 __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR); 207 __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA); 208 } 209 210 static inline void pxa27x_reset_hc(struct pxa27x_ohci *pxa_ohci) 211 { 212 uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR); 213 214 __raw_writel(uhchr | UHCHR_FHR, pxa_ohci->mmio_base + UHCHR); 215 udelay(11); 216 __raw_writel(uhchr & ~UHCHR_FHR, pxa_ohci->mmio_base + UHCHR); 217 } 218 219 #ifdef CONFIG_PXA27x 220 extern void pxa27x_clear_otgph(void); 221 #else 222 #define pxa27x_clear_otgph() do {} while (0) 223 #endif 224 225 static int pxa27x_start_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev) 226 { 227 int retval = 0; 228 struct pxaohci_platform_data *inf; 229 uint32_t uhchr; 230 struct usb_hcd *hcd = dev_get_drvdata(dev); 231 232 inf = dev_get_platdata(dev); 233 234 clk_prepare_enable(pxa_ohci->clk); 235 236 pxa27x_reset_hc(pxa_ohci); 237 238 uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) | UHCHR_FSBIR; 239 __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR); 240 241 while (__raw_readl(pxa_ohci->mmio_base + UHCHR) & UHCHR_FSBIR) 242 cpu_relax(); 243 244 pxa27x_setup_hc(pxa_ohci, inf); 245 246 if (inf->init) 247 retval = inf->init(dev); 248 249 if (retval < 0) 250 return retval; 251 252 if (cpu_is_pxa3xx()) 253 pxa3xx_u2d_start_hc(&hcd->self); 254 255 uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) & ~UHCHR_SSE; 256 __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR); 257 __raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, pxa_ohci->mmio_base + UHCHIE); 258 259 /* Clear any OTG Pin Hold */ 260 pxa27x_clear_otgph(); 261 return 0; 262 } 263 264 static void pxa27x_stop_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev) 265 { 266 struct pxaohci_platform_data *inf; 267 struct usb_hcd *hcd = dev_get_drvdata(dev); 268 uint32_t uhccoms; 269 270 inf = dev_get_platdata(dev); 271 272 if (cpu_is_pxa3xx()) 273 pxa3xx_u2d_stop_hc(&hcd->self); 274 275 if (inf->exit) 276 inf->exit(dev); 277 278 pxa27x_reset_hc(pxa_ohci); 279 280 /* Host Controller Reset */ 281 uhccoms = __raw_readl(pxa_ohci->mmio_base + UHCCOMS) | 0x01; 282 __raw_writel(uhccoms, pxa_ohci->mmio_base + UHCCOMS); 283 udelay(10); 284 285 clk_disable_unprepare(pxa_ohci->clk); 286 } 287 288 #ifdef CONFIG_OF 289 static const struct of_device_id pxa_ohci_dt_ids[] = { 290 { .compatible = "marvell,pxa-ohci" }, 291 { } 292 }; 293 294 MODULE_DEVICE_TABLE(of, pxa_ohci_dt_ids); 295 296 static int ohci_pxa_of_init(struct platform_device *pdev) 297 { 298 struct device_node *np = pdev->dev.of_node; 299 struct pxaohci_platform_data *pdata; 300 u32 tmp; 301 int ret; 302 303 if (!np) 304 return 0; 305 306 /* Right now device-tree probed devices don't get dma_mask set. 307 * Since shared usb code relies on it, set it here for now. 308 * Once we have dma capability bindings this can go away. 309 */ 310 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 311 if (ret) 312 return ret; 313 314 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 315 if (!pdata) 316 return -ENOMEM; 317 318 if (of_get_property(np, "marvell,enable-port1", NULL)) 319 pdata->flags |= ENABLE_PORT1; 320 if (of_get_property(np, "marvell,enable-port2", NULL)) 321 pdata->flags |= ENABLE_PORT2; 322 if (of_get_property(np, "marvell,enable-port3", NULL)) 323 pdata->flags |= ENABLE_PORT3; 324 if (of_get_property(np, "marvell,port-sense-low", NULL)) 325 pdata->flags |= POWER_SENSE_LOW; 326 if (of_get_property(np, "marvell,power-control-low", NULL)) 327 pdata->flags |= POWER_CONTROL_LOW; 328 if (of_get_property(np, "marvell,no-oc-protection", NULL)) 329 pdata->flags |= NO_OC_PROTECTION; 330 if (of_get_property(np, "marvell,oc-mode-perport", NULL)) 331 pdata->flags |= OC_MODE_PERPORT; 332 if (!of_property_read_u32(np, "marvell,power-on-delay", &tmp)) 333 pdata->power_on_delay = tmp; 334 if (!of_property_read_u32(np, "marvell,port-mode", &tmp)) 335 pdata->port_mode = tmp; 336 if (!of_property_read_u32(np, "marvell,power-budget", &tmp)) 337 pdata->power_budget = tmp; 338 339 pdev->dev.platform_data = pdata; 340 341 return 0; 342 } 343 #else 344 static int ohci_pxa_of_init(struct platform_device *pdev) 345 { 346 return 0; 347 } 348 #endif 349 350 /*-------------------------------------------------------------------------*/ 351 352 /* configure so an HC device and id are always provided */ 353 /* always called with process context; sleeping is OK */ 354 355 356 /** 357 * usb_hcd_pxa27x_probe - initialize pxa27x-based HCDs 358 * Context: !in_interrupt() 359 * 360 * Allocates basic resources for this USB host controller, and 361 * then invokes the start() method for the HCD associated with it 362 * through the hotplug entry's driver_data. 363 * 364 */ 365 int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device *pdev) 366 { 367 int retval, irq; 368 struct usb_hcd *hcd; 369 struct pxaohci_platform_data *inf; 370 struct pxa27x_ohci *pxa_ohci; 371 struct ohci_hcd *ohci; 372 struct resource *r; 373 struct clk *usb_clk; 374 375 retval = ohci_pxa_of_init(pdev); 376 if (retval) 377 return retval; 378 379 inf = dev_get_platdata(&pdev->dev); 380 381 if (!inf) 382 return -ENODEV; 383 384 irq = platform_get_irq(pdev, 0); 385 if (irq < 0) { 386 pr_err("no resource of IORESOURCE_IRQ"); 387 return -ENXIO; 388 } 389 390 usb_clk = clk_get(&pdev->dev, NULL); 391 if (IS_ERR(usb_clk)) 392 return PTR_ERR(usb_clk); 393 394 hcd = usb_create_hcd (driver, &pdev->dev, "pxa27x"); 395 if (!hcd) { 396 retval = -ENOMEM; 397 goto err0; 398 } 399 400 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 401 if (!r) { 402 pr_err("no resource of IORESOURCE_MEM"); 403 retval = -ENXIO; 404 goto err1; 405 } 406 407 hcd->rsrc_start = r->start; 408 hcd->rsrc_len = resource_size(r); 409 410 if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { 411 pr_debug("request_mem_region failed"); 412 retval = -EBUSY; 413 goto err1; 414 } 415 416 hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); 417 if (!hcd->regs) { 418 pr_debug("ioremap failed"); 419 retval = -ENOMEM; 420 goto err2; 421 } 422 423 /* initialize "struct pxa27x_ohci" */ 424 pxa_ohci = to_pxa27x_ohci(hcd); 425 pxa_ohci->clk = usb_clk; 426 pxa_ohci->mmio_base = (void __iomem *)hcd->regs; 427 428 retval = pxa27x_start_hc(pxa_ohci, &pdev->dev); 429 if (retval < 0) { 430 pr_debug("pxa27x_start_hc failed"); 431 goto err3; 432 } 433 434 /* Select Power Management Mode */ 435 pxa27x_ohci_select_pmm(pxa_ohci, inf->port_mode); 436 437 if (inf->power_budget) 438 hcd->power_budget = inf->power_budget; 439 440 /* The value of NDP in roothub_a is incorrect on this hardware */ 441 ohci = hcd_to_ohci(hcd); 442 ohci->num_ports = 3; 443 444 retval = usb_add_hcd(hcd, irq, 0); 445 if (retval == 0) 446 return retval; 447 448 pxa27x_stop_hc(pxa_ohci, &pdev->dev); 449 err3: 450 iounmap(hcd->regs); 451 err2: 452 release_mem_region(hcd->rsrc_start, hcd->rsrc_len); 453 err1: 454 usb_put_hcd(hcd); 455 err0: 456 clk_put(usb_clk); 457 return retval; 458 } 459 460 461 /* may be called without controller electrically present */ 462 /* may be called with controller, bus, and devices active */ 463 464 /** 465 * usb_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs 466 * @dev: USB Host Controller being removed 467 * Context: !in_interrupt() 468 * 469 * Reverses the effect of usb_hcd_pxa27x_probe(), first invoking 470 * the HCD's stop() method. It is always called from a thread 471 * context, normally "rmmod", "apmd", or something similar. 472 * 473 */ 474 void usb_hcd_pxa27x_remove (struct usb_hcd *hcd, struct platform_device *pdev) 475 { 476 struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd); 477 478 usb_remove_hcd(hcd); 479 pxa27x_stop_hc(pxa_ohci, &pdev->dev); 480 iounmap(hcd->regs); 481 release_mem_region(hcd->rsrc_start, hcd->rsrc_len); 482 clk_put(pxa_ohci->clk); 483 usb_put_hcd(hcd); 484 } 485 486 /*-------------------------------------------------------------------------*/ 487 488 static int ohci_hcd_pxa27x_drv_probe(struct platform_device *pdev) 489 { 490 pr_debug ("In ohci_hcd_pxa27x_drv_probe"); 491 492 if (usb_disabled()) 493 return -ENODEV; 494 495 return usb_hcd_pxa27x_probe(&ohci_pxa27x_hc_driver, pdev); 496 } 497 498 static int ohci_hcd_pxa27x_drv_remove(struct platform_device *pdev) 499 { 500 struct usb_hcd *hcd = platform_get_drvdata(pdev); 501 502 usb_hcd_pxa27x_remove(hcd, pdev); 503 return 0; 504 } 505 506 #ifdef CONFIG_PM 507 static int ohci_hcd_pxa27x_drv_suspend(struct device *dev) 508 { 509 struct usb_hcd *hcd = dev_get_drvdata(dev); 510 struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd); 511 struct ohci_hcd *ohci = hcd_to_ohci(hcd); 512 bool do_wakeup = device_may_wakeup(dev); 513 int ret; 514 515 516 if (time_before(jiffies, ohci->next_statechange)) 517 msleep(5); 518 ohci->next_statechange = jiffies; 519 520 ret = ohci_suspend(hcd, do_wakeup); 521 if (ret) 522 return ret; 523 524 pxa27x_stop_hc(pxa_ohci, dev); 525 return ret; 526 } 527 528 static int ohci_hcd_pxa27x_drv_resume(struct device *dev) 529 { 530 struct usb_hcd *hcd = dev_get_drvdata(dev); 531 struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd); 532 struct pxaohci_platform_data *inf = dev_get_platdata(dev); 533 struct ohci_hcd *ohci = hcd_to_ohci(hcd); 534 int status; 535 536 if (time_before(jiffies, ohci->next_statechange)) 537 msleep(5); 538 ohci->next_statechange = jiffies; 539 540 status = pxa27x_start_hc(pxa_ohci, dev); 541 if (status < 0) 542 return status; 543 544 /* Select Power Management Mode */ 545 pxa27x_ohci_select_pmm(pxa_ohci, inf->port_mode); 546 547 ohci_resume(hcd, false); 548 return 0; 549 } 550 551 static const struct dev_pm_ops ohci_hcd_pxa27x_pm_ops = { 552 .suspend = ohci_hcd_pxa27x_drv_suspend, 553 .resume = ohci_hcd_pxa27x_drv_resume, 554 }; 555 #endif 556 557 static struct platform_driver ohci_hcd_pxa27x_driver = { 558 .probe = ohci_hcd_pxa27x_drv_probe, 559 .remove = ohci_hcd_pxa27x_drv_remove, 560 .shutdown = usb_hcd_platform_shutdown, 561 .driver = { 562 .name = "pxa27x-ohci", 563 .owner = THIS_MODULE, 564 .of_match_table = of_match_ptr(pxa_ohci_dt_ids), 565 #ifdef CONFIG_PM 566 .pm = &ohci_hcd_pxa27x_pm_ops, 567 #endif 568 }, 569 }; 570 571 static const struct ohci_driver_overrides pxa27x_overrides __initconst = { 572 .extra_priv_size = sizeof(struct pxa27x_ohci), 573 }; 574 575 static int __init ohci_pxa27x_init(void) 576 { 577 if (usb_disabled()) 578 return -ENODEV; 579 580 pr_info("%s: " DRIVER_DESC "\n", hcd_name); 581 ohci_init_driver(&ohci_pxa27x_hc_driver, &pxa27x_overrides); 582 return platform_driver_register(&ohci_hcd_pxa27x_driver); 583 } 584 module_init(ohci_pxa27x_init); 585 586 static void __exit ohci_pxa27x_cleanup(void) 587 { 588 platform_driver_unregister(&ohci_hcd_pxa27x_driver); 589 } 590 module_exit(ohci_pxa27x_cleanup); 591 592 MODULE_DESCRIPTION(DRIVER_DESC); 593 MODULE_LICENSE("GPL"); 594 MODULE_ALIAS("platform:pxa27x-ohci"); 595