1 // SPDX-License-Identifier: GPL-1.0+ 2 /* 3 * OHCI HCD (Host Controller Driver) for USB. 4 * 5 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 6 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net> 7 * (C) Copyright 2002 Hewlett-Packard Company 8 * 9 * Bus Glue for pxa27x 10 * 11 * Written by Christopher Hoover <ch@hpl.hp.com> 12 * Based on fragments of previous driver by Russell King et al. 13 * 14 * Modified for LH7A404 from ohci-sa1111.c 15 * by Durgesh Pattamatta <pattamattad@sharpsec.com> 16 * 17 * Modified for pxa27x from ohci-lh7a404.c 18 * by Nick Bane <nick@cecomputing.co.uk> 26-8-2004 19 * 20 * This file is licenced under the GPL. 21 */ 22 23 #include <linux/clk.h> 24 #include <linux/device.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/io.h> 27 #include <linux/kernel.h> 28 #include <linux/module.h> 29 #include <linux/of_platform.h> 30 #include <linux/of_gpio.h> 31 #include <linux/platform_data/usb-ohci-pxa27x.h> 32 #include <linux/platform_data/pxa2xx_udc.h> 33 #include <linux/platform_device.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/signal.h> 36 #include <linux/usb.h> 37 #include <linux/usb/hcd.h> 38 #include <linux/usb/otg.h> 39 #include <linux/soc/pxa/cpu.h> 40 41 #include "ohci.h" 42 43 #define DRIVER_DESC "OHCI PXA27x/PXA3x driver" 44 45 /* 46 * UHC: USB Host Controller (OHCI-like) register definitions 47 */ 48 #define UHCREV (0x0000) /* UHC HCI Spec Revision */ 49 #define UHCHCON (0x0004) /* UHC Host Control Register */ 50 #define UHCCOMS (0x0008) /* UHC Command Status Register */ 51 #define UHCINTS (0x000C) /* UHC Interrupt Status Register */ 52 #define UHCINTE (0x0010) /* UHC Interrupt Enable */ 53 #define UHCINTD (0x0014) /* UHC Interrupt Disable */ 54 #define UHCHCCA (0x0018) /* UHC Host Controller Comm. Area */ 55 #define UHCPCED (0x001C) /* UHC Period Current Endpt Descr */ 56 #define UHCCHED (0x0020) /* UHC Control Head Endpt Descr */ 57 #define UHCCCED (0x0024) /* UHC Control Current Endpt Descr */ 58 #define UHCBHED (0x0028) /* UHC Bulk Head Endpt Descr */ 59 #define UHCBCED (0x002C) /* UHC Bulk Current Endpt Descr */ 60 #define UHCDHEAD (0x0030) /* UHC Done Head */ 61 #define UHCFMI (0x0034) /* UHC Frame Interval */ 62 #define UHCFMR (0x0038) /* UHC Frame Remaining */ 63 #define UHCFMN (0x003C) /* UHC Frame Number */ 64 #define UHCPERS (0x0040) /* UHC Periodic Start */ 65 #define UHCLS (0x0044) /* UHC Low Speed Threshold */ 66 67 #define UHCRHDA (0x0048) /* UHC Root Hub Descriptor A */ 68 #define UHCRHDA_NOCP (1 << 12) /* No over current protection */ 69 #define UHCRHDA_OCPM (1 << 11) /* Over Current Protection Mode */ 70 #define UHCRHDA_POTPGT(x) \ 71 (((x) & 0xff) << 24) /* Power On To Power Good Time */ 72 73 #define UHCRHDB (0x004C) /* UHC Root Hub Descriptor B */ 74 #define UHCRHS (0x0050) /* UHC Root Hub Status */ 75 #define UHCRHPS1 (0x0054) /* UHC Root Hub Port 1 Status */ 76 #define UHCRHPS2 (0x0058) /* UHC Root Hub Port 2 Status */ 77 #define UHCRHPS3 (0x005C) /* UHC Root Hub Port 3 Status */ 78 79 #define UHCSTAT (0x0060) /* UHC Status Register */ 80 #define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */ 81 #define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/ 82 #define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/ 83 #define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */ 84 #define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */ 85 #define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */ 86 #define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */ 87 #define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */ 88 #define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */ 89 90 #define UHCHR (0x0064) /* UHC Reset Register */ 91 #define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */ 92 #define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */ 93 #define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */ 94 #define UHCHR_PCPL (1 << 7) /* Power control polarity low */ 95 #define UHCHR_PSPL (1 << 6) /* Power sense polarity low */ 96 #define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */ 97 #define UHCHR_UIT (1 << 4) /* USB Interrupt Test */ 98 #define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */ 99 #define UHCHR_CGR (1 << 2) /* Clock Generation Reset */ 100 #define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */ 101 #define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */ 102 103 #define UHCHIE (0x0068) /* UHC Interrupt Enable Register*/ 104 #define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */ 105 #define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */ 106 #define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */ 107 #define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */ 108 #define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort 109 Interrupt Enable*/ 110 #define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */ 111 #define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */ 112 113 #define UHCHIT (0x006C) /* UHC Interrupt Test register */ 114 115 #define PXA_UHC_MAX_PORTNUM 3 116 117 static struct hc_driver __read_mostly ohci_pxa27x_hc_driver; 118 119 struct pxa27x_ohci { 120 struct clk *clk; 121 void __iomem *mmio_base; 122 struct regulator *vbus[3]; 123 bool vbus_enabled[3]; 124 }; 125 126 #define to_pxa27x_ohci(hcd) (struct pxa27x_ohci *)(hcd_to_ohci(hcd)->priv) 127 128 /* 129 PMM_NPS_MODE -- PMM Non-power switching mode 130 Ports are powered continuously. 131 132 PMM_GLOBAL_MODE -- PMM global switching mode 133 All ports are powered at the same time. 134 135 PMM_PERPORT_MODE -- PMM per port switching mode 136 Ports are powered individually. 137 */ 138 static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *pxa_ohci, int mode) 139 { 140 uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA); 141 uint32_t uhcrhdb = __raw_readl(pxa_ohci->mmio_base + UHCRHDB); 142 143 switch (mode) { 144 case PMM_NPS_MODE: 145 uhcrhda |= RH_A_NPS; 146 break; 147 case PMM_GLOBAL_MODE: 148 uhcrhda &= ~(RH_A_NPS | RH_A_PSM); 149 break; 150 case PMM_PERPORT_MODE: 151 uhcrhda &= ~(RH_A_NPS); 152 uhcrhda |= RH_A_PSM; 153 154 /* Set port power control mask bits, only 3 ports. */ 155 uhcrhdb |= (0x7<<17); 156 break; 157 default: 158 printk( KERN_ERR 159 "Invalid mode %d, set to non-power switch mode.\n", 160 mode ); 161 162 uhcrhda |= RH_A_NPS; 163 } 164 165 __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA); 166 __raw_writel(uhcrhdb, pxa_ohci->mmio_base + UHCRHDB); 167 return 0; 168 } 169 170 static int pxa27x_ohci_set_vbus_power(struct pxa27x_ohci *pxa_ohci, 171 unsigned int port, bool enable) 172 { 173 struct regulator *vbus = pxa_ohci->vbus[port]; 174 int ret = 0; 175 176 if (IS_ERR_OR_NULL(vbus)) 177 return 0; 178 179 if (enable && !pxa_ohci->vbus_enabled[port]) 180 ret = regulator_enable(vbus); 181 else if (!enable && pxa_ohci->vbus_enabled[port]) 182 ret = regulator_disable(vbus); 183 184 if (ret < 0) 185 return ret; 186 187 pxa_ohci->vbus_enabled[port] = enable; 188 189 return 0; 190 } 191 192 static int pxa27x_ohci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 193 u16 wIndex, char *buf, u16 wLength) 194 { 195 struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd); 196 int ret; 197 198 switch (typeReq) { 199 case SetPortFeature: 200 case ClearPortFeature: 201 if (!wIndex || wIndex > 3) 202 return -EPIPE; 203 204 if (wValue != USB_PORT_FEAT_POWER) 205 break; 206 207 ret = pxa27x_ohci_set_vbus_power(pxa_ohci, wIndex - 1, 208 typeReq == SetPortFeature); 209 if (ret) 210 return ret; 211 break; 212 } 213 214 return ohci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength); 215 } 216 /*-------------------------------------------------------------------------*/ 217 218 static inline void pxa27x_setup_hc(struct pxa27x_ohci *pxa_ohci, 219 struct pxaohci_platform_data *inf) 220 { 221 uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR); 222 uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA); 223 224 if (inf->flags & ENABLE_PORT1) 225 uhchr &= ~UHCHR_SSEP1; 226 227 if (inf->flags & ENABLE_PORT2) 228 uhchr &= ~UHCHR_SSEP2; 229 230 if (inf->flags & ENABLE_PORT3) 231 uhchr &= ~UHCHR_SSEP3; 232 233 if (inf->flags & POWER_CONTROL_LOW) 234 uhchr |= UHCHR_PCPL; 235 236 if (inf->flags & POWER_SENSE_LOW) 237 uhchr |= UHCHR_PSPL; 238 239 if (inf->flags & NO_OC_PROTECTION) 240 uhcrhda |= UHCRHDA_NOCP; 241 else 242 uhcrhda &= ~UHCRHDA_NOCP; 243 244 if (inf->flags & OC_MODE_PERPORT) 245 uhcrhda |= UHCRHDA_OCPM; 246 else 247 uhcrhda &= ~UHCRHDA_OCPM; 248 249 if (inf->power_on_delay) { 250 uhcrhda &= ~UHCRHDA_POTPGT(0xff); 251 uhcrhda |= UHCRHDA_POTPGT(inf->power_on_delay / 2); 252 } 253 254 __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR); 255 __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA); 256 } 257 258 static inline void pxa27x_reset_hc(struct pxa27x_ohci *pxa_ohci) 259 { 260 uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR); 261 262 __raw_writel(uhchr | UHCHR_FHR, pxa_ohci->mmio_base + UHCHR); 263 udelay(11); 264 __raw_writel(uhchr & ~UHCHR_FHR, pxa_ohci->mmio_base + UHCHR); 265 } 266 267 static int pxa27x_start_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev) 268 { 269 int retval; 270 struct pxaohci_platform_data *inf; 271 uint32_t uhchr; 272 273 inf = dev_get_platdata(dev); 274 275 retval = clk_prepare_enable(pxa_ohci->clk); 276 if (retval) 277 return retval; 278 279 pxa27x_reset_hc(pxa_ohci); 280 281 uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) | UHCHR_FSBIR; 282 __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR); 283 284 while (__raw_readl(pxa_ohci->mmio_base + UHCHR) & UHCHR_FSBIR) 285 cpu_relax(); 286 287 pxa27x_setup_hc(pxa_ohci, inf); 288 289 if (inf->init) 290 retval = inf->init(dev); 291 292 if (retval < 0) { 293 clk_disable_unprepare(pxa_ohci->clk); 294 return retval; 295 } 296 297 uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) & ~UHCHR_SSE; 298 __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR); 299 __raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, pxa_ohci->mmio_base + UHCHIE); 300 301 /* Clear any OTG Pin Hold */ 302 pxa27x_clear_otgph(); 303 return 0; 304 } 305 306 static void pxa27x_stop_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev) 307 { 308 struct pxaohci_platform_data *inf; 309 uint32_t uhccoms; 310 311 inf = dev_get_platdata(dev); 312 313 if (inf->exit) 314 inf->exit(dev); 315 316 pxa27x_reset_hc(pxa_ohci); 317 318 /* Host Controller Reset */ 319 uhccoms = __raw_readl(pxa_ohci->mmio_base + UHCCOMS) | 0x01; 320 __raw_writel(uhccoms, pxa_ohci->mmio_base + UHCCOMS); 321 udelay(10); 322 323 clk_disable_unprepare(pxa_ohci->clk); 324 } 325 326 #ifdef CONFIG_OF 327 static const struct of_device_id pxa_ohci_dt_ids[] = { 328 { .compatible = "marvell,pxa-ohci" }, 329 { } 330 }; 331 332 MODULE_DEVICE_TABLE(of, pxa_ohci_dt_ids); 333 334 static int ohci_pxa_of_init(struct platform_device *pdev) 335 { 336 struct device_node *np = pdev->dev.of_node; 337 struct pxaohci_platform_data *pdata; 338 u32 tmp; 339 int ret; 340 341 if (!np) 342 return 0; 343 344 /* Right now device-tree probed devices don't get dma_mask set. 345 * Since shared usb code relies on it, set it here for now. 346 * Once we have dma capability bindings this can go away. 347 */ 348 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 349 if (ret) 350 return ret; 351 352 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 353 if (!pdata) 354 return -ENOMEM; 355 356 if (of_property_read_bool(np, "marvell,enable-port1")) 357 pdata->flags |= ENABLE_PORT1; 358 if (of_property_read_bool(np, "marvell,enable-port2")) 359 pdata->flags |= ENABLE_PORT2; 360 if (of_property_read_bool(np, "marvell,enable-port3")) 361 pdata->flags |= ENABLE_PORT3; 362 if (of_property_read_bool(np, "marvell,port-sense-low")) 363 pdata->flags |= POWER_SENSE_LOW; 364 if (of_property_read_bool(np, "marvell,power-control-low")) 365 pdata->flags |= POWER_CONTROL_LOW; 366 if (of_property_read_bool(np, "marvell,no-oc-protection")) 367 pdata->flags |= NO_OC_PROTECTION; 368 if (of_property_read_bool(np, "marvell,oc-mode-perport")) 369 pdata->flags |= OC_MODE_PERPORT; 370 if (!of_property_read_u32(np, "marvell,power-on-delay", &tmp)) 371 pdata->power_on_delay = tmp; 372 if (!of_property_read_u32(np, "marvell,port-mode", &tmp)) 373 pdata->port_mode = tmp; 374 if (!of_property_read_u32(np, "marvell,power-budget", &tmp)) 375 pdata->power_budget = tmp; 376 377 pdev->dev.platform_data = pdata; 378 379 return 0; 380 } 381 #else 382 static int ohci_pxa_of_init(struct platform_device *pdev) 383 { 384 return 0; 385 } 386 #endif 387 388 /*-------------------------------------------------------------------------*/ 389 390 /* configure so an HC device and id are always provided */ 391 /* always called with process context; sleeping is OK */ 392 393 394 /** 395 * ohci_hcd_pxa27x_probe - initialize pxa27x-based HCDs 396 * @pdev: USB Host controller to probe 397 * 398 * Context: task context, might sleep 399 * 400 * Allocates basic resources for this USB host controller, and 401 * then invokes the start() method for the HCD associated with it 402 * through the hotplug entry's driver_data. 403 */ 404 static int ohci_hcd_pxa27x_probe(struct platform_device *pdev) 405 { 406 int retval, irq; 407 struct usb_hcd *hcd; 408 struct pxaohci_platform_data *inf; 409 struct pxa27x_ohci *pxa_ohci; 410 struct ohci_hcd *ohci; 411 struct resource *r; 412 struct clk *usb_clk; 413 unsigned int i; 414 415 retval = ohci_pxa_of_init(pdev); 416 if (retval) 417 return retval; 418 419 inf = dev_get_platdata(&pdev->dev); 420 421 if (!inf) 422 return -ENODEV; 423 424 irq = platform_get_irq(pdev, 0); 425 if (irq < 0) { 426 pr_err("no resource of IORESOURCE_IRQ"); 427 return irq; 428 } 429 430 usb_clk = devm_clk_get(&pdev->dev, NULL); 431 if (IS_ERR(usb_clk)) 432 return PTR_ERR(usb_clk); 433 434 hcd = usb_create_hcd(&ohci_pxa27x_hc_driver, &pdev->dev, "pxa27x"); 435 if (!hcd) 436 return -ENOMEM; 437 438 hcd->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &r); 439 if (IS_ERR(hcd->regs)) { 440 retval = PTR_ERR(hcd->regs); 441 goto err; 442 } 443 hcd->rsrc_start = r->start; 444 hcd->rsrc_len = resource_size(r); 445 446 /* initialize "struct pxa27x_ohci" */ 447 pxa_ohci = to_pxa27x_ohci(hcd); 448 pxa_ohci->clk = usb_clk; 449 pxa_ohci->mmio_base = (void __iomem *)hcd->regs; 450 451 for (i = 0; i < 3; ++i) { 452 char name[6]; 453 454 if (!(inf->flags & (ENABLE_PORT1 << i))) 455 continue; 456 457 sprintf(name, "vbus%u", i + 1); 458 pxa_ohci->vbus[i] = devm_regulator_get(&pdev->dev, name); 459 } 460 461 retval = pxa27x_start_hc(pxa_ohci, &pdev->dev); 462 if (retval < 0) { 463 pr_debug("pxa27x_start_hc failed"); 464 goto err; 465 } 466 467 /* Select Power Management Mode */ 468 pxa27x_ohci_select_pmm(pxa_ohci, inf->port_mode); 469 470 if (inf->power_budget) 471 hcd->power_budget = inf->power_budget; 472 473 /* The value of NDP in roothub_a is incorrect on this hardware */ 474 ohci = hcd_to_ohci(hcd); 475 ohci->num_ports = 3; 476 477 retval = usb_add_hcd(hcd, irq, 0); 478 if (retval == 0) { 479 device_wakeup_enable(hcd->self.controller); 480 return retval; 481 } 482 483 pxa27x_stop_hc(pxa_ohci, &pdev->dev); 484 err: 485 usb_put_hcd(hcd); 486 return retval; 487 } 488 489 490 /* may be called without controller electrically present */ 491 /* may be called with controller, bus, and devices active */ 492 493 /** 494 * ohci_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs 495 * @pdev: USB Host Controller being removed 496 * 497 * Context: task context, might sleep 498 * 499 * Reverses the effect of ohci_hcd_pxa27x_probe(), first invoking 500 * the HCD's stop() method. It is always called from a thread 501 * context, normally "rmmod", "apmd", or something similar. 502 */ 503 static void ohci_hcd_pxa27x_remove(struct platform_device *pdev) 504 { 505 struct usb_hcd *hcd = platform_get_drvdata(pdev); 506 struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd); 507 unsigned int i; 508 509 usb_remove_hcd(hcd); 510 pxa27x_stop_hc(pxa_ohci, &pdev->dev); 511 512 for (i = 0; i < 3; ++i) 513 pxa27x_ohci_set_vbus_power(pxa_ohci, i, false); 514 515 usb_put_hcd(hcd); 516 } 517 518 /*-------------------------------------------------------------------------*/ 519 520 #ifdef CONFIG_PM 521 static int ohci_hcd_pxa27x_drv_suspend(struct device *dev) 522 { 523 struct usb_hcd *hcd = dev_get_drvdata(dev); 524 struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd); 525 struct ohci_hcd *ohci = hcd_to_ohci(hcd); 526 bool do_wakeup = device_may_wakeup(dev); 527 int ret; 528 529 530 if (time_before(jiffies, ohci->next_statechange)) 531 msleep(5); 532 ohci->next_statechange = jiffies; 533 534 ret = ohci_suspend(hcd, do_wakeup); 535 if (ret) 536 return ret; 537 538 pxa27x_stop_hc(pxa_ohci, dev); 539 return ret; 540 } 541 542 static int ohci_hcd_pxa27x_drv_resume(struct device *dev) 543 { 544 struct usb_hcd *hcd = dev_get_drvdata(dev); 545 struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd); 546 struct pxaohci_platform_data *inf = dev_get_platdata(dev); 547 struct ohci_hcd *ohci = hcd_to_ohci(hcd); 548 int status; 549 550 if (time_before(jiffies, ohci->next_statechange)) 551 msleep(5); 552 ohci->next_statechange = jiffies; 553 554 status = pxa27x_start_hc(pxa_ohci, dev); 555 if (status < 0) 556 return status; 557 558 /* Select Power Management Mode */ 559 pxa27x_ohci_select_pmm(pxa_ohci, inf->port_mode); 560 561 ohci_resume(hcd, false); 562 return 0; 563 } 564 565 static const struct dev_pm_ops ohci_hcd_pxa27x_pm_ops = { 566 .suspend = ohci_hcd_pxa27x_drv_suspend, 567 .resume = ohci_hcd_pxa27x_drv_resume, 568 }; 569 #endif 570 571 static struct platform_driver ohci_hcd_pxa27x_driver = { 572 .probe = ohci_hcd_pxa27x_probe, 573 .remove_new = ohci_hcd_pxa27x_remove, 574 .shutdown = usb_hcd_platform_shutdown, 575 .driver = { 576 .name = "pxa27x-ohci", 577 .of_match_table = of_match_ptr(pxa_ohci_dt_ids), 578 #ifdef CONFIG_PM 579 .pm = &ohci_hcd_pxa27x_pm_ops, 580 #endif 581 }, 582 }; 583 584 static const struct ohci_driver_overrides pxa27x_overrides __initconst = { 585 .extra_priv_size = sizeof(struct pxa27x_ohci), 586 }; 587 588 static int __init ohci_pxa27x_init(void) 589 { 590 if (usb_disabled()) 591 return -ENODEV; 592 593 ohci_init_driver(&ohci_pxa27x_hc_driver, &pxa27x_overrides); 594 ohci_pxa27x_hc_driver.hub_control = pxa27x_ohci_hub_control; 595 596 return platform_driver_register(&ohci_hcd_pxa27x_driver); 597 } 598 module_init(ohci_pxa27x_init); 599 600 static void __exit ohci_pxa27x_cleanup(void) 601 { 602 platform_driver_unregister(&ohci_hcd_pxa27x_driver); 603 } 604 module_exit(ohci_pxa27x_cleanup); 605 606 MODULE_DESCRIPTION(DRIVER_DESC); 607 MODULE_LICENSE("GPL"); 608 MODULE_ALIAS("platform:pxa27x-ohci"); 609