1 /* 2 * OHCI HCD (Host Controller Driver) for USB. 3 * 4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net> 6 * 7 * [ Initialisation is based on Linus' ] 8 * [ uhci code and gregs ohci fragments ] 9 * [ (C) Copyright 1999 Linus Torvalds ] 10 * [ (C) Copyright 1999 Gregory P. Smith] 11 * 12 * PCI Bus Glue 13 * 14 * This file is licenced under the GPL. 15 */ 16 17 #ifndef CONFIG_PCI 18 #error "This file is PCI bus glue. CONFIG_PCI must be defined." 19 #endif 20 21 #include <linux/pci.h> 22 #include <linux/io.h> 23 24 25 /*-------------------------------------------------------------------------*/ 26 27 static int broken_suspend(struct usb_hcd *hcd) 28 { 29 device_init_wakeup(&hcd->self.root_hub->dev, 0); 30 return 0; 31 } 32 33 /* AMD 756, for most chips (early revs), corrupts register 34 * values on read ... so enable the vendor workaround. 35 */ 36 static int ohci_quirk_amd756(struct usb_hcd *hcd) 37 { 38 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 39 40 ohci->flags = OHCI_QUIRK_AMD756; 41 ohci_dbg (ohci, "AMD756 erratum 4 workaround\n"); 42 43 /* also erratum 10 (suspend/resume issues) */ 44 return broken_suspend(hcd); 45 } 46 47 /* Apple's OHCI driver has a lot of bizarre workarounds 48 * for this chip. Evidently control and bulk lists 49 * can get confused. (B&W G3 models, and ...) 50 */ 51 static int ohci_quirk_opti(struct usb_hcd *hcd) 52 { 53 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 54 55 ohci_dbg (ohci, "WARNING: OPTi workarounds unavailable\n"); 56 57 return 0; 58 } 59 60 /* Check for NSC87560. We have to look at the bridge (fn1) to 61 * identify the USB (fn2). This quirk might apply to more or 62 * even all NSC stuff. 63 */ 64 static int ohci_quirk_ns(struct usb_hcd *hcd) 65 { 66 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 67 struct pci_dev *b; 68 69 b = pci_get_slot (pdev->bus, PCI_DEVFN (PCI_SLOT (pdev->devfn), 1)); 70 if (b && b->device == PCI_DEVICE_ID_NS_87560_LIO 71 && b->vendor == PCI_VENDOR_ID_NS) { 72 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 73 74 ohci->flags |= OHCI_QUIRK_SUPERIO; 75 ohci_dbg (ohci, "Using NSC SuperIO setup\n"); 76 } 77 pci_dev_put(b); 78 79 return 0; 80 } 81 82 /* Check for Compaq's ZFMicro chipset, which needs short 83 * delays before control or bulk queues get re-activated 84 * in finish_unlinks() 85 */ 86 static int ohci_quirk_zfmicro(struct usb_hcd *hcd) 87 { 88 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 89 90 ohci->flags |= OHCI_QUIRK_ZFMICRO; 91 ohci_dbg(ohci, "enabled Compaq ZFMicro chipset quirks\n"); 92 93 return 0; 94 } 95 96 /* Check for Toshiba SCC OHCI which has big endian registers 97 * and little endian in memory data structures 98 */ 99 static int ohci_quirk_toshiba_scc(struct usb_hcd *hcd) 100 { 101 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 102 103 /* That chip is only present in the southbridge of some 104 * cell based platforms which are supposed to select 105 * CONFIG_USB_OHCI_BIG_ENDIAN_MMIO. We verify here if 106 * that was the case though. 107 */ 108 #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO 109 ohci->flags |= OHCI_QUIRK_BE_MMIO; 110 ohci_dbg (ohci, "enabled big endian Toshiba quirk\n"); 111 return 0; 112 #else 113 ohci_err (ohci, "unsupported big endian Toshiba quirk\n"); 114 return -ENXIO; 115 #endif 116 } 117 118 /* Check for NEC chip and apply quirk for allegedly lost interrupts. 119 */ 120 121 static void ohci_quirk_nec_worker(struct work_struct *work) 122 { 123 struct ohci_hcd *ohci = container_of(work, struct ohci_hcd, nec_work); 124 int status; 125 126 status = ohci_init(ohci); 127 if (status != 0) { 128 ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n", 129 "ohci_init", status); 130 return; 131 } 132 133 status = ohci_restart(ohci); 134 if (status != 0) 135 ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n", 136 "ohci_restart", status); 137 } 138 139 static int ohci_quirk_nec(struct usb_hcd *hcd) 140 { 141 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 142 143 ohci->flags |= OHCI_QUIRK_NEC; 144 INIT_WORK(&ohci->nec_work, ohci_quirk_nec_worker); 145 ohci_dbg (ohci, "enabled NEC chipset lost interrupt quirk\n"); 146 147 return 0; 148 } 149 150 static int ohci_quirk_amd700(struct usb_hcd *hcd) 151 { 152 struct ohci_hcd *ohci = hcd_to_ohci(hcd); 153 struct pci_dev *amd_smbus_dev; 154 u8 rev; 155 156 if (usb_amd_find_chipset_info()) 157 ohci->flags |= OHCI_QUIRK_AMD_PLL; 158 159 amd_smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 160 PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL); 161 if (!amd_smbus_dev) 162 return 0; 163 164 rev = amd_smbus_dev->revision; 165 166 /* SB800 needs pre-fetch fix */ 167 if ((rev >= 0x40) && (rev <= 0x4f)) { 168 ohci->flags |= OHCI_QUIRK_AMD_PREFETCH; 169 ohci_dbg(ohci, "enabled AMD prefetch quirk\n"); 170 } 171 172 pci_dev_put(amd_smbus_dev); 173 amd_smbus_dev = NULL; 174 175 return 0; 176 } 177 178 static void sb800_prefetch(struct ohci_hcd *ohci, int on) 179 { 180 struct pci_dev *pdev; 181 u16 misc; 182 183 pdev = to_pci_dev(ohci_to_hcd(ohci)->self.controller); 184 pci_read_config_word(pdev, 0x50, &misc); 185 if (on == 0) 186 pci_write_config_word(pdev, 0x50, misc & 0xfcff); 187 else 188 pci_write_config_word(pdev, 0x50, misc | 0x0300); 189 } 190 191 /* List of quirks for OHCI */ 192 static const struct pci_device_id ohci_pci_quirks[] = { 193 { 194 PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x740c), 195 .driver_data = (unsigned long)ohci_quirk_amd756, 196 }, 197 { 198 PCI_DEVICE(PCI_VENDOR_ID_OPTI, 0xc861), 199 .driver_data = (unsigned long)ohci_quirk_opti, 200 }, 201 { 202 PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_ANY_ID), 203 .driver_data = (unsigned long)ohci_quirk_ns, 204 }, 205 { 206 PCI_DEVICE(PCI_VENDOR_ID_COMPAQ, 0xa0f8), 207 .driver_data = (unsigned long)ohci_quirk_zfmicro, 208 }, 209 { 210 PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, 0x01b6), 211 .driver_data = (unsigned long)ohci_quirk_toshiba_scc, 212 }, 213 { 214 PCI_DEVICE(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB), 215 .driver_data = (unsigned long)ohci_quirk_nec, 216 }, 217 { 218 /* Toshiba portege 4000 */ 219 .vendor = PCI_VENDOR_ID_AL, 220 .device = 0x5237, 221 .subvendor = PCI_VENDOR_ID_TOSHIBA, 222 .subdevice = 0x0004, 223 .driver_data = (unsigned long) broken_suspend, 224 }, 225 { 226 PCI_DEVICE(PCI_VENDOR_ID_ITE, 0x8152), 227 .driver_data = (unsigned long) broken_suspend, 228 }, 229 { 230 PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4397), 231 .driver_data = (unsigned long)ohci_quirk_amd700, 232 }, 233 { 234 PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4398), 235 .driver_data = (unsigned long)ohci_quirk_amd700, 236 }, 237 { 238 PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4399), 239 .driver_data = (unsigned long)ohci_quirk_amd700, 240 }, 241 242 /* FIXME for some of the early AMD 760 southbridges, OHCI 243 * won't work at all. blacklist them. 244 */ 245 246 {}, 247 }; 248 249 static int ohci_pci_reset (struct usb_hcd *hcd) 250 { 251 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 252 int ret = 0; 253 254 if (hcd->self.controller) { 255 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 256 const struct pci_device_id *quirk_id; 257 258 quirk_id = pci_match_id(ohci_pci_quirks, pdev); 259 if (quirk_id != NULL) { 260 int (*quirk)(struct usb_hcd *ohci); 261 quirk = (void *)quirk_id->driver_data; 262 ret = quirk(hcd); 263 } 264 } 265 if (ret == 0) { 266 ohci_hcd_init (ohci); 267 return ohci_init (ohci); 268 } 269 return ret; 270 } 271 272 273 static int ohci_pci_start (struct usb_hcd *hcd) 274 { 275 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 276 int ret; 277 278 #ifdef CONFIG_PM /* avoid warnings about unused pdev */ 279 if (hcd->self.controller) { 280 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 281 282 /* RWC may not be set for add-in PCI cards, since boot 283 * firmware probably ignored them. This transfers PCI 284 * PM wakeup capabilities. 285 */ 286 if (device_can_wakeup(&pdev->dev)) 287 ohci->hc_control |= OHCI_CTRL_RWC; 288 } 289 #endif /* CONFIG_PM */ 290 291 ret = ohci_run (ohci); 292 if (ret < 0) { 293 ohci_err (ohci, "can't start\n"); 294 ohci_stop (hcd); 295 } 296 return ret; 297 } 298 299 300 /*-------------------------------------------------------------------------*/ 301 302 static const struct hc_driver ohci_pci_hc_driver = { 303 .description = hcd_name, 304 .product_desc = "OHCI Host Controller", 305 .hcd_priv_size = sizeof(struct ohci_hcd), 306 307 /* 308 * generic hardware linkage 309 */ 310 .irq = ohci_irq, 311 .flags = HCD_MEMORY | HCD_USB11, 312 313 /* 314 * basic lifecycle operations 315 */ 316 .reset = ohci_pci_reset, 317 .start = ohci_pci_start, 318 .stop = ohci_stop, 319 .shutdown = ohci_shutdown, 320 321 #ifdef CONFIG_PM 322 .pci_suspend = ohci_suspend, 323 .pci_resume = ohci_resume, 324 #endif 325 326 /* 327 * managing i/o requests and associated device resources 328 */ 329 .urb_enqueue = ohci_urb_enqueue, 330 .urb_dequeue = ohci_urb_dequeue, 331 .endpoint_disable = ohci_endpoint_disable, 332 333 /* 334 * scheduling support 335 */ 336 .get_frame_number = ohci_get_frame, 337 338 /* 339 * root hub support 340 */ 341 .hub_status_data = ohci_hub_status_data, 342 .hub_control = ohci_hub_control, 343 #ifdef CONFIG_PM 344 .bus_suspend = ohci_bus_suspend, 345 .bus_resume = ohci_bus_resume, 346 #endif 347 .start_port_reset = ohci_start_port_reset, 348 }; 349 350 /*-------------------------------------------------------------------------*/ 351 352 353 static const struct pci_device_id pci_ids [] = { { 354 /* handle any USB OHCI controller */ 355 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_OHCI, ~0), 356 .driver_data = (unsigned long) &ohci_pci_hc_driver, 357 }, { 358 /* The device in the ConneXT I/O hub has no class reg */ 359 PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_OHCI), 360 .driver_data = (unsigned long) &ohci_pci_hc_driver, 361 }, { /* end: all zeroes */ } 362 }; 363 MODULE_DEVICE_TABLE (pci, pci_ids); 364 365 /* pci driver glue; this is a "new style" PCI driver module */ 366 static struct pci_driver ohci_pci_driver = { 367 .name = (char *) hcd_name, 368 .id_table = pci_ids, 369 370 .probe = usb_hcd_pci_probe, 371 .remove = usb_hcd_pci_remove, 372 .shutdown = usb_hcd_pci_shutdown, 373 374 #ifdef CONFIG_PM_SLEEP 375 .driver = { 376 .pm = &usb_hcd_pci_pm_ops 377 }, 378 #endif 379 }; 380