1 /* 2 * OHCI HCD (Host Controller Driver) for USB. 3 * 4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net> 6 * 7 * [ Initialisation is based on Linus' ] 8 * [ uhci code and gregs ohci fragments ] 9 * [ (C) Copyright 1999 Linus Torvalds ] 10 * [ (C) Copyright 1999 Gregory P. Smith] 11 * 12 * PCI Bus Glue 13 * 14 * This file is licenced under the GPL. 15 */ 16 17 #ifndef CONFIG_PCI 18 #error "This file is PCI bus glue. CONFIG_PCI must be defined." 19 #endif 20 21 #include <linux/pci.h> 22 #include <linux/io.h> 23 24 25 /*-------------------------------------------------------------------------*/ 26 27 static int broken_suspend(struct usb_hcd *hcd) 28 { 29 device_init_wakeup(&hcd->self.root_hub->dev, 0); 30 return 0; 31 } 32 33 /* AMD 756, for most chips (early revs), corrupts register 34 * values on read ... so enable the vendor workaround. 35 */ 36 static int ohci_quirk_amd756(struct usb_hcd *hcd) 37 { 38 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 39 40 ohci->flags = OHCI_QUIRK_AMD756; 41 ohci_dbg (ohci, "AMD756 erratum 4 workaround\n"); 42 43 /* also erratum 10 (suspend/resume issues) */ 44 return broken_suspend(hcd); 45 } 46 47 /* Apple's OHCI driver has a lot of bizarre workarounds 48 * for this chip. Evidently control and bulk lists 49 * can get confused. (B&W G3 models, and ...) 50 */ 51 static int ohci_quirk_opti(struct usb_hcd *hcd) 52 { 53 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 54 55 ohci_dbg (ohci, "WARNING: OPTi workarounds unavailable\n"); 56 57 return 0; 58 } 59 60 /* Check for NSC87560. We have to look at the bridge (fn1) to 61 * identify the USB (fn2). This quirk might apply to more or 62 * even all NSC stuff. 63 */ 64 static int ohci_quirk_ns(struct usb_hcd *hcd) 65 { 66 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 67 struct pci_dev *b; 68 69 b = pci_get_slot (pdev->bus, PCI_DEVFN (PCI_SLOT (pdev->devfn), 1)); 70 if (b && b->device == PCI_DEVICE_ID_NS_87560_LIO 71 && b->vendor == PCI_VENDOR_ID_NS) { 72 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 73 74 ohci->flags |= OHCI_QUIRK_SUPERIO; 75 ohci_dbg (ohci, "Using NSC SuperIO setup\n"); 76 } 77 pci_dev_put(b); 78 79 return 0; 80 } 81 82 /* Check for Compaq's ZFMicro chipset, which needs short 83 * delays before control or bulk queues get re-activated 84 * in finish_unlinks() 85 */ 86 static int ohci_quirk_zfmicro(struct usb_hcd *hcd) 87 { 88 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 89 90 ohci->flags |= OHCI_QUIRK_ZFMICRO; 91 ohci_dbg(ohci, "enabled Compaq ZFMicro chipset quirks\n"); 92 93 return 0; 94 } 95 96 /* Check for Toshiba SCC OHCI which has big endian registers 97 * and little endian in memory data structures 98 */ 99 static int ohci_quirk_toshiba_scc(struct usb_hcd *hcd) 100 { 101 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 102 103 /* That chip is only present in the southbridge of some 104 * cell based platforms which are supposed to select 105 * CONFIG_USB_OHCI_BIG_ENDIAN_MMIO. We verify here if 106 * that was the case though. 107 */ 108 #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO 109 ohci->flags |= OHCI_QUIRK_BE_MMIO; 110 ohci_dbg (ohci, "enabled big endian Toshiba quirk\n"); 111 return 0; 112 #else 113 ohci_err (ohci, "unsupported big endian Toshiba quirk\n"); 114 return -ENXIO; 115 #endif 116 } 117 118 /* Check for NEC chip and apply quirk for allegedly lost interrupts. 119 */ 120 121 static void ohci_quirk_nec_worker(struct work_struct *work) 122 { 123 struct ohci_hcd *ohci = container_of(work, struct ohci_hcd, nec_work); 124 int status; 125 126 status = ohci_init(ohci); 127 if (status != 0) { 128 ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n", 129 "ohci_init", status); 130 return; 131 } 132 133 status = ohci_restart(ohci); 134 if (status != 0) 135 ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n", 136 "ohci_restart", status); 137 } 138 139 static int ohci_quirk_nec(struct usb_hcd *hcd) 140 { 141 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 142 143 ohci->flags |= OHCI_QUIRK_NEC; 144 INIT_WORK(&ohci->nec_work, ohci_quirk_nec_worker); 145 ohci_dbg (ohci, "enabled NEC chipset lost interrupt quirk\n"); 146 147 return 0; 148 } 149 150 static int ohci_quirk_amd700(struct usb_hcd *hcd) 151 { 152 struct ohci_hcd *ohci = hcd_to_ohci(hcd); 153 struct pci_dev *amd_smbus_dev; 154 u8 rev; 155 156 if (usb_amd_find_chipset_info()) 157 ohci->flags |= OHCI_QUIRK_AMD_PLL; 158 159 amd_smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 160 PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL); 161 if (!amd_smbus_dev) 162 return 0; 163 164 rev = amd_smbus_dev->revision; 165 166 /* SB800 needs pre-fetch fix */ 167 if ((rev >= 0x40) && (rev <= 0x4f)) { 168 ohci->flags |= OHCI_QUIRK_AMD_PREFETCH; 169 ohci_dbg(ohci, "enabled AMD prefetch quirk\n"); 170 } 171 172 pci_dev_put(amd_smbus_dev); 173 amd_smbus_dev = NULL; 174 175 return 0; 176 } 177 178 /* nVidia controllers continue to drive Reset signalling on the bus 179 * even after system shutdown, wasting power. This flag tells the 180 * shutdown routine to leave the controller OPERATIONAL instead of RESET. 181 */ 182 static int ohci_quirk_nvidia_shutdown(struct usb_hcd *hcd) 183 { 184 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 185 struct ohci_hcd *ohci = hcd_to_ohci(hcd); 186 187 /* Evidently nVidia fixed their later hardware; this is a guess at 188 * the changeover point. 189 */ 190 #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_USB 0x026d 191 192 if (pdev->device < PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_USB) { 193 ohci->flags |= OHCI_QUIRK_SHUTDOWN; 194 ohci_dbg(ohci, "enabled nVidia shutdown quirk\n"); 195 } 196 197 return 0; 198 } 199 200 static void sb800_prefetch(struct ohci_hcd *ohci, int on) 201 { 202 struct pci_dev *pdev; 203 u16 misc; 204 205 pdev = to_pci_dev(ohci_to_hcd(ohci)->self.controller); 206 pci_read_config_word(pdev, 0x50, &misc); 207 if (on == 0) 208 pci_write_config_word(pdev, 0x50, misc & 0xfcff); 209 else 210 pci_write_config_word(pdev, 0x50, misc | 0x0300); 211 } 212 213 /* List of quirks for OHCI */ 214 static const struct pci_device_id ohci_pci_quirks[] = { 215 { 216 PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x740c), 217 .driver_data = (unsigned long)ohci_quirk_amd756, 218 }, 219 { 220 PCI_DEVICE(PCI_VENDOR_ID_OPTI, 0xc861), 221 .driver_data = (unsigned long)ohci_quirk_opti, 222 }, 223 { 224 PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_ANY_ID), 225 .driver_data = (unsigned long)ohci_quirk_ns, 226 }, 227 { 228 PCI_DEVICE(PCI_VENDOR_ID_COMPAQ, 0xa0f8), 229 .driver_data = (unsigned long)ohci_quirk_zfmicro, 230 }, 231 { 232 PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, 0x01b6), 233 .driver_data = (unsigned long)ohci_quirk_toshiba_scc, 234 }, 235 { 236 PCI_DEVICE(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB), 237 .driver_data = (unsigned long)ohci_quirk_nec, 238 }, 239 { 240 /* Toshiba portege 4000 */ 241 .vendor = PCI_VENDOR_ID_AL, 242 .device = 0x5237, 243 .subvendor = PCI_VENDOR_ID_TOSHIBA, 244 .subdevice = 0x0004, 245 .driver_data = (unsigned long) broken_suspend, 246 }, 247 { 248 PCI_DEVICE(PCI_VENDOR_ID_ITE, 0x8152), 249 .driver_data = (unsigned long) broken_suspend, 250 }, 251 { 252 PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4397), 253 .driver_data = (unsigned long)ohci_quirk_amd700, 254 }, 255 { 256 PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4398), 257 .driver_data = (unsigned long)ohci_quirk_amd700, 258 }, 259 { 260 PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4399), 261 .driver_data = (unsigned long)ohci_quirk_amd700, 262 }, 263 { 264 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 265 .driver_data = (unsigned long) ohci_quirk_nvidia_shutdown, 266 }, 267 268 /* FIXME for some of the early AMD 760 southbridges, OHCI 269 * won't work at all. blacklist them. 270 */ 271 272 {}, 273 }; 274 275 static int ohci_pci_reset (struct usb_hcd *hcd) 276 { 277 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 278 int ret = 0; 279 280 if (hcd->self.controller) { 281 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 282 const struct pci_device_id *quirk_id; 283 284 quirk_id = pci_match_id(ohci_pci_quirks, pdev); 285 if (quirk_id != NULL) { 286 int (*quirk)(struct usb_hcd *ohci); 287 quirk = (void *)quirk_id->driver_data; 288 ret = quirk(hcd); 289 } 290 } 291 if (ret == 0) { 292 ohci_hcd_init (ohci); 293 return ohci_init (ohci); 294 } 295 return ret; 296 } 297 298 299 static int __devinit ohci_pci_start (struct usb_hcd *hcd) 300 { 301 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 302 int ret; 303 304 #ifdef CONFIG_PM /* avoid warnings about unused pdev */ 305 if (hcd->self.controller) { 306 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 307 308 /* RWC may not be set for add-in PCI cards, since boot 309 * firmware probably ignored them. This transfers PCI 310 * PM wakeup capabilities. 311 */ 312 if (device_can_wakeup(&pdev->dev)) 313 ohci->hc_control |= OHCI_CTRL_RWC; 314 } 315 #endif /* CONFIG_PM */ 316 317 ret = ohci_run (ohci); 318 if (ret < 0) { 319 ohci_err (ohci, "can't start\n"); 320 ohci_stop (hcd); 321 } 322 return ret; 323 } 324 325 #ifdef CONFIG_PM 326 327 static int ohci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 328 { 329 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 330 unsigned long flags; 331 int rc = 0; 332 333 /* Root hub was already suspended. Disable irq emission and 334 * mark HW unaccessible, bail out if RH has been resumed. Use 335 * the spinlock to properly synchronize with possible pending 336 * RH suspend or resume activity. 337 * 338 * This is still racy as hcd->state is manipulated outside of 339 * any locks =P But that will be a different fix. 340 */ 341 spin_lock_irqsave (&ohci->lock, flags); 342 if (hcd->state != HC_STATE_SUSPENDED) { 343 rc = -EINVAL; 344 goto bail; 345 } 346 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); 347 (void)ohci_readl(ohci, &ohci->regs->intrdisable); 348 349 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 350 bail: 351 spin_unlock_irqrestore (&ohci->lock, flags); 352 353 return rc; 354 } 355 356 357 static int ohci_pci_resume(struct usb_hcd *hcd, bool hibernated) 358 { 359 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 360 361 /* Make sure resume from hibernation re-enumerates everything */ 362 if (hibernated) 363 ohci_usb_reset(hcd_to_ohci(hcd)); 364 365 ohci_finish_controller_resume(hcd); 366 return 0; 367 } 368 369 #endif /* CONFIG_PM */ 370 371 372 /*-------------------------------------------------------------------------*/ 373 374 static const struct hc_driver ohci_pci_hc_driver = { 375 .description = hcd_name, 376 .product_desc = "OHCI Host Controller", 377 .hcd_priv_size = sizeof(struct ohci_hcd), 378 379 /* 380 * generic hardware linkage 381 */ 382 .irq = ohci_irq, 383 .flags = HCD_MEMORY | HCD_USB11, 384 385 /* 386 * basic lifecycle operations 387 */ 388 .reset = ohci_pci_reset, 389 .start = ohci_pci_start, 390 .stop = ohci_stop, 391 .shutdown = ohci_shutdown, 392 393 #ifdef CONFIG_PM 394 .pci_suspend = ohci_pci_suspend, 395 .pci_resume = ohci_pci_resume, 396 #endif 397 398 /* 399 * managing i/o requests and associated device resources 400 */ 401 .urb_enqueue = ohci_urb_enqueue, 402 .urb_dequeue = ohci_urb_dequeue, 403 .endpoint_disable = ohci_endpoint_disable, 404 405 /* 406 * scheduling support 407 */ 408 .get_frame_number = ohci_get_frame, 409 410 /* 411 * root hub support 412 */ 413 .hub_status_data = ohci_hub_status_data, 414 .hub_control = ohci_hub_control, 415 #ifdef CONFIG_PM 416 .bus_suspend = ohci_bus_suspend, 417 .bus_resume = ohci_bus_resume, 418 #endif 419 .start_port_reset = ohci_start_port_reset, 420 }; 421 422 /*-------------------------------------------------------------------------*/ 423 424 425 static const struct pci_device_id pci_ids [] = { { 426 /* handle any USB OHCI controller */ 427 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_OHCI, ~0), 428 .driver_data = (unsigned long) &ohci_pci_hc_driver, 429 }, { /* end: all zeroes */ } 430 }; 431 MODULE_DEVICE_TABLE (pci, pci_ids); 432 433 /* pci driver glue; this is a "new style" PCI driver module */ 434 static struct pci_driver ohci_pci_driver = { 435 .name = (char *) hcd_name, 436 .id_table = pci_ids, 437 438 .probe = usb_hcd_pci_probe, 439 .remove = usb_hcd_pci_remove, 440 .shutdown = usb_hcd_pci_shutdown, 441 442 #ifdef CONFIG_PM_SLEEP 443 .driver = { 444 .pm = &usb_hcd_pci_pm_ops 445 }, 446 #endif 447 }; 448