1 /* 2 * OHCI HCD (Host Controller Driver) for USB. 3 * 4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 5 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net> 6 * 7 * [ Initialisation is based on Linus' ] 8 * [ uhci code and gregs ohci fragments ] 9 * [ (C) Copyright 1999 Linus Torvalds ] 10 * [ (C) Copyright 1999 Gregory P. Smith] 11 * 12 * 13 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller 14 * interfaces (though some non-x86 Intel chips use it). It supports 15 * smarter hardware than UHCI. A download link for the spec available 16 * through the http://www.usb.org website. 17 * 18 * This file is licenced under the GPL. 19 */ 20 21 #include <linux/module.h> 22 #include <linux/moduleparam.h> 23 #include <linux/pci.h> 24 #include <linux/kernel.h> 25 #include <linux/delay.h> 26 #include <linux/ioport.h> 27 #include <linux/sched.h> 28 #include <linux/slab.h> 29 #include <linux/errno.h> 30 #include <linux/init.h> 31 #include <linux/timer.h> 32 #include <linux/list.h> 33 #include <linux/usb.h> 34 #include <linux/usb/otg.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/dmapool.h> 37 #include <linux/reboot.h> 38 #include <linux/workqueue.h> 39 #include <linux/debugfs.h> 40 41 #include <asm/io.h> 42 #include <asm/irq.h> 43 #include <asm/system.h> 44 #include <asm/unaligned.h> 45 #include <asm/byteorder.h> 46 47 #include "../core/hcd.h" 48 49 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell" 50 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver" 51 52 /*-------------------------------------------------------------------------*/ 53 54 #undef OHCI_VERBOSE_DEBUG /* not always helpful */ 55 56 /* For initializing controller (mask in an HCFS mode too) */ 57 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR 58 #define OHCI_INTR_INIT \ 59 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \ 60 | OHCI_INTR_RD | OHCI_INTR_WDH) 61 62 #ifdef __hppa__ 63 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ 64 #define IR_DISABLE 65 #endif 66 67 #ifdef CONFIG_ARCH_OMAP 68 /* OMAP doesn't support IR (no SMM; not needed) */ 69 #define IR_DISABLE 70 #endif 71 72 /*-------------------------------------------------------------------------*/ 73 74 static const char hcd_name [] = "ohci_hcd"; 75 76 #define STATECHANGE_DELAY msecs_to_jiffies(300) 77 78 #include "ohci.h" 79 80 static void ohci_dump (struct ohci_hcd *ohci, int verbose); 81 static int ohci_init (struct ohci_hcd *ohci); 82 static void ohci_stop (struct usb_hcd *hcd); 83 84 #if defined(CONFIG_PM) || defined(CONFIG_PCI) 85 static int ohci_restart (struct ohci_hcd *ohci); 86 #endif 87 88 #ifdef CONFIG_PCI 89 static void quirk_amd_pll(int state); 90 static void amd_iso_dev_put(void); 91 #else 92 static inline void quirk_amd_pll(int state) 93 { 94 return; 95 } 96 static inline void amd_iso_dev_put(void) 97 { 98 return; 99 } 100 #endif 101 102 103 #include "ohci-hub.c" 104 #include "ohci-dbg.c" 105 #include "ohci-mem.c" 106 #include "ohci-q.c" 107 108 109 /* 110 * On architectures with edge-triggered interrupts we must never return 111 * IRQ_NONE. 112 */ 113 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */ 114 #define IRQ_NOTMINE IRQ_HANDLED 115 #else 116 #define IRQ_NOTMINE IRQ_NONE 117 #endif 118 119 120 /* Some boards misreport power switching/overcurrent */ 121 static int distrust_firmware = 1; 122 module_param (distrust_firmware, bool, 0); 123 MODULE_PARM_DESC (distrust_firmware, 124 "true to distrust firmware power/overcurrent setup"); 125 126 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */ 127 static int no_handshake = 0; 128 module_param (no_handshake, bool, 0); 129 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake"); 130 131 /*-------------------------------------------------------------------------*/ 132 133 /* 134 * queue up an urb for anything except the root hub 135 */ 136 static int ohci_urb_enqueue ( 137 struct usb_hcd *hcd, 138 struct urb *urb, 139 gfp_t mem_flags 140 ) { 141 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 142 struct ed *ed; 143 urb_priv_t *urb_priv; 144 unsigned int pipe = urb->pipe; 145 int i, size = 0; 146 unsigned long flags; 147 int retval = 0; 148 149 #ifdef OHCI_VERBOSE_DEBUG 150 urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS); 151 #endif 152 153 /* every endpoint has a ed, locate and maybe (re)initialize it */ 154 if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval))) 155 return -ENOMEM; 156 157 /* for the private part of the URB we need the number of TDs (size) */ 158 switch (ed->type) { 159 case PIPE_CONTROL: 160 /* td_submit_urb() doesn't yet handle these */ 161 if (urb->transfer_buffer_length > 4096) 162 return -EMSGSIZE; 163 164 /* 1 TD for setup, 1 for ACK, plus ... */ 165 size = 2; 166 /* FALLTHROUGH */ 167 // case PIPE_INTERRUPT: 168 // case PIPE_BULK: 169 default: 170 /* one TD for every 4096 Bytes (can be upto 8K) */ 171 size += urb->transfer_buffer_length / 4096; 172 /* ... and for any remaining bytes ... */ 173 if ((urb->transfer_buffer_length % 4096) != 0) 174 size++; 175 /* ... and maybe a zero length packet to wrap it up */ 176 if (size == 0) 177 size++; 178 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0 179 && (urb->transfer_buffer_length 180 % usb_maxpacket (urb->dev, pipe, 181 usb_pipeout (pipe))) == 0) 182 size++; 183 break; 184 case PIPE_ISOCHRONOUS: /* number of packets from URB */ 185 size = urb->number_of_packets; 186 break; 187 } 188 189 /* allocate the private part of the URB */ 190 urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *), 191 mem_flags); 192 if (!urb_priv) 193 return -ENOMEM; 194 INIT_LIST_HEAD (&urb_priv->pending); 195 urb_priv->length = size; 196 urb_priv->ed = ed; 197 198 /* allocate the TDs (deferring hash chain updates) */ 199 for (i = 0; i < size; i++) { 200 urb_priv->td [i] = td_alloc (ohci, mem_flags); 201 if (!urb_priv->td [i]) { 202 urb_priv->length = i; 203 urb_free_priv (ohci, urb_priv); 204 return -ENOMEM; 205 } 206 } 207 208 spin_lock_irqsave (&ohci->lock, flags); 209 210 /* don't submit to a dead HC */ 211 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { 212 retval = -ENODEV; 213 goto fail; 214 } 215 if (!HC_IS_RUNNING(hcd->state)) { 216 retval = -ENODEV; 217 goto fail; 218 } 219 retval = usb_hcd_link_urb_to_ep(hcd, urb); 220 if (retval) 221 goto fail; 222 223 /* schedule the ed if needed */ 224 if (ed->state == ED_IDLE) { 225 retval = ed_schedule (ohci, ed); 226 if (retval < 0) { 227 usb_hcd_unlink_urb_from_ep(hcd, urb); 228 goto fail; 229 } 230 if (ed->type == PIPE_ISOCHRONOUS) { 231 u16 frame = ohci_frame_no(ohci); 232 233 /* delay a few frames before the first TD */ 234 frame += max_t (u16, 8, ed->interval); 235 frame &= ~(ed->interval - 1); 236 frame |= ed->branch; 237 urb->start_frame = frame; 238 239 /* yes, only URB_ISO_ASAP is supported, and 240 * urb->start_frame is never used as input. 241 */ 242 } 243 } else if (ed->type == PIPE_ISOCHRONOUS) 244 urb->start_frame = ed->last_iso + ed->interval; 245 246 /* fill the TDs and link them to the ed; and 247 * enable that part of the schedule, if needed 248 * and update count of queued periodic urbs 249 */ 250 urb->hcpriv = urb_priv; 251 td_submit_urb (ohci, urb); 252 253 fail: 254 if (retval) 255 urb_free_priv (ohci, urb_priv); 256 spin_unlock_irqrestore (&ohci->lock, flags); 257 return retval; 258 } 259 260 /* 261 * decouple the URB from the HC queues (TDs, urb_priv). 262 * reporting is always done 263 * asynchronously, and we might be dealing with an urb that's 264 * partially transferred, or an ED with other urbs being unlinked. 265 */ 266 static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) 267 { 268 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 269 unsigned long flags; 270 int rc; 271 272 #ifdef OHCI_VERBOSE_DEBUG 273 urb_print(urb, "UNLINK", 1, status); 274 #endif 275 276 spin_lock_irqsave (&ohci->lock, flags); 277 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 278 if (rc) { 279 ; /* Do nothing */ 280 } else if (HC_IS_RUNNING(hcd->state)) { 281 urb_priv_t *urb_priv; 282 283 /* Unless an IRQ completed the unlink while it was being 284 * handed to us, flag it for unlink and giveback, and force 285 * some upcoming INTR_SF to call finish_unlinks() 286 */ 287 urb_priv = urb->hcpriv; 288 if (urb_priv) { 289 if (urb_priv->ed->state == ED_OPER) 290 start_ed_unlink (ohci, urb_priv->ed); 291 } 292 } else { 293 /* 294 * with HC dead, we won't respect hc queue pointers 295 * any more ... just clean up every urb's memory. 296 */ 297 if (urb->hcpriv) 298 finish_urb(ohci, urb, status); 299 } 300 spin_unlock_irqrestore (&ohci->lock, flags); 301 return rc; 302 } 303 304 /*-------------------------------------------------------------------------*/ 305 306 /* frees config/altsetting state for endpoints, 307 * including ED memory, dummy TD, and bulk/intr data toggle 308 */ 309 310 static void 311 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) 312 { 313 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 314 unsigned long flags; 315 struct ed *ed = ep->hcpriv; 316 unsigned limit = 1000; 317 318 /* ASSERT: any requests/urbs are being unlinked */ 319 /* ASSERT: nobody can be submitting urbs for this any more */ 320 321 if (!ed) 322 return; 323 324 rescan: 325 spin_lock_irqsave (&ohci->lock, flags); 326 327 if (!HC_IS_RUNNING (hcd->state)) { 328 sanitize: 329 ed->state = ED_IDLE; 330 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT) 331 ohci->eds_scheduled--; 332 finish_unlinks (ohci, 0); 333 } 334 335 switch (ed->state) { 336 case ED_UNLINK: /* wait for hw to finish? */ 337 /* major IRQ delivery trouble loses INTR_SF too... */ 338 if (limit-- == 0) { 339 ohci_warn(ohci, "ED unlink timeout\n"); 340 if (quirk_zfmicro(ohci)) { 341 ohci_warn(ohci, "Attempting ZF TD recovery\n"); 342 ohci->ed_to_check = ed; 343 ohci->zf_delay = 2; 344 } 345 goto sanitize; 346 } 347 spin_unlock_irqrestore (&ohci->lock, flags); 348 schedule_timeout_uninterruptible(1); 349 goto rescan; 350 case ED_IDLE: /* fully unlinked */ 351 if (list_empty (&ed->td_list)) { 352 td_free (ohci, ed->dummy); 353 ed_free (ohci, ed); 354 break; 355 } 356 /* else FALL THROUGH */ 357 default: 358 /* caller was supposed to have unlinked any requests; 359 * that's not our job. can't recover; must leak ed. 360 */ 361 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n", 362 ed, ep->desc.bEndpointAddress, ed->state, 363 list_empty (&ed->td_list) ? "" : " (has tds)"); 364 td_free (ohci, ed->dummy); 365 break; 366 } 367 ep->hcpriv = NULL; 368 spin_unlock_irqrestore (&ohci->lock, flags); 369 return; 370 } 371 372 static int ohci_get_frame (struct usb_hcd *hcd) 373 { 374 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 375 376 return ohci_frame_no(ohci); 377 } 378 379 static void ohci_usb_reset (struct ohci_hcd *ohci) 380 { 381 ohci->hc_control = ohci_readl (ohci, &ohci->regs->control); 382 ohci->hc_control &= OHCI_CTRL_RWC; 383 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); 384 } 385 386 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and 387 * other cases where the next software may expect clean state from the 388 * "firmware". this is bus-neutral, unlike shutdown() methods. 389 */ 390 static void 391 ohci_shutdown (struct usb_hcd *hcd) 392 { 393 struct ohci_hcd *ohci; 394 395 ohci = hcd_to_ohci (hcd); 396 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); 397 ohci_usb_reset (ohci); 398 /* flush the writes */ 399 (void) ohci_readl (ohci, &ohci->regs->control); 400 } 401 402 static int check_ed(struct ohci_hcd *ohci, struct ed *ed) 403 { 404 return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0 405 && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK) 406 == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK) 407 && !list_empty(&ed->td_list); 408 } 409 410 /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes 411 * an interrupt TD but neglects to add it to the donelist. On systems with 412 * this chipset, we need to periodically check the state of the queues to look 413 * for such "lost" TDs. 414 */ 415 static void unlink_watchdog_func(unsigned long _ohci) 416 { 417 unsigned long flags; 418 unsigned max; 419 unsigned seen_count = 0; 420 unsigned i; 421 struct ed **seen = NULL; 422 struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci; 423 424 spin_lock_irqsave(&ohci->lock, flags); 425 max = ohci->eds_scheduled; 426 if (!max) 427 goto done; 428 429 if (ohci->ed_to_check) 430 goto out; 431 432 seen = kcalloc(max, sizeof *seen, GFP_ATOMIC); 433 if (!seen) 434 goto out; 435 436 for (i = 0; i < NUM_INTS; i++) { 437 struct ed *ed = ohci->periodic[i]; 438 439 while (ed) { 440 unsigned temp; 441 442 /* scan this branch of the periodic schedule tree */ 443 for (temp = 0; temp < seen_count; temp++) { 444 if (seen[temp] == ed) { 445 /* we've checked it and what's after */ 446 ed = NULL; 447 break; 448 } 449 } 450 if (!ed) 451 break; 452 seen[seen_count++] = ed; 453 if (!check_ed(ohci, ed)) { 454 ed = ed->ed_next; 455 continue; 456 } 457 458 /* HC's TD list is empty, but HCD sees at least one 459 * TD that's not been sent through the donelist. 460 */ 461 ohci->ed_to_check = ed; 462 ohci->zf_delay = 2; 463 464 /* The HC may wait until the next frame to report the 465 * TD as done through the donelist and INTR_WDH. (We 466 * just *assume* it's not a multi-TD interrupt URB; 467 * those could defer the IRQ more than one frame, using 468 * DI...) Check again after the next INTR_SF. 469 */ 470 ohci_writel(ohci, OHCI_INTR_SF, 471 &ohci->regs->intrstatus); 472 ohci_writel(ohci, OHCI_INTR_SF, 473 &ohci->regs->intrenable); 474 475 /* flush those writes */ 476 (void) ohci_readl(ohci, &ohci->regs->control); 477 478 goto out; 479 } 480 } 481 out: 482 kfree(seen); 483 if (ohci->eds_scheduled) 484 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ)); 485 done: 486 spin_unlock_irqrestore(&ohci->lock, flags); 487 } 488 489 /*-------------------------------------------------------------------------* 490 * HC functions 491 *-------------------------------------------------------------------------*/ 492 493 /* init memory, and kick BIOS/SMM off */ 494 495 static int ohci_init (struct ohci_hcd *ohci) 496 { 497 int ret; 498 struct usb_hcd *hcd = ohci_to_hcd(ohci); 499 500 if (distrust_firmware) 501 ohci->flags |= OHCI_QUIRK_HUB_POWER; 502 503 disable (ohci); 504 ohci->regs = hcd->regs; 505 506 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and 507 * was never needed for most non-PCI systems ... remove the code? 508 */ 509 510 #ifndef IR_DISABLE 511 /* SMM owns the HC? not for long! */ 512 if (!no_handshake && ohci_readl (ohci, 513 &ohci->regs->control) & OHCI_CTRL_IR) { 514 u32 temp; 515 516 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n"); 517 518 /* this timeout is arbitrary. we make it long, so systems 519 * depending on usb keyboards may be usable even if the 520 * BIOS/SMM code seems pretty broken. 521 */ 522 temp = 500; /* arbitrary: five seconds */ 523 524 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable); 525 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus); 526 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) { 527 msleep (10); 528 if (--temp == 0) { 529 ohci_err (ohci, "USB HC takeover failed!" 530 " (BIOS/SMM bug)\n"); 531 return -EBUSY; 532 } 533 } 534 ohci_usb_reset (ohci); 535 } 536 #endif 537 538 /* Disable HC interrupts */ 539 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); 540 541 /* flush the writes, and save key bits like RWC */ 542 if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC) 543 ohci->hc_control |= OHCI_CTRL_RWC; 544 545 /* Read the number of ports unless overridden */ 546 if (ohci->num_ports == 0) 547 ohci->num_ports = roothub_a(ohci) & RH_A_NDP; 548 549 if (ohci->hcca) 550 return 0; 551 552 ohci->hcca = dma_alloc_coherent (hcd->self.controller, 553 sizeof *ohci->hcca, &ohci->hcca_dma, 0); 554 if (!ohci->hcca) 555 return -ENOMEM; 556 557 if ((ret = ohci_mem_init (ohci)) < 0) 558 ohci_stop (hcd); 559 else { 560 create_debug_files (ohci); 561 } 562 563 return ret; 564 } 565 566 /*-------------------------------------------------------------------------*/ 567 568 /* Start an OHCI controller, set the BUS operational 569 * resets USB and controller 570 * enable interrupts 571 */ 572 static int ohci_run (struct ohci_hcd *ohci) 573 { 574 u32 mask, temp; 575 int first = ohci->fminterval == 0; 576 struct usb_hcd *hcd = ohci_to_hcd(ohci); 577 578 disable (ohci); 579 580 /* boot firmware should have set this up (5.1.1.3.1) */ 581 if (first) { 582 583 temp = ohci_readl (ohci, &ohci->regs->fminterval); 584 ohci->fminterval = temp & 0x3fff; 585 if (ohci->fminterval != FI) 586 ohci_dbg (ohci, "fminterval delta %d\n", 587 ohci->fminterval - FI); 588 ohci->fminterval |= FSMP (ohci->fminterval) << 16; 589 /* also: power/overcurrent flags in roothub.a */ 590 } 591 592 /* Reset USB nearly "by the book". RemoteWakeupConnected has 593 * to be checked in case boot firmware (BIOS/SMM/...) has set up 594 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM). 595 * If the bus glue detected wakeup capability then it should 596 * already be enabled; if so we'll just enable it again. 597 */ 598 if ((ohci->hc_control & OHCI_CTRL_RWC) != 0) 599 device_set_wakeup_capable(hcd->self.controller, 1); 600 601 switch (ohci->hc_control & OHCI_CTRL_HCFS) { 602 case OHCI_USB_OPER: 603 temp = 0; 604 break; 605 case OHCI_USB_SUSPEND: 606 case OHCI_USB_RESUME: 607 ohci->hc_control &= OHCI_CTRL_RWC; 608 ohci->hc_control |= OHCI_USB_RESUME; 609 temp = 10 /* msec wait */; 610 break; 611 // case OHCI_USB_RESET: 612 default: 613 ohci->hc_control &= OHCI_CTRL_RWC; 614 ohci->hc_control |= OHCI_USB_RESET; 615 temp = 50 /* msec wait */; 616 break; 617 } 618 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); 619 // flush the writes 620 (void) ohci_readl (ohci, &ohci->regs->control); 621 msleep(temp); 622 623 memset (ohci->hcca, 0, sizeof (struct ohci_hcca)); 624 625 /* 2msec timelimit here means no irqs/preempt */ 626 spin_lock_irq (&ohci->lock); 627 628 retry: 629 /* HC Reset requires max 10 us delay */ 630 ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus); 631 temp = 30; /* ... allow extra time */ 632 while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) { 633 if (--temp == 0) { 634 spin_unlock_irq (&ohci->lock); 635 ohci_err (ohci, "USB HC reset timed out!\n"); 636 return -1; 637 } 638 udelay (1); 639 } 640 641 /* now we're in the SUSPEND state ... must go OPERATIONAL 642 * within 2msec else HC enters RESUME 643 * 644 * ... but some hardware won't init fmInterval "by the book" 645 * (SiS, OPTi ...), so reset again instead. SiS doesn't need 646 * this if we write fmInterval after we're OPERATIONAL. 647 * Unclear about ALi, ServerWorks, and others ... this could 648 * easily be a longstanding bug in chip init on Linux. 649 */ 650 if (ohci->flags & OHCI_QUIRK_INITRESET) { 651 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); 652 // flush those writes 653 (void) ohci_readl (ohci, &ohci->regs->control); 654 } 655 656 /* Tell the controller where the control and bulk lists are 657 * The lists are empty now. */ 658 ohci_writel (ohci, 0, &ohci->regs->ed_controlhead); 659 ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead); 660 661 /* a reset clears this */ 662 ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca); 663 664 periodic_reinit (ohci); 665 666 /* some OHCI implementations are finicky about how they init. 667 * bogus values here mean not even enumeration could work. 668 */ 669 if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0 670 || !ohci_readl (ohci, &ohci->regs->periodicstart)) { 671 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) { 672 ohci->flags |= OHCI_QUIRK_INITRESET; 673 ohci_dbg (ohci, "enabling initreset quirk\n"); 674 goto retry; 675 } 676 spin_unlock_irq (&ohci->lock); 677 ohci_err (ohci, "init err (%08x %04x)\n", 678 ohci_readl (ohci, &ohci->regs->fminterval), 679 ohci_readl (ohci, &ohci->regs->periodicstart)); 680 return -EOVERFLOW; 681 } 682 683 /* use rhsc irqs after khubd is fully initialized */ 684 hcd->poll_rh = 1; 685 hcd->uses_new_polling = 1; 686 687 /* start controller operations */ 688 ohci->hc_control &= OHCI_CTRL_RWC; 689 ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER; 690 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); 691 hcd->state = HC_STATE_RUNNING; 692 693 /* wake on ConnectStatusChange, matching external hubs */ 694 ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status); 695 696 /* Choose the interrupts we care about now, others later on demand */ 697 mask = OHCI_INTR_INIT; 698 ohci_writel (ohci, ~0, &ohci->regs->intrstatus); 699 ohci_writel (ohci, mask, &ohci->regs->intrenable); 700 701 /* handle root hub init quirks ... */ 702 temp = roothub_a (ohci); 703 temp &= ~(RH_A_PSM | RH_A_OCPM); 704 if (ohci->flags & OHCI_QUIRK_SUPERIO) { 705 /* NSC 87560 and maybe others */ 706 temp |= RH_A_NOCP; 707 temp &= ~(RH_A_POTPGT | RH_A_NPS); 708 ohci_writel (ohci, temp, &ohci->regs->roothub.a); 709 } else if ((ohci->flags & OHCI_QUIRK_AMD756) || 710 (ohci->flags & OHCI_QUIRK_HUB_POWER)) { 711 /* hub power always on; required for AMD-756 and some 712 * Mac platforms. ganged overcurrent reporting, if any. 713 */ 714 temp |= RH_A_NPS; 715 ohci_writel (ohci, temp, &ohci->regs->roothub.a); 716 } 717 ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status); 718 ohci_writel (ohci, (temp & RH_A_NPS) ? 0 : RH_B_PPCM, 719 &ohci->regs->roothub.b); 720 // flush those writes 721 (void) ohci_readl (ohci, &ohci->regs->control); 722 723 ohci->next_statechange = jiffies + STATECHANGE_DELAY; 724 spin_unlock_irq (&ohci->lock); 725 726 // POTPGT delay is bits 24-31, in 2 ms units. 727 mdelay ((temp >> 23) & 0x1fe); 728 hcd->state = HC_STATE_RUNNING; 729 730 if (quirk_zfmicro(ohci)) { 731 /* Create timer to watch for bad queue state on ZF Micro */ 732 setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func, 733 (unsigned long) ohci); 734 735 ohci->eds_scheduled = 0; 736 ohci->ed_to_check = NULL; 737 } 738 739 ohci_dump (ohci, 1); 740 741 return 0; 742 } 743 744 /*-------------------------------------------------------------------------*/ 745 746 /* an interrupt happens */ 747 748 static irqreturn_t ohci_irq (struct usb_hcd *hcd) 749 { 750 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 751 struct ohci_regs __iomem *regs = ohci->regs; 752 int ints; 753 754 /* Read interrupt status (and flush pending writes). We ignore the 755 * optimization of checking the LSB of hcca->done_head; it doesn't 756 * work on all systems (edge triggering for OHCI can be a factor). 757 */ 758 ints = ohci_readl(ohci, ®s->intrstatus); 759 760 /* Check for an all 1's result which is a typical consequence 761 * of dead, unclocked, or unplugged (CardBus...) devices 762 */ 763 if (ints == ~(u32)0) { 764 disable (ohci); 765 ohci_dbg (ohci, "device removed!\n"); 766 return IRQ_HANDLED; 767 } 768 769 /* We only care about interrupts that are enabled */ 770 ints &= ohci_readl(ohci, ®s->intrenable); 771 772 /* interrupt for some other device? */ 773 if (ints == 0) 774 return IRQ_NOTMINE; 775 776 if (ints & OHCI_INTR_UE) { 777 // e.g. due to PCI Master/Target Abort 778 if (quirk_nec(ohci)) { 779 /* Workaround for a silicon bug in some NEC chips used 780 * in Apple's PowerBooks. Adapted from Darwin code. 781 */ 782 ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n"); 783 784 ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable); 785 786 schedule_work (&ohci->nec_work); 787 } else { 788 disable (ohci); 789 ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n"); 790 } 791 792 ohci_dump (ohci, 1); 793 ohci_usb_reset (ohci); 794 } 795 796 if (ints & OHCI_INTR_RHSC) { 797 ohci_vdbg(ohci, "rhsc\n"); 798 ohci->next_statechange = jiffies + STATECHANGE_DELAY; 799 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC, 800 ®s->intrstatus); 801 802 /* NOTE: Vendors didn't always make the same implementation 803 * choices for RHSC. Many followed the spec; RHSC triggers 804 * on an edge, like setting and maybe clearing a port status 805 * change bit. With others it's level-triggered, active 806 * until khubd clears all the port status change bits. We'll 807 * always disable it here and rely on polling until khubd 808 * re-enables it. 809 */ 810 ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable); 811 usb_hcd_poll_rh_status(hcd); 812 } 813 814 /* For connect and disconnect events, we expect the controller 815 * to turn on RHSC along with RD. But for remote wakeup events 816 * this might not happen. 817 */ 818 else if (ints & OHCI_INTR_RD) { 819 ohci_vdbg(ohci, "resume detect\n"); 820 ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus); 821 hcd->poll_rh = 1; 822 if (ohci->autostop) { 823 spin_lock (&ohci->lock); 824 ohci_rh_resume (ohci); 825 spin_unlock (&ohci->lock); 826 } else 827 usb_hcd_resume_root_hub(hcd); 828 } 829 830 if (ints & OHCI_INTR_WDH) { 831 spin_lock (&ohci->lock); 832 dl_done_list (ohci); 833 spin_unlock (&ohci->lock); 834 } 835 836 if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) { 837 spin_lock(&ohci->lock); 838 if (ohci->ed_to_check) { 839 struct ed *ed = ohci->ed_to_check; 840 841 if (check_ed(ohci, ed)) { 842 /* HC thinks the TD list is empty; HCD knows 843 * at least one TD is outstanding 844 */ 845 if (--ohci->zf_delay == 0) { 846 struct td *td = list_entry( 847 ed->td_list.next, 848 struct td, td_list); 849 ohci_warn(ohci, 850 "Reclaiming orphan TD %p\n", 851 td); 852 takeback_td(ohci, td); 853 ohci->ed_to_check = NULL; 854 } 855 } else 856 ohci->ed_to_check = NULL; 857 } 858 spin_unlock(&ohci->lock); 859 } 860 861 /* could track INTR_SO to reduce available PCI/... bandwidth */ 862 863 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled 864 * when there's still unlinking to be done (next frame). 865 */ 866 spin_lock (&ohci->lock); 867 if (ohci->ed_rm_list) 868 finish_unlinks (ohci, ohci_frame_no(ohci)); 869 if ((ints & OHCI_INTR_SF) != 0 870 && !ohci->ed_rm_list 871 && !ohci->ed_to_check 872 && HC_IS_RUNNING(hcd->state)) 873 ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable); 874 spin_unlock (&ohci->lock); 875 876 if (HC_IS_RUNNING(hcd->state)) { 877 ohci_writel (ohci, ints, ®s->intrstatus); 878 ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable); 879 // flush those writes 880 (void) ohci_readl (ohci, &ohci->regs->control); 881 } 882 883 return IRQ_HANDLED; 884 } 885 886 /*-------------------------------------------------------------------------*/ 887 888 static void ohci_stop (struct usb_hcd *hcd) 889 { 890 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 891 892 ohci_dump (ohci, 1); 893 894 flush_scheduled_work(); 895 896 ohci_usb_reset (ohci); 897 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); 898 free_irq(hcd->irq, hcd); 899 hcd->irq = -1; 900 901 if (quirk_zfmicro(ohci)) 902 del_timer(&ohci->unlink_watchdog); 903 if (quirk_amdiso(ohci)) 904 amd_iso_dev_put(); 905 906 remove_debug_files (ohci); 907 ohci_mem_cleanup (ohci); 908 if (ohci->hcca) { 909 dma_free_coherent (hcd->self.controller, 910 sizeof *ohci->hcca, 911 ohci->hcca, ohci->hcca_dma); 912 ohci->hcca = NULL; 913 ohci->hcca_dma = 0; 914 } 915 } 916 917 /*-------------------------------------------------------------------------*/ 918 919 #if defined(CONFIG_PM) || defined(CONFIG_PCI) 920 921 /* must not be called from interrupt context */ 922 static int ohci_restart (struct ohci_hcd *ohci) 923 { 924 int temp; 925 int i; 926 struct urb_priv *priv; 927 928 spin_lock_irq(&ohci->lock); 929 disable (ohci); 930 931 /* Recycle any "live" eds/tds (and urbs). */ 932 if (!list_empty (&ohci->pending)) 933 ohci_dbg(ohci, "abort schedule...\n"); 934 list_for_each_entry (priv, &ohci->pending, pending) { 935 struct urb *urb = priv->td[0]->urb; 936 struct ed *ed = priv->ed; 937 938 switch (ed->state) { 939 case ED_OPER: 940 ed->state = ED_UNLINK; 941 ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE); 942 ed_deschedule (ohci, ed); 943 944 ed->ed_next = ohci->ed_rm_list; 945 ed->ed_prev = NULL; 946 ohci->ed_rm_list = ed; 947 /* FALLTHROUGH */ 948 case ED_UNLINK: 949 break; 950 default: 951 ohci_dbg(ohci, "bogus ed %p state %d\n", 952 ed, ed->state); 953 } 954 955 if (!urb->unlinked) 956 urb->unlinked = -ESHUTDOWN; 957 } 958 finish_unlinks (ohci, 0); 959 spin_unlock_irq(&ohci->lock); 960 961 /* paranoia, in case that didn't work: */ 962 963 /* empty the interrupt branches */ 964 for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0; 965 for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0; 966 967 /* no EDs to remove */ 968 ohci->ed_rm_list = NULL; 969 970 /* empty control and bulk lists */ 971 ohci->ed_controltail = NULL; 972 ohci->ed_bulktail = NULL; 973 974 if ((temp = ohci_run (ohci)) < 0) { 975 ohci_err (ohci, "can't restart, %d\n", temp); 976 return temp; 977 } 978 ohci_dbg(ohci, "restart complete\n"); 979 return 0; 980 } 981 982 #endif 983 984 /*-------------------------------------------------------------------------*/ 985 986 MODULE_AUTHOR (DRIVER_AUTHOR); 987 MODULE_DESCRIPTION(DRIVER_DESC); 988 MODULE_LICENSE ("GPL"); 989 990 #ifdef CONFIG_PCI 991 #include "ohci-pci.c" 992 #define PCI_DRIVER ohci_pci_driver 993 #endif 994 995 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111) 996 #include "ohci-sa1111.c" 997 #define SA1111_DRIVER ohci_hcd_sa1111_driver 998 #endif 999 1000 #if defined(CONFIG_ARCH_S3C2410) || defined(CONFIG_ARCH_S3C64XX) 1001 #include "ohci-s3c2410.c" 1002 #define PLATFORM_DRIVER ohci_hcd_s3c2410_driver 1003 #endif 1004 1005 #ifdef CONFIG_ARCH_OMAP 1006 #include "ohci-omap.c" 1007 #define PLATFORM_DRIVER ohci_hcd_omap_driver 1008 #endif 1009 1010 #ifdef CONFIG_ARCH_LH7A404 1011 #include "ohci-lh7a404.c" 1012 #define PLATFORM_DRIVER ohci_hcd_lh7a404_driver 1013 #endif 1014 1015 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) 1016 #include "ohci-pxa27x.c" 1017 #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver 1018 #endif 1019 1020 #ifdef CONFIG_ARCH_EP93XX 1021 #include "ohci-ep93xx.c" 1022 #define PLATFORM_DRIVER ohci_hcd_ep93xx_driver 1023 #endif 1024 1025 #ifdef CONFIG_SOC_AU1X00 1026 #include "ohci-au1xxx.c" 1027 #define PLATFORM_DRIVER ohci_hcd_au1xxx_driver 1028 #endif 1029 1030 #ifdef CONFIG_PNX8550 1031 #include "ohci-pnx8550.c" 1032 #define PLATFORM_DRIVER ohci_hcd_pnx8550_driver 1033 #endif 1034 1035 #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC 1036 #include "ohci-ppc-soc.c" 1037 #define PLATFORM_DRIVER ohci_hcd_ppc_soc_driver 1038 #endif 1039 1040 #ifdef CONFIG_ARCH_AT91 1041 #include "ohci-at91.c" 1042 #define PLATFORM_DRIVER ohci_hcd_at91_driver 1043 #endif 1044 1045 #ifdef CONFIG_ARCH_PNX4008 1046 #include "ohci-pnx4008.c" 1047 #define PLATFORM_DRIVER usb_hcd_pnx4008_driver 1048 #endif 1049 1050 #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 1051 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 1052 defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 1053 defined(CONFIG_CPU_SUBTYPE_SH7786) 1054 #include "ohci-sh.c" 1055 #define PLATFORM_DRIVER ohci_hcd_sh_driver 1056 #endif 1057 1058 1059 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF 1060 #include "ohci-ppc-of.c" 1061 #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver 1062 #endif 1063 1064 #ifdef CONFIG_PPC_PS3 1065 #include "ohci-ps3.c" 1066 #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver 1067 #endif 1068 1069 #ifdef CONFIG_USB_OHCI_HCD_SSB 1070 #include "ohci-ssb.c" 1071 #define SSB_OHCI_DRIVER ssb_ohci_driver 1072 #endif 1073 1074 #ifdef CONFIG_MFD_SM501 1075 #include "ohci-sm501.c" 1076 #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver 1077 #endif 1078 1079 #ifdef CONFIG_MFD_TC6393XB 1080 #include "ohci-tmio.c" 1081 #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver 1082 #endif 1083 1084 #if !defined(PCI_DRIVER) && \ 1085 !defined(PLATFORM_DRIVER) && \ 1086 !defined(OF_PLATFORM_DRIVER) && \ 1087 !defined(SA1111_DRIVER) && \ 1088 !defined(PS3_SYSTEM_BUS_DRIVER) && \ 1089 !defined(SM501_OHCI_DRIVER) && \ 1090 !defined(TMIO_OHCI_DRIVER) && \ 1091 !defined(SSB_OHCI_DRIVER) 1092 #error "missing bus glue for ohci-hcd" 1093 #endif 1094 1095 static int __init ohci_hcd_mod_init(void) 1096 { 1097 int retval = 0; 1098 1099 if (usb_disabled()) 1100 return -ENODEV; 1101 1102 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); 1103 pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name, 1104 sizeof (struct ed), sizeof (struct td)); 1105 set_bit(USB_OHCI_LOADED, &usb_hcds_loaded); 1106 1107 #ifdef DEBUG 1108 ohci_debug_root = debugfs_create_dir("ohci", NULL); 1109 if (!ohci_debug_root) { 1110 retval = -ENOENT; 1111 goto error_debug; 1112 } 1113 #endif 1114 1115 #ifdef PS3_SYSTEM_BUS_DRIVER 1116 retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER); 1117 if (retval < 0) 1118 goto error_ps3; 1119 #endif 1120 1121 #ifdef PLATFORM_DRIVER 1122 retval = platform_driver_register(&PLATFORM_DRIVER); 1123 if (retval < 0) 1124 goto error_platform; 1125 #endif 1126 1127 #ifdef OF_PLATFORM_DRIVER 1128 retval = of_register_platform_driver(&OF_PLATFORM_DRIVER); 1129 if (retval < 0) 1130 goto error_of_platform; 1131 #endif 1132 1133 #ifdef SA1111_DRIVER 1134 retval = sa1111_driver_register(&SA1111_DRIVER); 1135 if (retval < 0) 1136 goto error_sa1111; 1137 #endif 1138 1139 #ifdef PCI_DRIVER 1140 retval = pci_register_driver(&PCI_DRIVER); 1141 if (retval < 0) 1142 goto error_pci; 1143 #endif 1144 1145 #ifdef SSB_OHCI_DRIVER 1146 retval = ssb_driver_register(&SSB_OHCI_DRIVER); 1147 if (retval) 1148 goto error_ssb; 1149 #endif 1150 1151 #ifdef SM501_OHCI_DRIVER 1152 retval = platform_driver_register(&SM501_OHCI_DRIVER); 1153 if (retval < 0) 1154 goto error_sm501; 1155 #endif 1156 1157 #ifdef TMIO_OHCI_DRIVER 1158 retval = platform_driver_register(&TMIO_OHCI_DRIVER); 1159 if (retval < 0) 1160 goto error_tmio; 1161 #endif 1162 1163 return retval; 1164 1165 /* Error path */ 1166 #ifdef TMIO_OHCI_DRIVER 1167 platform_driver_unregister(&TMIO_OHCI_DRIVER); 1168 error_tmio: 1169 #endif 1170 #ifdef SM501_OHCI_DRIVER 1171 platform_driver_unregister(&SM501_OHCI_DRIVER); 1172 error_sm501: 1173 #endif 1174 #ifdef SSB_OHCI_DRIVER 1175 ssb_driver_unregister(&SSB_OHCI_DRIVER); 1176 error_ssb: 1177 #endif 1178 #ifdef PCI_DRIVER 1179 pci_unregister_driver(&PCI_DRIVER); 1180 error_pci: 1181 #endif 1182 #ifdef SA1111_DRIVER 1183 sa1111_driver_unregister(&SA1111_DRIVER); 1184 error_sa1111: 1185 #endif 1186 #ifdef OF_PLATFORM_DRIVER 1187 of_unregister_platform_driver(&OF_PLATFORM_DRIVER); 1188 error_of_platform: 1189 #endif 1190 #ifdef PLATFORM_DRIVER 1191 platform_driver_unregister(&PLATFORM_DRIVER); 1192 error_platform: 1193 #endif 1194 #ifdef PS3_SYSTEM_BUS_DRIVER 1195 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1196 error_ps3: 1197 #endif 1198 #ifdef DEBUG 1199 debugfs_remove(ohci_debug_root); 1200 ohci_debug_root = NULL; 1201 error_debug: 1202 #endif 1203 1204 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); 1205 return retval; 1206 } 1207 module_init(ohci_hcd_mod_init); 1208 1209 static void __exit ohci_hcd_mod_exit(void) 1210 { 1211 #ifdef TMIO_OHCI_DRIVER 1212 platform_driver_unregister(&TMIO_OHCI_DRIVER); 1213 #endif 1214 #ifdef SM501_OHCI_DRIVER 1215 platform_driver_unregister(&SM501_OHCI_DRIVER); 1216 #endif 1217 #ifdef SSB_OHCI_DRIVER 1218 ssb_driver_unregister(&SSB_OHCI_DRIVER); 1219 #endif 1220 #ifdef PCI_DRIVER 1221 pci_unregister_driver(&PCI_DRIVER); 1222 #endif 1223 #ifdef SA1111_DRIVER 1224 sa1111_driver_unregister(&SA1111_DRIVER); 1225 #endif 1226 #ifdef OF_PLATFORM_DRIVER 1227 of_unregister_platform_driver(&OF_PLATFORM_DRIVER); 1228 #endif 1229 #ifdef PLATFORM_DRIVER 1230 platform_driver_unregister(&PLATFORM_DRIVER); 1231 #endif 1232 #ifdef PS3_SYSTEM_BUS_DRIVER 1233 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1234 #endif 1235 #ifdef DEBUG 1236 debugfs_remove(ohci_debug_root); 1237 #endif 1238 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); 1239 } 1240 module_exit(ohci_hcd_mod_exit); 1241 1242